July 2008 - U-Boot

[U-Boot-Users] [PATCH] ppc4xx: Fix printf format warnings now visible with the updated format check
by Stefan Roese 10 Jul '08

10 Jul '08

This patch fixes ppc4xx related printf format warning. Those warnings are now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is really helpful. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/katmai/cmd_katmai.c | 4 ++-- board/esd/du440/du440.c | 4 ++-- board/lwmon5/sdram.c | 2 +- board/zeus/zeus.c | 2 +- cpu/ppc4xx/44x_spd_ddr2.c | 10 +++++----- cpu/ppc4xx/4xx_enet.c | 2 +- cpu/ppc4xx/denali_spd_ddr2.c | 8 ++++---- cpu/ppc4xx/tlb.c | 4 ++-- cpu/ppc4xx/traps.c | 26 +++++++++++++------------- 9 files changed, 31 insertions(+), 31 deletions(-) diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c index 439be4f..703d225 100644 --- a/board/amcc/katmai/cmd_katmai.c +++ b/board/amcc/katmai/cmd_katmai.c @@ -176,7 +176,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif } #ifdef DEBUG - printf(" pin strap0 to write in i2c = %x\n", data); + printf(" pin strap0 to write in i2c = %lx\n", data); #endif /* DEBUG */ if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) @@ -201,7 +201,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) data |= 0x05A50000; #ifdef DEBUG - printf(" pin strap1 to write in i2c = %x\n", data); + printf(" pin strap1 to write in i2c = %lx\n", data); #endif /* DEBUG */ udelay(1000); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 3dbb2e1..8765cc1 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -956,9 +956,9 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ret = run_command (cmd, 0); end = get_ticks(); - printf("ticks=%d\n", (ulong)(end - start)); + printf("ticks=%ld\n", (ulong)(end - start)); us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000)); - printf("usec=%d\n", us); + printf("usec=%ld\n", us); return ret; } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 0a13831..189e824 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -84,7 +84,7 @@ void board_add_ram_info(int use_default) puts(" (ECC not"); get_sys_info(&board_cfg); - printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000); + printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000); mfsdram(DDR0_03, val); val = DDR0_03_CASLAT_DECODE(val); diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 0113d48..33d971a 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -280,7 +280,7 @@ static int restore_default(void) } else { crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4); if (crc != *(u32 *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf); + printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf); return -1; } diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 9a5340c..a27e276 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -378,7 +378,7 @@ static phys_size_t sdram_memsize(void) mem_size+=4096; break; default: - printf("WARNING: Unsupported bank size (SDSZ=0x%x)!\n" + printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" , sdsz); mem_size=0; break; @@ -860,8 +860,8 @@ static void check_rank_number(unsigned long *dimm_populated, if (dimm_rank > MAXRANKS) { - printf("ERROR: DRAM DIMM detected with %d ranks in " - "slot %d is not supported.\n", dimm_rank, dimm_num); + printf("ERROR: DRAM DIMM detected with %lu ranks in " + "slot %lu is not supported.\n", dimm_rank, dimm_num); printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); printf("Replace the DIMM module with a supported DIMM.\n\n"); spd_ddr_init_hang (); @@ -1062,7 +1062,7 @@ static void program_copt1(unsigned long *dimm_populated, dimm_32bit = TRUE; break; default: - printf("WARNING: Detected a DIMM with a data width of %d bits.\n", + printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", data_width); printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n"); break; @@ -1615,7 +1615,7 @@ static void program_mode(unsigned long *dimm_populated, printf("Make sure the PLB speed is within the supported range of the DIMMs.\n"); printf("cas3=%d cas4=%d cas5=%d\n", cas_3_0_available, cas_4_0_available, cas_5_0_available); - printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n", + printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n", sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); spd_ddr_init_hang (); } diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index c40e0ca..4e863dc 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1076,7 +1076,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); if (!bd_cached) { - printf("%s: Error allocating MAL descriptor buffers!\n"); + printf("%s: Error allocating MAL descriptor buffers!\n", __func__); return -1; } diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 3bd6375..670fc5c 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -339,7 +339,7 @@ static void get_spd_info(unsigned long dimm_ranks[], "\n", dimm_num, ranks_on_dimm); if (ranks_on_dimm > max_ranks_per_dimm) { printf("WARNING: DRAM DIMM in slot %lu has %lu " - "ranks.\n"); + "ranks.\n", dimm_num, ranks_on_dimm); if (1 == max_ranks_per_dimm) { printf("Only one rank will be used.\n"); } else { @@ -668,8 +668,8 @@ static void program_ddr0_03(unsigned long dimm_ranks[], "and 5.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range " "of the DIMMs.\n"); - printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d " - "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk, + printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld " + "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); spd_ddr_init_hang(); } @@ -1248,7 +1248,7 @@ void board_add_ram_info(int use_default) if (!is_ecc_enabled()) { printf(" not"); } - printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000); + printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000); mfsdram(DDR0_03, val); printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1); diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index f44822d..24a9a9c 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -316,12 +316,12 @@ static void program_tlb_addr(u64 phys_addr, virt_addr += TLB_1KB_SIZE; } } else { - printf("ERROR: no TLB size exists for the base address 0x%0X.\n", + printf("ERROR: no TLB size exists for the base address 0x%llx.\n", phys_addr); } if (rc != 0) - printf("ERROR: no TLB entries available for the base addr 0x%0X.\n", + printf("ERROR: no TLB entries available for the base addr 0x%llx.\n", phys_addr); } diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 8b7e32a..55154b6 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -214,7 +214,7 @@ MachineCheckException(struct pt_regs *regs) } #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) mfsdram(DDR0_00, val) ; - printf("DDR0: DDR0_00 %p\n", val); + printf("DDR0: DDR0_00 %lx\n", val); val = (val >> 16) & 0xff; if (val & 0x80) printf("DDR0: At least one interrupt active\n"); @@ -263,44 +263,44 @@ MachineCheckException(struct pt_regs *regs) break; default: mfsdram(DDR0_01, value2); - printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2); + printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2); } mfsdram(DDR0_23, val); if (((val >> 16) & 0xff) && corr_ecc) - printf("DDR0: Syndrome for correctable ECC event 0x%x\n", + printf("DDR0: Syndrome for correctable ECC event 0x%lx\n", (val >> 16) & 0xff); mfsdram(DDR0_23, val); if (((val >> 8) & 0xff) && uncorr_ecc) - printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n", + printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n", (val >> 8) & 0xff); mfsdram(DDR0_33, val); if (val) printf("DDR0: Address of command that caused an " - "Out-of-Range interrupt %p\n", val); + "Out-of-Range interrupt %lx\n", val); mfsdram(DDR0_34, val); if (val && uncorr_ecc) - printf("DDR0: Address of uncorrectable ECC event %p\n", val); + printf("DDR0: Address of uncorrectable ECC event %lx\n", val); mfsdram(DDR0_35, val); if (val && uncorr_ecc) - printf("DDR0: Address of uncorrectable ECC event %p\n", val); + printf("DDR0: Address of uncorrectable ECC event %lx\n", val); mfsdram(DDR0_36, val); if (val && uncorr_ecc) - printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); + printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val); mfsdram(DDR0_37, val); if (val && uncorr_ecc) - printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); + printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val); mfsdram(DDR0_38, val); if (val && corr_ecc) - printf("DDR0: Address of correctable ECC event %p\n", val); + printf("DDR0: Address of correctable ECC event %lx\n", val); mfsdram(DDR0_39, val); if (val && corr_ecc) - printf("DDR0: Address of correctable ECC event %p\n", val); + printf("DDR0: Address of correctable ECC event %lx\n", val); mfsdram(DDR0_40, val); if (val && corr_ecc) - printf("DDR0: Data of correctable ECC event 0x%08x\n", val); + printf("DDR0: Data of correctable ECC event 0x%08lx\n", val); mfsdram(DDR0_41, val); if (val && corr_ecc) - printf("DDR0: Data of correctable ECC event 0x%08x\n", val); + printf("DDR0: Data of correctable ECC event 0x%08lx\n", val); #endif /* CONFIG_440EPX */ #endif /* CONFIG_440 */ show_regs(regs); -- 1.5.6.2

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[U-Boot-Users] [PATCH] Fix boot from NOR due to incorrect reset delay.
by Stelian Pop 10 Jul '08

10 Jul '08

AT91 RSTC registers are battery-backuped, so their values are not reset across power cycles. One of those registers, the AT91_RSTC_MR register, is being modified by U-Boot, in the ethernet initialisation routine, to generate a 500ms user reset. Unfortunately, this value is not being restored afterwards, causing subsequent resets to also last for 500ms. This long reset sequence causes problems (at least) in the boot sequence from NOR: by the time the CPU tries to load a program from the NOR flash, the latter is still in reset and not yet available. Additionaly, this patch fixes a bug in the original code which caused the reset delay to last for 2s instead of 500ms. Signed-off-by: Stelian Pop <stelian(a)popies.net> --- This patch applies on top of the latest AT91 patches, as integrated in the testing-V2 branch of the u-boot-at91 repository. board/atmel/at91cap9adk/at91cap9adk.c | 7 ++++++- board/atmel/at91sam9260ek/at91sam9260ek.c | 4 ++-- board/atmel/at91sam9263ek/at91sam9263ek.c | 7 ++++++- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index a3eaf19..c5082a0 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -196,7 +196,7 @@ static void at91cap9_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -204,6 +204,11 @@ static void at91cap9_macb_hw_init(void) /* Wait for end hardware reset */ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PB22) | pin_to_mask(AT91_PIN_PB25) | diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 4635f0f..3572b16 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -149,7 +149,7 @@ static void at91sam9260ek_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -159,7 +159,7 @@ static void at91sam9260ek_macb_hw_init(void) /* Restore NRST value */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0 << 8) | + (AT91_RSTC_ERSTL & (0x0 << 8)) | AT91_RSTC_URSTEN); /* Re-enable pull-up */ diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index ba7fc71..169ee25 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -147,7 +147,7 @@ static void at91sam9263ek_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -155,6 +155,11 @@ static void at91sam9263ek_macb_hw_init(void) /* Wait for end hardware reset */ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PC25), pin_to_controller(AT91_PIN_PC0) + PIO_PUER); -- 1.5.3.3

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[U-Boot-Users] [PATCH] pp44xx: Remove implementation of testdram() from Korat board support
by Larry Johnson 10 Jul '08

10 Jul '08

Signed-off-by: Larry Johnson <lrj(a)acm.org> --- This patch requires the previously-submitted patch for these files. board/korat/korat.c | 38 -------------------------------------- include/configs/korat.h | 1 - 2 files changed, 0 insertions(+), 39 deletions(-) diff --git a/board/korat/korat.c b/board/korat/korat.c index dc97724..51874ea 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -569,44 +569,6 @@ int checkboard(void) return 0; } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - /* TODO: find correct size of SDRAM */ - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) - printf("%3d MB\r", k / 1024); - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif /* defined(CFG_DRAM_TEST) */ - #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) /* * Assign interrupts to PCI devices. diff --git a/include/configs/korat.h b/include/configs/korat.h index e2610be..4ca4ed0 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -145,7 +145,6 @@ #define CONFIG_DDR_ECC /* Use ECC when available */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB -#define CFG_DRAM_TEST #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */

2 1

[U-Boot-Users] [PATCH] ppc4xx: Update and add FDT to Korat board support
by Larry Johnson 10 Jul '08

10 Jul '08

Signed-off-by: Larry Johnson <lrj(a)acm.org> --- board/korat/korat.c | 42 ++++++++++++++++++++++++++++++++++++++++-- include/configs/korat.h | 10 +++++++--- 2 files changed, 47 insertions(+), 5 deletions(-) diff --git a/board/korat/korat.c b/board/korat/korat.c index a7b4b27..dc97724 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -26,12 +26,15 @@ */ #include <common.h> +#include <fdt_support.h> #include <i2c.h> +#include <libfdt.h> #include <ppc440.h> +#include <asm/bitops.h> #include <asm/gpio.h> -#include <asm/processor.h> #include <asm/io.h> -#include <asm/bitops.h> +#include <asm/ppc4xx-intvec.h> +#include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -604,6 +607,16 @@ int testdram(void) } #endif /* defined(CFG_DRAM_TEST) */ +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. + */ +void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); +} +#endif + /* * pci_pre_init * @@ -654,6 +667,10 @@ int pci_pre_init(struct pci_controller *hose) addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); +#if defined(CONFIG_PCI_PNP) + hose->fixup_irq = korat_pci_fixup_irq; +#endif + return 1; } #endif /* defined(CONFIG_PCI) */ @@ -779,3 +796,24 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 1; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 7655666..e2610be 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -129,7 +129,7 @@ #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) @@ -185,7 +185,7 @@ #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ CFG_BOOTFILE \ CFG_ROOTPATH \ "netdev=eth0\0" \ @@ -216,7 +216,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ #define CONFIG_PHY_DYNAMIC_ANEG 1 @@ -548,4 +548,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */

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Re: [U-Boot-Users] [PATCH] at91: Fix to enable using Teridian MII phy (78Q21x3) with at91sam9260
by Anatolij Gustschin 10 Jul '08

10 Jul '08

Manuel Sahm wrote: > if I apply the patch with: > > patch -p1 < patchat91.diff > > some messages occur, is this correct ? > > > (Stripping trailing CRs from patch.) > patching file board/atmel/at91sam9260ek/at91sam9260ek.c > patch unexpectedly ends in middle of line > Hunk #1 succeeded at 183 with fuzz 2 (offset -5 lines). it is very likely that these messages occur because the patch was incorrectly saved from the email body. This patch applies cleanly against top of our u-boot git tree. > The description is correct - PA23 and PA24 are connected to the TWI > EEPROM an the DevBoard at91sam9260ek. > The patch works well. > Here the signed-off line: > > Signed-off-by: Manuel Sahm <Manuel.Sahm(a)feig.de> Thanks, I will repost the patch again. > Another problem is, that the same error is in the official kernel tree > in the file at91sam9260ek_devices.c ?! > Although the error is still in the kernel, a modification of the uboot > file at91sam9260ek.c is enough to get ethernet working ? if the kernel resets Peripheral B pin configuration, then ethernet will stop working, I think. This should be fixed in the kernel code, too. Best regards, Anatolij

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[U-Boot-Users] please ignore
by Feng Kan 10 Jul '08

10 Jul '08

1 0

[U-Boot-Users] Undelivered Mail Returned to Sender
by MAILER-DAEMON＠efw-budpar.budpar.go.id 10 Jul '08

10 Jul '08

This is the mail system at host efw-budpar.budpar.go.id. I'm sorry to have to inform you that your message could not be delivered to one or more recipients. It's attached below. For further assistance, please send mail to <postmaster> If you do so, please include this problem report. You can delete your own text from the attached returned message. The mail system <madmax(a)hotmail.com>: host mx3.hotmail.com[65.54.245.72] said: 550 Requested action not taken: mailbox unavailable (in reply to RCPT TO command)

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[U-Boot-Users] Undelivered Mail Returned to Sender
by MAILER-DAEMON＠efw-budpar.budpar.go.id 10 Jul '08

10 Jul '08

This is the mail system at host efw-budpar.budpar.go.id. I'm sorry to have to inform you that your message could not be delivered to one or more recipients. It's attached below. For further assistance, please send mail to <postmaster> If you do so, please include this problem report. You can delete your own text from the attached returned message. The mail system <maria(a)colomboscuba.com>: host mx01.1and1.com[74.208.5.4] said: 550 <maria(a)colomboscuba.com>: invalid address (in reply to RCPT TO command)

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[U-Boot-Users] Undelivered Mail Returned to Sender
by MAILER-DAEMON＠efw-budpar.budpar.go.id 10 Jul '08

10 Jul '08

This is the mail system at host efw-budpar.budpar.go.id. I'm sorry to have to inform you that your message could not be delivered to one or more recipients. It's attached below. For further assistance, please send mail to <postmaster> If you do so, please include this problem report. You can delete your own text from the attached returned message. The mail system <julie(a)jakarta.apache.org>: host mx1.us.apache.org[140.211.11.136] said: 552 Message rejected as it is spam (body) (in reply to end of DATA command)

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[U-Boot-Users] [PATCH] sh: add support for SH7785
by Yoshihiro Shimoda 10 Jul '08

10 Jul '08

Renesas SH7785 has DDR2-SDRAM controller, PCI, and other. This patch supports CPU register's header file. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> --- include/asm-sh/cpu_sh4.h | 2 + include/asm-sh/cpu_sh7785.h | 156 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+), 0 deletions(-) create mode 100644 include/asm-sh/cpu_sh7785.h diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index 5a8a5a1..de6eb5a 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -39,6 +39,8 @@ # include <asm/cpu_sh7763.h> #elif defined (CONFIG_CPU_SH7780) # include <asm/cpu_sh7780.h> +#elif defined (CONFIG_CPU_SH7785) +# include <asm/cpu_sh7785.h> #else # error "Unknown SH4 variant" #endif diff --git a/include/asm-sh/cpu_sh7785.h b/include/asm-sh/cpu_sh7785.h new file mode 100644 index 0000000..ec42bc6 --- /dev/null +++ b/include/asm-sh/cpu_sh7785.h @@ -0,0 +1,156 @@ +#ifndef _ASM_CPU_SH7785_H_ +#define _ASM_CPU_SH7785_H_ + +/* + * Copyright (c) 2007,2008 Nobuhiro Iwamatsu + * Copyright (c) 2008 Yusuke Goda <goda.yusuke(a)renesas.com> + * Copyright (c) 2008 Yoshihiro Shimoda <goda.yusuke(a)renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#define CACHE_OC_NUM_WAYS 1 +#define CCR_CACHE_INIT 0x0000090b + +/* Exceptions */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* Cache Controller */ +#define CCR 0xFF00001C +#define QACR0 0xFF000038 +#define QACR1 0xFF00003C +#define RAMCR 0xFF000074 + +/* Watchdog Timer and Reset */ +#define WTCNT WDTCNT +#define WDTST 0xFFCC0000 +#define WDTCSR 0xFFCC0004 +#define WDTBST 0xFFCC0008 +#define WDTCNT 0xFFCC0010 +#define WDTBCNT 0xFFCC0018 + +/* Timer Unit */ +#define TSTR TSTR0 +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 +#define TCPR2 0xFFD8002C +#define TSTR1 0xFFDC0004 +#define TCOR3 0xFFDC0008 +#define TCNT3 0xFFDC000C +#define TCR3 0xFFDC0010 +#define TCOR4 0xFFDC0014 +#define TCNT4 0xFFDC0018 +#define TCR4 0xFFDC001C +#define TCOR5 0xFFDC0020 +#define TCNT5 0xFFDC0024 +#define TCR5 0xFFDC0028 + +/* Serial Communication Interface with FIFO */ +#define SCIF1_BASE 0xffeb0000 + +/* LBSC */ +#define MMSELR 0xfc400020 +#define LBSC_BASE 0xff800000 +#define BCR (LBSC_BASE + 0x1000) +#define CS0BCR (LBSC_BASE + 0x2000) +#define CS1BCR (LBSC_BASE + 0x2010) +#define CS2BCR (LBSC_BASE + 0x2020) +#define CS3BCR (LBSC_BASE + 0x2030) +#define CS4BCR (LBSC_BASE + 0x2040) +#define CS5BCR (LBSC_BASE + 0x2050) +#define CS6BCR (LBSC_BASE + 0x2060) +#define CS0WCR (LBSC_BASE + 0x2008) +#define CS1WCR (LBSC_BASE + 0x2018) +#define CS2WCR (LBSC_BASE + 0x2028) +#define CS3WCR (LBSC_BASE + 0x2038) +#define CS4WCR (LBSC_BASE + 0x2048) +#define CS5WCR (LBSC_BASE + 0x2058) +#define CS6WCR (LBSC_BASE + 0x2068) +#define CS5PCR (LBSC_BASE + 0x2070) +#define CS6PCR (LBSC_BASE + 0x2080) + +/* PCI Controller */ +#define SH7780_PCIECR 0xFE000008 +#define SH7780_PCIVID 0xFE040000 +#define SH7780_PCIDID 0xFE040002 +#define SH7780_PCICMD 0xFE040004 +#define SH7780_PCISTATUS 0xFE040006 +#define SH7780_PCIRID 0xFE040008 +#define SH7780_PCIPIF 0xFE040009 +#define SH7780_PCISUB 0xFE04000A +#define SH7780_PCIBCC 0xFE04000B +#define SH7780_PCICLS 0xFE04000C +#define SH7780_PCILTM 0xFE04000D +#define SH7780_PCIHDR 0xFE04000E +#define SH7780_PCIBIST 0xFE04000F +#define SH7780_PCIIBAR 0xFE040010 +#define SH7780_PCIMBAR0 0xFE040014 +#define SH7780_PCIMBAR1 0xFE040018 +#define SH7780_PCISVID 0xFE04002C +#define SH7780_PCISID 0xFE04002E +#define SH7780_PCICP 0xFE040034 +#define SH7780_PCIINTLINE 0xFE04003C +#define SH7780_PCIINTPIN 0xFE04003D +#define SH7780_PCIMINGNT 0xFE04003E +#define SH7780_PCIMAXLAT 0xFE04003F +#define SH7780_PCICID 0xFE040040 +#define SH7780_PCINIP 0xFE040041 +#define SH7780_PCIPMC 0xFE040042 +#define SH7780_PCIPMCSR 0xFE040044 +#define SH7780_PCIPMCSRBSE 0xFE040046 +#define SH7780_PCI_CDD 0xFE040047 +#define SH7780_PCICR 0xFE040100 +#define SH7780_PCILSR0 0xFE040104 +#define SH7780_PCILSR1 0xFE040108 +#define SH7780_PCILAR0 0xFE04010C +#define SH7780_PCILAR1 0xFE040110 +#define SH7780_PCIIR 0xFE040114 +#define SH7780_PCIIMR 0xFE040118 +#define SH7780_PCIAIR 0xFE04011C +#define SH7780_PCICIR 0xFE040120 +#define SH7780_PCIAINT 0xFE040130 +#define SH7780_PCIAINTM 0xFE040134 +#define SH7780_PCIBMIR 0xFE040138 +#define SH7780_PCIPAR 0xFE0401C0 +#define SH7780_PCIPINT 0xFE0401CC +#define SH7780_PCIPINTM 0xFE0401D0 +#define SH7780_PCIMBR0 0xFE0401E0 +#define SH7780_PCIMBMR0 0xFE0401E4 +#define SH7780_PCIMBR1 0xFE0401E8 +#define SH7780_PCIMBMR1 0xFE0401EC +#define SH7780_PCIMBR2 0xFE0401F0 +#define SH7780_PCIMBMR2 0xFE0401F4 +#define SH7780_PCIIOBR 0xFE0401F8 +#define SH7780_PCIIOBMR 0xFE0401FC +#define SH7780_PCICSCR0 0xFE040210 +#define SH7780_PCICSCR1 0xFE040214 +#define SH7780_PCICSAR0 0xFE040218 +#define SH7780_PCICSAR1 0xFE04021C +#define SH7780_PCIPDR 0xFE040220 + +#endif /* _ASM_CPU_SH7780_H_ */

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