March 2008 - U-Boot

[U-Boot-Users] All your gay issues solved
by fazeel ceniccola 11 Mar '08

11 Mar '08

Whet your partner's appetite for sex with our amazing new product

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[U-Boot-Users] MPC8548E 4G SDRAM support
by Subbu Linux 11 Mar '08

11 Mar '08

Hi Guys, I posted couple of days back in linux-ppc to know whether its possible to support 4GB SDRAM in u-boot and Linux using the 36bit Physical address suport provided by e500v2 core, though i tried in u-boot moving SDRAM base address at 0x1_0000_0000, I found that Ethernet driver is not working, may be Buffer descritors are not able to get base address of the ram as it assumes to be RAM with in 4GB. I need some key pointers. I am also open if someone is confident in PPC u-boot and want to join me in executing this as project. Thanks, Subbu

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[U-Boot-Users] [PATCH 0/9] ppc4xx: Add AMCC 460EX Canyonlands support
by Stefan Roese 11 Mar '08

11 Mar '08

This patchseries adds support for the new AMCC Canyonlands eval board based on the PPC460EX. Here a short summary of this board/cpu: 460EX: - Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU - 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane) - 2 * GBit Ethernet with TCP/IP acceleration - USB 2.0 Host/Device OTG and Host interface - SATA controller - Optional security feature 460GT (only changes to 460EX): - 4 * GBit Ethernet with TCP/IP acceleration - RapidIO - No SATA - No USB Canyonlands is the AMCC 460EX eval board, featuring nearly all of the 460EX interfaces: - 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane) - 2 * GBit Ethernet with TCP/IP acceleration - USB 2.0 Host/Device OTG and Host interface - SATA port I'll commit there changes to the master branch of the u-boot-ppc4xx custodian repository and send a pull request in a few days, if nobody has any objections. Thanks. Best regards, Stefan

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[U-Boot-Users] [PATCH] 83xx: Add support for CFG_I2C_SPEED in fsl_i2c.c
by Timur Tabi 11 Mar '08

11 Mar '08

Add support to fsl_i2c.c for setting and querying the I2C bus speed. Current 83xx boards define the CFG_I2C_SPEED, but fsl_i2c.c ignores the value and uses a conservative value of 0x3F when programming the I2C bus speed. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- Unfortunately, only 83xx calculates and stores the I2C clock frequencies, so this code is compiled on 83xx only. cpu/mpc83xx/cpu.c | 24 +++++++++++ drivers/i2c/fsl_i2c.c | 90 ++++++++++++++++++++++++++++++++++++++++- include/asm-ppc/fsl_i2c.h | 23 ++++++++++ include/configs/MPC832XEMDS.h | 1 + 4 files changed, 137 insertions(+), 1 deletions(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index f1ea17d..51cb1b7 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -716,3 +716,27 @@ int dma_xfer(void *dest, u32 count, void *src) return ((int)dma_check()); } #endif /*CONFIG_DDR_ECC*/ + +#ifdef CFG_I2C_SPEED +/* + * Map the frequency divider to the FDR. This data is taken from table 17-5 + * of the MPC8349EA reference manual, with duplicates removed. It also applies + * to the 8360. + */ +struct fsl_i2c_speed_map fsl_i2c_speed_map[] = { + {256, 0x20}, {288, 0x21}, {320, 0x22}, {352, 0x23}, + {384, 0x24}, {416, 0x01}, {448, 0x25}, {480, 0x02}, + {512, 0x26}, {576, 0x27}, {640, 0x28}, {704, 0x05}, + {768, 0x29}, {832, 0x06}, {896, 0x2A}, {1024, 0x2B}, + {1152, 0x08}, {1280, 0x2C}, {1536, 0x2D}, {1792, 0x2E}, + {1920, 0x0B}, {2048, 0x2F}, {2304, 0x0C}, {2560, 0x30}, + {3072, 0x31}, {3584, 0x32}, {3840, 0x0F}, {4096, 0x33}, + {4608, 0x10}, {5120, 0x34}, {6144, 0x35}, {7168, 0x36}, + {7680, 0x13}, {8192, 0x37}, {9216, 0x14}, {10240, 0x38}, + {12288, 0x39}, {14336, 0x3A}, {15360, 0x17}, {16384, 0x3B}, + {18432, 0x18}, {20480, 0x3C}, {24576, 0x3D}, {28672, 0x3E}, + {30720, 0x1B}, {32768, 0x3F}, {36864, 0x1C}, {40960, 0x1D}, + {49152, 0x1E}, {61440, 0x1F}, + {-1, 0x1F} +}; +#endif diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 22485ea..bca2c75 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -32,6 +32,8 @@ #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 +DECLARE_GLOBAL_DATA_PTR; + /* Initialize the bus pointer to whatever one the SPD EEPROM is on. * Default is bus 0. This is necessary because the DDR initialization * runs from ROM, and we can't switch buses because we can't modify @@ -43,6 +45,8 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; #endif +static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; + static volatile struct fsl_i2c *i2c_dev[2] = { (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), #ifdef CFG_I2C2_OFFSET @@ -50,6 +54,53 @@ static volatile struct fsl_i2c *i2c_dev[2] = { #endif }; +#ifdef CONFIG_MPC83XX +/* Currently, only 83xx determines and stores the I2C clock frequency */ + +#ifdef CFG_I2C_SPEED +/* Define a default I2C speed map if a real map isn't defined elsewhere */ +#pragma weak fsl_i2c_speed_map = default_fsl_i2c_speed_map + +struct fsl_i2c_speed_map default_fsl_i2c_speed_map[] = { + {0, 0x3F}, {-1, 0x3F} +}; +#endif + +/* + * Get the I2C FDR value for a given I2C clock and a given I2C bus speed + */ +static u8 get_fdr(unsigned int i2c_clk, unsigned int speed) +{ +#ifdef CFG_I2C_SPEED + extern struct fsl_i2c_speed_map fsl_i2c_speed_map[]; + unsigned int d; /* The I2C clock divider */ + unsigned int i = 0; + unsigned int low, high; + + d = i2c_clk / speed; + + /* Scan fsl_i2c_speed_map[] for the closest matching divider.*/ + + while (fsl_i2c_speed_map[i].divider != (unsigned int) -1) { + low = fsl_i2c_speed_map[i].divider; + high = fsl_i2c_speed_map[i+1].divider; + + if ((d >= low) && (d <= high)) { + /* Which one is closer? */ + if ((d - low) < (high - d)) + return fsl_i2c_speed_map[i].fdr; + else + return fsl_i2c_speed_map[i+1].fdr; + break; + } + i++; + } +#endif + + return 0x3F; /* Use a conservative value as the default */ +} +#endif /* CONFIG_MPC83XX */ + void i2c_init(int speed, int slaveadd) { @@ -59,23 +110,37 @@ i2c_init(int speed, int slaveadd) writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + writeb(get_fdr(gd->i2c1_clk, speed), &dev->fdr); /* set bus speed */ +#else writeb(0x3F, &dev->fdr); /* set bus speed */ +#endif writeb(0x3F, &dev->dfsrr); /* set default filter */ writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ + i2c_bus_speed[0] = speed; + #ifdef CFG_I2C2_OFFSET dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + writeb(get_fdr(gd->i2c2_clk, speed), &dev->fdr); /* set bus speed */ +#else writeb(0x3F, &dev->fdr); /* set bus speed */ +#endif writeb(0x3F, &dev->dfsrr); /* set default filter */ writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -#endif /* CFG_I2C2_OFFSET */ + + i2c_bus_speed[1] = speed; +#endif } static __inline__ int @@ -279,7 +344,23 @@ int i2c_set_bus_num(unsigned int bus) int i2c_set_bus_speed(unsigned int speed) { +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + + unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; + u8 fdr = get_fdr(i2c_clk, speed); + + printf("Writing %x to FDR\n", fdr); + writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ + writeb(fdr, &i2c_dev[i2c_bus_num]->fdr); /* set bus speed */ + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ + + i2c_bus_speed[i2c_bus_num] = speed; + + return 0; +#else return -1; +#endif } unsigned int i2c_get_bus_num(void) @@ -289,7 +370,14 @@ unsigned int i2c_get_bus_num(void) unsigned int i2c_get_bus_speed(void) { +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + + return i2c_bus_speed[i2c_bus_num]; +#else return 0; +#endif } + #endif /* CONFIG_HARD_I2C */ #endif /* CONFIG_FSL_I2C */ diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h index 4f71341..f84a803 100644 --- a/include/asm-ppc/fsl_i2c.h +++ b/include/asm-ppc/fsl_i2c.h @@ -83,4 +83,27 @@ typedef struct fsl_i2c { u8 res6[0xE8]; } fsl_i2c_t; +/* + * Map I2C frequency dividers to FDR values + * + * This structure is used to define the elements of a table that maps I2C + * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be + * programmed into the Frequency Divider Ratio (FDR) register. + * + * The actual table should be defined in the board file, and it must be called + * fsl_i2c_speed_map[]. + * + * The first entry must be {0, X}, where X == fsl_i2c_speed_map[1].fdr. + * + * The last entry of the table must have a value of {-1,x}, where x is same + * FDR value as the second-to-last entry. + * + * The values of the divider must be in increasing numerical order, i.e. + * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. + */ +typedef struct fsl_i2c_speed_map { + unsigned int divider; + u8 fdr; +} fsl_i2c_speed_map_t; + #endif /* _ASM_I2C_H_ */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index c9c6d88..d5e588a 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -335,6 +335,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CONFIG_I2C_CMD_TREE /* * Config on-board RTC -- 1.5.2.4

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[U-Boot-Users] [PATCH 1/9] rtc: Add M41T62 support
by Stefan Roese 11 Mar '08

11 Mar '08

This patch add support for the STM M41T62 RTC. It is used and tested on the AMCC Canyonlands 406EX platform. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/rtc/Makefile | 1 + drivers/rtc/m41t62.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/m41t62.c diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af2bf4..17c0f86 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -41,6 +41,7 @@ COBJS-y += ds174x.o COBJS-y += ds3231.o COBJS-y += m41t11.o COBJS-y += m41t60.o +COBJS-y += m41t62.o COBJS-y += max6900.o COBJS-y += m48t35ax.o COBJS-y += mc146818.o diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c new file mode 100644 index 0000000..002ebba --- /dev/null +++ b/drivers/rtc/m41t62.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * based on a the Linux rtc-m41t80.c driver which is: + * Alexander Bigga <ab(a)mycable.de>, 2006 (c) mycable GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for STMicroelectronics M41T62 + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> +#include <bcd.h> + +#if defined(CONFIG_RTC_M41T62) && defined(CONFIG_CMD_DATE) + +#define M41T62_REG_SSEC 0 +#define M41T62_REG_SEC 1 +#define M41T62_REG_MIN 2 +#define M41T62_REG_HOUR 3 +#define M41T62_REG_WDAY 4 +#define M41T62_REG_DAY 5 +#define M41T62_REG_MON 6 +#define M41T62_REG_YEAR 7 +#define M41T62_REG_ALARM_MON 0xa +#define M41T62_REG_ALARM_DAY 0xb +#define M41T62_REG_ALARM_HOUR 0xc +#define M41T62_REG_ALARM_MIN 0xd +#define M41T62_REG_ALARM_SEC 0xe +#define M41T62_REG_FLAGS 0xf + +#define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1) +#define M41T62_ALARM_REG_SIZE \ + (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON) + +#define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */ +#define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */ +#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */ +#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ +#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */ +#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */ + +#define M41T62_FEATURE_HT (1 << 0) +#define M41T62_FEATURE_BL (1 << 1) + +void rtc_get(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + + debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " + "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", + __FUNCTION__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + tm->tm_sec = BCD2BIN(buf[M41T62_REG_SEC] & 0x7f); + tm->tm_min = BCD2BIN(buf[M41T62_REG_MIN] & 0x7f); + tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f); + tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f); + tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; + tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1; + + /* assume 20YY not 19YY, and ignore the Century Bit */ + /* U-Boot needs to add 1900 here */ + tm->tm_year = BCD2BIN(buf[M41T62_REG_YEAR]) + 100 + 1900; + + debug("%s: tm is secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __FUNCTION__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); +} + +void rtc_set(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + + /* Merge time-data and register flags into buf[0..7] */ + buf[M41T62_REG_SSEC] = 0; + buf[M41T62_REG_SEC] = + BIN2BCD(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f); + buf[M41T62_REG_MIN] = + BIN2BCD(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f); + buf[M41T62_REG_HOUR] = + BIN2BCD(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ; + buf[M41T62_REG_WDAY] = + (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07); + buf[M41T62_REG_DAY] = + BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); + buf[M41T62_REG_MON] = + BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f); + /* assume 20YY not 19YY */ + buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); + + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) + printf("I2C write failed in %s()\n", __func__); +} + +void rtc_reset(void) +{ + /* + * Nothing to do + */ +} + +#endif -- 1.5.4.4

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[U-Boot-Users] [PATCH] ppc4xx: Fix comment in 405EX DDR2 init code
by Stefan Roese 11 Mar '08

11 Mar '08

Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/kilauea/init.S | 4 ++-- board/amcc/makalu/init.S | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S index 4338744..053fe19 100644 --- a/board/amcc/kilauea/init.S +++ b/board/amcc/kilauea/init.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * Based on code provided from UDTech and AMCC @@ -64,7 +64,7 @@ ext_bus_cntlr_init: /* SET SDRAM_MB3CF - Not enabled */ mtsdram_as(SDRAM_MB3CF, 0x00000000); - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ mtsdram_as(SDRAM_CLKTR, 0x80000000); /* Refresh Time register (0x30) Refresh every 7.8125uS */ diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 57c1774..5e9a5e0 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * Based on code provided from Senao and AMCC @@ -57,7 +57,7 @@ ext_bus_cntlr_init: /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ mtsdram_as(SDRAM_CLKTR,0x80000000); /* Refresh Time register (0x30) Refresh every 7.8125uS */ -- 1.5.4.4

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[U-Boot-Users] [PATCH] sh: Updated support for MPR2 board (SH7720)
by Mark Jonas 11 Mar '08

11 Mar '08

Hello, the attached patch replaces the patch I sent before. I added myself to the list of board maintainers and diffed against U-Boot git from this morning, i.e. v1.3.2. The attached patch adds support for the Renesas SH7720 based board MPR2. Regards, Mark Jonas CHANGELOG: ---------- sh: Added support for SH7720 based board MPR2. Signed-off-by: Mark Jonas <mark.jonas(a)de.bosch.com>

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[U-Boot-Users] [PATCH] sh: Fix receive FIFO level register of SH4A
by Nobuhiro Iwamatsu 11 Mar '08

11 Mar '08

Receive FIFO level register is different in SH4A. Because register is different, cannot occasionally receive data. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/serial/serial_sh.c | 52 +++++++++++++++++++++++++------------------ 1 files changed, 30 insertions(+), 22 deletions(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index ecb97bf..8ee58a0 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -37,41 +37,45 @@ #define SCFCR (vu_short *)(SCIF_BASE + 0x18) #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ -#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ -#define SCFTDR (vu_char *)(SCIF_BASE + 0x20) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x24) +# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +# define SCFTDR (vu_char *)(SCIF_BASE + 0x20) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else -#define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -#define SCFSR (vu_short *)(SCIF_BASE + 0x10) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x14) +# define SCFTDR (vu_char *)(SCIF_BASE + 0xC) +# define SCFSR (vu_short *)(SCIF_BASE + 0x10) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x14) #endif #if defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7785) -#define SCRFDR (vu_short *)(SCIF_BASE + 0x20) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x24) -#define SCLSR (vu_short *)(SCIF_BASE + 0x28) -#define SCRER (vu_short *)(SCIF_BASE + 0x2C) -#define LSR_ORER 1 +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x28) +# define SCRER (vu_short *)(SCIF_BASE + 0x2C) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0xFF #elif defined(CONFIG_CPU_SH7750) || \ defined(CONFIG_CPU_SH7722) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#define LSR_ORER 1 +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7720) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#define LSR_ORER 0x0200 +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 0x0200 +# define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7710) defined(CONFIG_CPU_SH7712) -#define SCLSR SCFSR /* SCSSR */ -#define LSR_ORER 1 +# define SCLSR SCFSR /* SCSSR */ +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F #endif /* SCBRR register value setting */ #if defined(CONFIG_CPU_SH7720) -#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #else /* Generic SuperH */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif #define SCR_RE (1 << 4) @@ -109,12 +113,16 @@ int serial_init (void) static int serial_tx_fifo_level (void) { - return (*SCFDR >> 8) & 0x1F; + return (*SCFDR >> 8) & FIFOLEVEL_MASK; } static int serial_rx_fifo_level (void) { - return (*SCFDR >> 0) & 0x1F; +#if defined(CONFIG_SH4A) + return (*SCRFDR >> 0) & FIFOLEVEL_MASK; +#else + return (*SCFDR >> 0) & FIFOLEVEL_MASK; +#endif } void serial_raw_putc (const char c) -- 1.5.3.8

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[U-Boot-Users] Fiona and her broken hymen
by Abodi Reidt 10 Mar '08

10 Mar '08

Stop depriving yourself of good sex - click here

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Re: [U-Boot-Users] Flash write crash on MPC8548CDS
by Andy Fleming 10 Mar '08

10 Mar '08

> It is too late today but tomorrow I will try to write something in Flash > with cp.b and check if this still happens. > > Everything works OK with the old U-Boot that came with CDS though... Ok, I found the problem. Check my tree (u-boot-mpc85xx.git) now. It's got a patch which removes the mappings for INIT_RAM, thus preventing speculative loads from going out on the bus. Andy

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