March 2008 - U-Boot

[U-Boot-Users] console kernel parameter problem
by Fabio Ubaldi 14 Mar '08

14 Mar '08

Hi all, I'm working with a board with a MPC8548 processor. I built the uboot (version 1.3.0), the DTS file (myboard.dtb) and a kernel 2.6.21 . When I try to boot the kernel via NFS I have some exception mode when parsing the kernel parameters. Specifically I obtained an error during the parsing of "console" parameter. My host computer is connected to the board via console using a standard 8250 port. I append the log in this post. Has anyone any suggestion? Thanks in advance for the reply. root=/dev/nfs rw nfsroot=192.168.0.90:/home/ftpuser/workspace/rootfs ip=192.168.0.11:192.168.0.90:192.168.0.90:255.255.255.0:MYBOARD:eth2:off console=ttyS1,115200 => => => run nfsboot Enet starting in 1000BT/FD Speed: 1000, full duplex Using eTSEC2 device TFTP from server 192.168.0.90; our IP address is 192.168.0.11 Filename 'uImage'. Load address: 0x1000000 Loading: * Enet starting in 1000BT/FD Speed: 1000, full duplex Using eTSEC2 device TFTP from server 192.168.0.90; our IP address is 192.168.0.11 Filename 'myboard.dtb'. Load address: 0x3000000 Loading: * ## Booting image at 01000000 ... Image Name: Linux-2.6.21.7 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 1509390 Bytes = 1.4 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Booting using the fdt at 0x3000000 Loading Device Tree to 007fc000, end 007fd313 ... OK Parsing ARGS: root=/dev/nfs rw nfsroot=192.168.0.90:/home/ftpuser/workspace/rootfs ip=192.168.0.11:192.168.0.90:192.168.0.90:255.255.255.0:MYBOARD:eth2:off console=ttyS1,115200 early options: Parameter `root' Unknown argument: calling c02dc5f0 return parse_one 0 early options: Parameter `root' early options: Parameter `rw' Unknown argument: calling c02dc5f0 return parse_one 0 early options: Parameter `rw' early options: Parameter `nfsroot' Unknown argument: calling c02dc5f0 return parse_one 0 early options: Parameter `nfsroot' early options: Parameter `ip' Unknown argument: calling c02dc5f0 return parse_one 0 early options: Parameter `ip' early options: Parameter `console' Unknown argument: calling c02dc5f0 return parse_one 0 early options: Parameter `console' Using MYBOARD machine description Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=256Mb residual: 256Mb Linux version 2.6.21.7 (gcc version 4.1.2 ) #2 PREEMPT Thu Mar 13 16:30:01 GMT 2008 setup_arch: bootmem setup_arch() arch: exit Zone PFN ranges: DMA 0 -> 196608 Normal 196608 -> 196608 HighMem 196608 -> 262144 early_node_map[1] active PFN ranges 0: 0 -> 262144 Built 1 zonelists. Total pages: 260096 Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.90:/home/ftpuser/workspace/rootfs ip=192.168.0.11:192.168.0.90:192.168.0.90:255.255.255.0:MYBOARD:eth2:off console=ttyS1,115200 Parsing ARGS: root=/dev/nfs rw nfsroot=192.168.0.90:/home/ftpuser/workspace/rootfs ip=192.168.0.11:192.168.0.90:192.168.0.90:255.255.255.0:MYBOARD:eth2:off console=ttyS1,115200 Booting kernel: Parameter `root' Unknown argument: calling c02dc318 return parse_one 0 Booting kernel: Parameter `root=/dev/nfs' Booting kernel: Parameter `rw' Unknown argument: calling c02dc318 return parse_one 0 Booting kernel: Parameter `rw' Booting kernel: Parameter `nfsroot' Unknown argument: calling c02dc318 return parse_one 0 Booting kernel: Parameter `nfsroot=192.168.0.90:/home/ftpuser/workspace/rootfs' Booting kernel: Parameter `ip' Unknown argument: calling c02dc318 return parse_one 0 Booting kernel: Parameter `ip=192.168.0.11:192.168.0.90:192.168.0.90:255.255.255.0:MYBOARD:eth2:off' Booting kernel: Parameter `console' Unknown argument: calling c02dc318 Oops: Exception in kernel mode, sig: 4 [#1] PREEMPT Modules linked in: NIP: C02E7B30 LR: C02E7C28 CTR: 00000000 REGS: c031be80 TRAP: 0700 Not tainted (2.6.21.7) MSR: 00021000 <ME> CR: 24084022 XER: 00000000 TASK = c02fe5b8[0] 'swapper' THREAD: c031a000 GPR00: 00000000 C031BF30 C02FE5B8 C0332184 C031BF58 C035595A C031BF5E C0300000 GPR08: 0000000A C0332184 00000001 C0332184 00000000 60000000 3FFFC400 03000000 GPR16: 00000001 00000000 007FFF00 00000000 00000000 007FFEB0 00000000 C02D6000 GPR24: 00000044 00021000 00000000 C035595A 00000001 C031BF58 C0332184 00000000 NIP [C02E7B30] add_preferred_console+0xac/0xd8 LR [C02E7C28] console_setup+0xcc/0xe4 Call Trace: [C031BF30] [C03017C0] 0xc03017c0 (unreliable) [C031BF50] [C02E7C28] console_setup+0xcc/0xe4 [C031BF70] [C02DC400] unknown_bootoption+0xe8/0x260 [C031BF90] [C003DDC8] parse_args+0x1f8/0x310 [C031BFC0] [C02DC7F4] start_kernel+0x16c/0x2b4 [C031BFF0] [C0000388] skpinv+0x2b8/0x2f4 Instruction dump: 48000048 3d20c030 38600000 93e9ff98 48000038 3d20c030 93e9ff98 3d20c033 39292184 57eb2036 7d6b4a14 38000000 <7d3d44aa> 7d2b45aa 38600000 938b0008 Kernel panic - not syncing: Attempted to kill the idle task! Rebooting in 180 seconds..

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[U-Boot-Users] udc_endpoint_write
by Ulf Luecking 14 Mar '08

14 Mar '08

Hello, I am new to u-boot code, but there seem to be different versions of "udc_endpoint_write" in drivers/usb/usbdcore_mpc8xx.c and drivers/usb/ usbdcore_omap1510.c. Trying the configuration for OMAP 1510 with USB tty, the compiler complains 'usbtty.c:1057: error: void value not ignored as it ought to be'. Grepping for this function returns drivers/usb/usbdcore_mpc8xx.c:int udc_endpoint_write (struct usb_endpoint_instance *epi) and drivers/usb/usbdcore_omap1510.c:void udc_endpoint_write (struct usb_endpoint_instance *endpoint) Same applies for drivers/usb/usbdcore_s3c2410.c when using OpenMoko patches. BR, Ulf

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[U-Boot-Users] [PATCH] Add support for Intersil isl1208 RTC
by Tor Krill 13 Mar '08

13 Mar '08

Signed-off-by: Tor Krill <tor(a)excito.com> --- README | 1 + drivers/rtc/Makefile | 1 + drivers/rtc/isl1208.c | 176 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 178 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/isl1208.c diff --git a/README b/README index 491397a..b230fde 100644 --- a/README +++ b/README @@ -669,6 +669,7 @@ The following options need to be configured: CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC + CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC Note that if the RTC uses I2C, then the I2C interface diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af2bf4..a0d3472 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -53,6 +53,7 @@ COBJS-y += rs5c372.o COBJS-y += rx8025.o COBJS-y += mcfrtc.o COBJS-y += x1205.o +COBJS-y += isl1208.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c new file mode 100644 index 0000000..d52d23d --- /dev/null +++ b/drivers/rtc/isl1208.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2008 + * Tor Krill, Excito Elektronik i Skåne , tor(a)excito.com + * + * Modelled after the ds1337 driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support (no alarms) for Intersil + * ISL1208 Real Time Clock (RTC). + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> + +#if defined(CONFIG_RTC_ISL1208) && defined(CONFIG_CMD_DATE) + +/*---------------------------------------------------------------------*/ +#undef DEBUG_RTC + +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/* + * RTC register addresses + */ + +#define RTC_SEC_REG_ADDR 0x0 +#define RTC_MIN_REG_ADDR 0x1 +#define RTC_HR_REG_ADDR 0x2 +#define RTC_DATE_REG_ADDR 0x3 +#define RTC_MON_REG_ADDR 0x4 +#define RTC_YR_REG_ADDR 0x5 +#define RTC_DAY_REG_ADDR 0x6 +#define RTC_STAT_REG_ADDR 0x7 +/* + * RTC control register bits + */ + +/* + * RTC status register bits + */ +#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */ +#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */ +#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */ +#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */ +#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ +#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + +/* + * Get the current time from the RTC + */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year, status; + + status = rtc_read (RTC_STAT_REG_ADDR); + sec = rtc_read (RTC_SEC_REG_ADDR); + min = rtc_read (RTC_MIN_REG_ADDR); + hour = rtc_read (RTC_HR_REG_ADDR); + wday = rtc_read (RTC_DAY_REG_ADDR); + mday = rtc_read (RTC_DATE_REG_ADDR); + mon = rtc_read (RTC_MON_REG_ADDR); + year = rtc_read (RTC_YR_REG_ADDR); + + DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x status: %02x\n", + year, mon, mday, wday, hour, min, sec, status); + + if (status & RTC_STAT_BIT_RTCF) { + printf ("### Warning: RTC oscillator has stopped\n"); + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF)); + } + + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year)+2000; + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/* + * Set the RTC + */ +void rtc_set (struct rtc_time *tmp) +{ + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* enable write */ + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC); + + rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); + rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */ + rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + + /* disable write */ + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC); +} + +void rtc_reset (void) +{ +} + +/* + * Helper functions + */ + +static +uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + + +#endif -- 1.5.3.7

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[U-Boot-Users] Veronica Lee hat dir eine hi5 Freunde-Anfrage geschickt
by info＠hi5.com 13 Mar '08

13 Mar '08

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[U-Boot-Users] [PATCH] HMI1001: add support for MPC5200 Rev. B processors.
by Wolfgang Denk 13 Mar '08

13 Mar '08

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/hmi1001/hmi1001.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 9fa0e74..3ecb74a 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -147,6 +147,24 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + /* return dramsize + dramsize2; */ return dramsize; } -- 1.5.4.2

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Re: [U-Boot-Users] Flash write crash on MPC8548CDS
by Andy Fleming 13 Mar '08

13 Mar '08

> Ok closer look revealed this entry. > ========================== tlb.c snip =============================== > /* > * TLB 6: 64M Cacheable, non-guarded > * 0xf000_0000 64M LBC SDRAM > */ > SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, > MAS3_SX|MAS3_SW|MAS3_SR, 0, > 0, 6, BOOKE_PAGESZ_64M, 1), > ===================================================================== > > And I don't even have SDRAM :)... but in order to stay as close to my > reference, mpc8548cds, I thought the extra tlb entry could not hurt me. > > I have remarked it and the Exception did not occur again. Excellent! > my last unknown / not understood corner... is why the speculative loads > occur in the first time. This is a common fact of CPUs. In order to improve performance, the cpu will often start executing code paths before it knows whether those paths will be taken. If the path is taken, the results are committed, and you don't have to wait. If the path isn't taken, the results are ignored. When the path is not taken, it's likely that the registers aren't in a sensible state, so random addresses can end up getting loaded. When things aren't mapped, the loads don't happen (speculative instructions aren't allowed to cause exceptions). Also, pages that are marked "guarded" don't allow speculative access (reading from IO regions can have side-effects, so it's not allowed to do so speculatively). After the first speculative load, either the branch predictor starts being right from them on, or it just isn't detected because the subsequent errors are gated behind the LBC interrupt logic, waiting for someone to clear it. Andy

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[U-Boot-Users] Ethernet problem with u-boot 1.3.2 on M5272C3 board
by Humphrey Li 13 Mar '08

13 Mar '08

Hi, I built u-boot 1.3.2 for my new M5272C3. Everything looks fine. I can program the u-boot image into M5272C3, and then boot into u-boot, but I cannot see the Ethernet interface working. I set the environment variables of U-Boot as below, -> setenv ipaddr 192.168.1.22 -> setenv serverip 192.168.1.20 -> setenv gatewayip 192.168.1.1 But I got the messages below for the ping command, -> ping 192.168.1.1 Using FEC0 device TX timeout fec_recv[216] err: 882 TX timeout ping failed; host 192.168.1.1 is not alive Even I ping 192.168.1.22, I got the same error messages. Do you have any idea why FEC0 doesn't work? There is no any problem when I use the network commands with dBUG monitor. Thank you! Humphrey Ask a question on any topic and get answers from real people. Go to Yahoo! Answers and share what you know at http://ca.answers.yahoo.com

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[U-Boot-Users] [PATCH 2/3] 83xx: serdes setup routines
by Anton Vorontsov 13 Mar '08

13 Mar '08

This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/serdes.c | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/fsl_serdes.h | 25 ++++++++ 3 files changed, 187 insertions(+), 1 deletions(-) create mode 100644 cpu/mpc83xx/serdes.c create mode 100644 include/fsl_serdes.h diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 94a3cb8..678be29 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o ecc.o qe_io.o pci.o fdt.o + spd_sdram.o ecc.o qe_io.o pci.o fdt.o serdes.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c new file mode 100644 index 0000000..666bffd --- /dev/null +++ b/cpu/mpc83xx/serdes.c @@ -0,0 +1,161 @@ +/* + * Freescale SerDes initialization routine + * + * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved. + * + * Author: Li Yang <leoli(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <config.h> + +#ifdef CONFIG_FSL_SERDES + +#include <common.h> +#include <asm/io.h> +#include <fsl_serdes.h> + +/* SerDes registers */ +#define FSL_SRDSCR0_OFFS 0x0 +#define FSL_SRDSCR0_DPP_1V2 0x00008800 +#define FSL_SRDSCR1_OFFS 0x4 +#define FSL_SRDSCR1_PLLBW 0x00000040 +#define FSL_SRDSCR2_OFFS 0x8 +#define FSL_SRDSCR2_VDD_1V2 0x00800000 +#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c +#define FSL_SRDSCR2_SEIC_SATA 0x00001414 +#define FSL_SRDSCR2_SEIC_PEX 0x00001010 +#define FSL_SRDSCR2_SEIC_SGMII 0x00000101 +#define FSL_SRDSCR3_OFFS 0xc +#define FSL_SRDSCR3_KFR_SATA 0x10100000 +#define FSL_SRDSCR3_KPH_SATA 0x04040000 +#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 +#define FSL_SRDSCR3_SDTXL_SATA 0x00000505 +#define FSL_SRDSCR4_OFFS 0x10 +#define FSL_SRDSCR4_PROT_SATA 0x00000808 +#define FSL_SRDSCR4_PROT_PEX 0x00000101 +#define FSL_SRDSCR4_PROT_SGMII 0x00000505 +#define FSL_SRDSCR4_PLANE_X2 0x01000000 +#define FSL_SRDSRSTCTL_OFFS 0x20 +#define FSL_SRDSRSTCTL_RST 0x80000000 +#define FSL_SRDSRSTCTL_SATA_RESET 0xf + +static void setup_serdes(void *regs, char proto, char rfcks, char vdd) +{ + u32 tmp; + + /* 1.0V corevdd */ + if (vdd) { + /* DPPE/DPPA = 0 */ + tmp = in_be32(regs + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_DPP_1V2; + out_be32(regs + FSL_SRDSCR0_OFFS, tmp); + + /* VDD = 0 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_VDD_1V2; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + } + + /* protocol specific configuration */ + switch (proto) { + case FSL_SERDES_PROTO_SATA: + /* Set and clear reset bits */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + udelay(1000); + tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SATA; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | + FSL_SRDSCR3_SDFM_SATA_PEX | + FSL_SRDSCR3_SDTXL_SATA; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SATA; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_PEX: + case FSL_SERDES_PROTO_PEX_X2: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp |= FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_PEX; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_SDFM_SATA_PEX; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_PEX; + if (proto == FSL_SERDES_PROTO_PEX_X2) + tmp |= FSL_SRDSCR4_PLANE_X2; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_SGMII: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SGMII; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + out_be32(regs + FSL_SRDSCR3_OFFS, 0); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + default: + return; + } + + /* Do a software reset */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_RST; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); +} + +void fsl_setup_serdes(void) +{ +#ifdef CONFIG_FSL_SERDES1 + setup_serdes(CONFIG_FSL_SERDES1, CONFIG_FSL_SERDES1_PROTO, + CONFIG_FSL_SERDES1_CLK, CONFIG_FSL_SERDES1_VDD_1V); +#endif +#ifdef CONFIG_FSL_SERDES2 + setup_serdes(CONFIG_FSL_SERDES2, CONFIG_FSL_SERDES2_PROTO, + CONFIG_FSL_SERDES2_CLK, CONFIG_FSL_SERDES2_VDD_1V); +#endif +} + +#endif diff --git a/include/fsl_serdes.h b/include/fsl_serdes.h new file mode 100644 index 0000000..4c9a766 --- /dev/null +++ b/include/fsl_serdes.h @@ -0,0 +1,25 @@ +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include <config.h> + +#ifdef CONFIG_FSL_SERDES + +#define FSL_SERDES_CLK_100 0 +#define FSL_SERDES_CLK_125 1 +#define FSL_SERDES_CLK_150 3 +#define FSL_SERDES_PROTO_SATA 0 +#define FSL_SERDES_PROTO_PEX 1 +#define FSL_SERDES_PROTO_PEX_X2 2 +#define FSL_SERDES_PROTO_SGMII 3 +#define FSL_SERDES_VDD1V 1 + +extern void fsl_setup_serdes(void); + +#else + +static inline void fsl_setup_serdes(void) {} + +#endif + +#endif /* __FSL_SERDES_H */ -- 1.5.2.2

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[U-Boot-Users] [PATCH] TQM5200: remove dead code
by Wolfgang Denk 13 Mar '08

13 Mar '08

This board never used a MGT5100 processor. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/tqm5200/tqm5200.c | 56 ----------------------------------------------- 1 files changed, 0 insertions(+), 56 deletions(-) diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 33ad2a3..e67145e 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -104,7 +104,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int initdram (int board_type) { ulong dramsize = 0; @@ -230,57 +229,6 @@ long int initdram (int board_type) #endif /* CONFIG_TQM5200_B */ } -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined(CONFIG_AEVFIFO) @@ -323,10 +271,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } -- 1.5.4.2

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[U-Boot-Users] [PATCH 1/8] SPARC: bootm SPARC support
by Daniel Hellstrom 13 Mar '08

13 Mar '08

This patch adds support for SPARC u-boot images to bootm. The IH_CPU_SPARC indentifier in the image header is recognized. The IH_CPU_SPARC indentifier has already been implemented in mkimage. Best Regards, Daniel Hellstrom common/cmd_bootm.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 9546729..466e783 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -262,6 +262,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (hdr->ih_arch != IH_CPU_PPC) #elif defined(__sh__) if (hdr->ih_arch != IH_CPU_SH) +#elif defined(__sparc__) + if (hdr->ih_arch != IH_CPU_SPARC) #else # error Unknown CPU type #endif

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