March 2008 - U-Boot

[U-Boot-Users] [PATCH] ColdFire: Fix second memory Chipselect for M5475EVB
by Tsi-Chung Liew 17 Mar '08

17 Mar '08

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- board/freescale/m547xevb/m547xevb.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index 0286084..539da78 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -43,6 +43,9 @@ long int initdram(int board_type) volatile siu_t *siu = (siu_t *) (MMAP_SIU); volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; +#ifdef CFG_DRAMSZ1 + u32 temp; +#endif siu->drv = CFG_SDRAM_DRVSTRENGTH; -- 1.5.4.1

1 0

[U-Boot-Users] [PATCH] ColdFire: Update correct FLASHBAR and RAMBAR1 for MCF5282
by Tsi-Chung Liew 17 Mar '08

17 Mar '08

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf52x2/start.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 260a09a..c086ca7 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -160,7 +160,7 @@ _copy_flash: _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %RAMBAR0 + movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: nop @@ -168,7 +168,7 @@ _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %RAMBAR0 + movec %d0, %RAMBAR1 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ #endif -- 1.5.4.1

1 0

[U-Boot-Users] [PATCH] [ARM] Move ARM supplied dev boards to new board/armltd directory
by Peter Pearse 17 Mar '08

17 Mar '08

This patch will allow code common to all ARM supplied development boards to be shared. This patch is also available for test from git://linux-arm.org/u-boot-armdev.git as branch 080312_move The patch is made against u-boot commit e95bcc3661a78ccc094c365ecd2484d00a60f97d: Wolfgang Denk (1): Merge branch 'master' of git +ssh://10.10.0.7/home/wd/git/u-boot/master --- Move ARM supplied dev boards to new board/armltd directory Signed-off-by Peter Pearse <peter.pearse(a)arm.com> --- diff --git a/Makefile b/Makefile old mode 100644 new mode 100755 index 4fde699..2e4af6b --- a/Makefile +++ b/Makefile @@ -2330,7 +2330,7 @@ ap720t_config \ ap920t_config \ ap926ejs_config \ ap946es_config: unconfig - @board/integratorap/split_by_variant.sh $@ + @board/armltd/integratorap/split_by_variant.sh $@ integratorcp_config \ cp_config \ @@ -2342,7 +2342,7 @@ cp966_config \ cp922_config \ cp922_XA10_config \ cp1026_config: unconfig - @board/integratorcp/split_by_variant.sh $@ + @board/armltd/integratorcp/split_by_variant.sh $@ kb9202_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200 @@ -2459,7 +2459,7 @@ VCMA9_config : unconfig versatile_config \ versatileab_config \ versatilepb_config : unconfig - @board/versatile/split_by_variant.sh $@ + @board/armltd/versatile/split_by_variant.sh $@ voiceblue_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm925t voiceblue diff --git a/cpu/arm926ejs/versatile/reset.S b/board/armltd/asm.S old mode 100644 new mode 100755 similarity index 57% rename from cpu/arm926ejs/versatile/reset.S rename to board/armltd/asm.S index e898902..db7e23f --- a/cpu/arm926ejs/versatile/reset.S +++ b/board/armltd/asm.S @@ -1,15 +1,7 @@ /* - * armboot - Startup Code for ARM926EJS CPU-core + * armltd.S - Assembler code common to development boards supplied by ARM Ltd. * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <gj(a)denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> - * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2008 ARM Ltd. * * See file CREDITS for list of people who contributed to this * project. @@ -30,16 +22,15 @@ * MA 02111-1307 USA */ +/* + * Whilst some cores and/or core mocules may provide explicit + * software reset, these are not used because they may have unwanted + * side effects. For U-Boot's purposes calling the reset vector suffices. + * If necessary, we could set some registers, update the MMU, etc. + */ + .align 5 .globl reset_cpu reset_cpu: - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever + b 0 -rstctl1: - .word 0xfffece10 diff --git a/board/integratorap/Makefile b/board/armltd/integratorap/Makefile similarity index 100% rename from board/integratorap/Makefile rename to board/armltd/integratorap/Makefile diff --git a/board/integratorap/config.mk b/board/armltd/integratorap/config.mk similarity index 100% rename from board/integratorap/config.mk rename to board/armltd/integratorap/config.mk diff --git a/board/integratorap/flash.c b/board/armltd/integratorap/flash.c similarity index 100% rename from board/integratorap/flash.c rename to board/armltd/integratorap/flash.c diff --git a/board/integratorap/integratorap.c b/board/armltd/integratorap/integratorap.c similarity index 100% rename from board/integratorap/integratorap.c rename to board/armltd/integratorap/integratorap.c diff --git a/board/integratorap/lowlevel_init.S b/board/armltd/integratorap/lowlevel_init.S similarity index 100% rename from board/integratorap/lowlevel_init.S rename to board/armltd/integratorap/lowlevel_init.S diff --git a/board/integratorap/memsetup.S b/board/armltd/integratorap/memsetup.S similarity index 100% rename from board/integratorap/memsetup.S rename to board/armltd/integratorap/memsetup.S diff --git a/board/integratorap/split_by_variant.sh b/board/armltd/integratorap/split_by_variant.sh similarity index 80% rename from board/integratorap/split_by_variant.sh rename to board/armltd/integratorap/split_by_variant.sh index 4b94d8f..e02f7fc 100755 --- a/board/integratorap/split_by_variant.sh +++ b/board/armltd/integratorap/split_by_variant.sh @@ -12,32 +12,32 @@ echo " 1 /* Integrator/AP */" >> tmp.fil # Set the core module defines according to Core Module # --------------------------------------------------------- cpu="arm_intcm" -variant="unknown core module" +variant="generic core module" if [ "$1" = "" ] then - echo "$0:: No parameters - using arm_intcm" + echo "$0:: No parameters - using core arm_unknown" else case "$1" in ap7_config) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM7TDMI" ;; ap966) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM966E-S" ;; ap922_config) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM922T" ;; integratorap_config | \ ap_config) - cpu="arm_intcm" - variant="unspecified core module" + cpu="arm_unknown" + variant="generic core module" ;; ap720t_config) @@ -48,7 +48,7 @@ else ;; ap922_XA10_config) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM922T_XA10" echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil @@ -76,18 +76,18 @@ else ;; *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" + echo "$0:: Unknown core, generic core module" + variant="generic core module" + cpu="arm_unknown" ;; esac fi -if [ "$cpu" = "arm_intcm" ] +if [ "$cpu" = "arm_unknown" ] then - echo "/* Core module undefined/not ported */" >> tmp.fil - echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo "/* Core unknown/not ported */" >> tmp.fil + echo "#define CONFIG_arm_unknown 1" >> tmp.fil echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil echo -n " /* CM may not have " >> tmp.fil echo "multiple SSRAM mapping */" >> tmp.fil @@ -105,15 +105,16 @@ then fi mkdir -p ${obj}include -mkdir -p ${obj}board/integratorap +mkdir -p ${obj}board/armltd/integratorap mv tmp.fil ${obj}include/config.h # --------------------------------------------------------- # Ensure correct core object loaded first in U-Boot image # --------------------------------------------------------- -sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorap/u-boot.lds.template > ${obj}board/integratorap/u-boot.lds +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' \ +${src}board/armltd/integratorap/u-boot.lds.template > \ +${obj}board/armltd/integratorap/u-boot.lds # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -$MKCONFIG -a integratorap arm $cpu integratorap; +$MKCONFIG -a integratorap arm $cpu integratorap armltd NULL; echo "Variant:: $variant with core $cpu" - diff --git a/board/integratorap/u-boot.lds.template b/board/armltd/integratorap/u-boot.lds.template similarity index 100% rename from board/integratorap/u-boot.lds.template rename to board/armltd/integratorap/u-boot.lds.template diff --git a/board/integratorcp/Makefile b/board/armltd/integratorcp/Makefile similarity index 100% rename from board/integratorcp/Makefile rename to board/armltd/integratorcp/Makefile diff --git a/board/integratorcp/config.mk b/board/armltd/integratorcp/config.mk similarity index 100% rename from board/integratorcp/config.mk rename to board/armltd/integratorcp/config.mk diff --git a/board/integratorcp/flash.c b/board/armltd/integratorcp/flash.c similarity index 100% rename from board/integratorcp/flash.c rename to board/armltd/integratorcp/flash.c diff --git a/board/integratorcp/integratorcp.c b/board/armltd/integratorcp/integratorcp.c similarity index 100% rename from board/integratorcp/integratorcp.c rename to board/armltd/integratorcp/integratorcp.c diff --git a/board/integratorcp/lowlevel_init.S b/board/armltd/integratorcp/lowlevel_init.S similarity index 100% rename from board/integratorcp/lowlevel_init.S rename to board/armltd/integratorcp/lowlevel_init.S diff --git a/board/integratorcp/memsetup.S b/board/armltd/integratorcp/memsetup.S similarity index 100% rename from board/integratorcp/memsetup.S rename to board/armltd/integratorcp/memsetup.S diff --git a/board/integratorcp/split_by_variant.sh b/board/armltd/integratorcp/split_by_variant.sh similarity index 82% rename from board/integratorcp/split_by_variant.sh rename to board/armltd/integratorcp/split_by_variant.sh index 79a6a9d..4eb3bf0 100755 --- a/board/integratorcp/split_by_variant.sh +++ b/board/armltd/integratorcp/split_by_variant.sh @@ -9,32 +9,32 @@ echo " /* Integrator board */" >> tmp.fil echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil echo " 1 /* Integrator/CP */" >> tmp.fil -cpu="arm_intcm" -variant="unknown core module" +cpu="arm_unknown" +variant="generic core module" if [ "$1" = "" ] then - echo "$0:: No parameters - using arm_intcm" + echo "$0:: No parameters - using arm_unknown" else case "$1" in ap966) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM966E-S" ;; ap922_config) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM922T" ;; integratorcp_config | \ cp_config) - cpu="arm_intcm" + cpu="arm_unknown" variant="unspecified core module" ;; cp922_XA10_config) - cpu="arm_intcm" + cpu="arm_unknown" variant="unported core module CM922T_XA10" echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil @@ -54,7 +54,6 @@ else echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil ;; - cp946es_config) cpu="arm946es" variant="Core module CM946E-S" @@ -70,19 +69,19 @@ else ;; *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" + echo "$0:: Unknown core" + variant="generic core module" + cpu="arm_unknown" ;; esac fi -if [ "$cpu" = "arm_intcm" ] +if [ "$cpu" = "arm_unknown" ] then echo "/* Core module undefined/not ported */" >> tmp.fil - echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo "#define CONFIG_arm_unknown 1" >> tmp.fil echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil echo -n " /* CM may not have " >> tmp.fil echo "multiple SSRAM mapping */" >> tmp.fil @@ -100,15 +99,16 @@ then fi mkdir -p ${obj}include -mkdir -p ${obj}board/integratorcp +mkdir -p ${obj}board/armltd/integratorcp mv tmp.fil ${obj}include/config.h # --------------------------------------------------------- # Ensure correct core object loaded first in U-Boot image # --------------------------------------------------------- -sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorcp/u-boot.lds.template > ${obj}board/integratorcp/u-boot.lds +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' \ +${src}board/armltd/integratorcp/u-boot.lds.template > \ +${obj}board/armltd/integratorcp/u-boot.lds # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -$MKCONFIG -a integratorcp arm $cpu integratorcp; +$MKCONFIG -a integratorcp arm $cpu integratorcp armltd NULL; echo "Variant:: $variant with core $cpu" - diff --git a/board/integratorcp/u-boot.lds.template b/board/armltd/integratorcp/u-boot.lds.template similarity index 100% rename from board/integratorcp/u-boot.lds.template rename to board/armltd/integratorcp/u-boot.lds.template diff --git a/cpu/arm926ejs/versatile/timer.c b/board/armltd/src.c old mode 100644 new mode 100755 similarity index 57% rename from cpu/arm926ejs/versatile/timer.c rename to board/armltd/src.c index 32872d2..722d897 --- a/cpu/arm926ejs/versatile/timer.c +++ b/board/armltd/src.c @@ -1,20 +1,7 @@ /* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> + * armltd.c - c code common to development boards supplied by ARM Ltd. * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu(a)sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> + * Copyright (c) 2008 ARM Ltd. * * See file CREDITS for list of people who contributed to this * project. @@ -26,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -34,6 +21,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +/* + * Timer routines applicable to all ARM supplied development boards + */ #include <common.h> #include <arm926ejs.h> @@ -47,10 +37,12 @@ static ulong timestamp; static ulong lastdec; /* nothing really to do with interrupts, just starts up a counter. */ -int timer_init (void) +int timer_init(void) { - *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */ - *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */ + /* TimerLoad */ + *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; + /* TimerValue */ + *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C; /* init the timestamp and lastdec value */ @@ -63,40 +55,54 @@ int timer_init (void) * timer without interrupts */ -void reset_timer (void) +void reset_timer(void) { reset_timer_masked (); } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { - return get_timer_masked () - base; + return get_timer_masked() - base; } -void set_timer (ulong t) +void set_timer(ulong t) { timestamp = t; } /* delay x useconds AND perserve advance timstamp value */ -void udelay (unsigned long usec) +void udelay(unsigned long usec) { ulong tmo, tmp; - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ + if (usec >= 1000) { + /* "big" number, + * spread normalization to seconds + * start to normalize for usec to ticks per sec + * find number of "ticks" to wait to achieve target + * finish normalize. + */ + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } else { + /* small number, + * don't kill it prior to HZ multiply + */ tmo = usec * CFG_HZ; tmo /= (1000*1000); } tmp = get_timer (0); /* get current timestamp */ - if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + if ((tmo + tmp + 1) < tmp) + /* if setting this forward will roll time stamp + * reset "advancing" timestamp to 0 + * set lastdec value + */ + reset_timer_masked (); else - tmo += tmp; /* else, set advancing stamp wake up time */ + /* else, set advancing stamp wake up time */ + tmo += tmp; while (get_timer_masked () < tmo)/* loop till event */ /*NOP*/; @@ -113,14 +119,17 @@ ulong get_timer_masked (void) { ulong now = READ_TIMER; /* current tick value */ - if (lastdec >= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ - } else { /* we have overflow of the count down timer */ + if (lastdec >= now) { + /* normal mode (non roll) */ + /* move stamp forward with absolute diff ticks */ + timestamp += lastdec - now; + } else { + /* we have overflow of the count down timer */ /* nts = ts + ld + (TLV - now) * ts=old stamp, ld=time that passed before passing through -1 * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and cause problems. + * nts = new "advancing time stamp" + * ...it could also roll and cause problems. */ timestamp += lastdec + TIMER_LOAD_VAL - now; } @@ -136,11 +145,18 @@ void udelay_masked (unsigned long usec) ulong endtime; signed long diff; - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + /* start to normalize for usec to ticks per sec */ + tmo = usec / 1000; + /* find number of "ticks" to wait to achieve target */ + tmo *= CFG_HZ; + /* finish normalize. */ + tmo /= 1000; + } else { + /* else small number, + * don't kill it prior to HZ multiply + */ tmo = usec * CFG_HZ; tmo /= (1000*1000); } diff --git a/board/versatile/Makefile b/board/armltd/versatile/Makefile old mode 100644 new mode 100755 similarity index 95% rename from board/versatile/Makefile rename to board/armltd/versatile/Makefile index 1fad0a7..cb39c6e --- a/board/versatile/Makefile +++ b/board/armltd/versatile/Makefile @@ -25,8 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := versatile.o flash.o -SOBJS := lowlevel_init.o +COBJS := versatile.o flash.o ../src.o +SOBJS := lowlevel_init.o ../asm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/versatile/config.mk b/board/armltd/versatile/config.mk similarity index 100% rename from board/versatile/config.mk rename to board/armltd/versatile/config.mk diff --git a/board/versatile/flash.c b/board/armltd/versatile/flash.c similarity index 100% rename from board/versatile/flash.c rename to board/armltd/versatile/flash.c diff --git a/board/versatile/lowlevel_init.S b/board/armltd/versatile/lowlevel_init.S similarity index 100% rename from board/versatile/lowlevel_init.S rename to board/armltd/versatile/lowlevel_init.S diff --git a/board/versatile/split_by_variant.sh b/board/armltd/versatile/split_by_variant.sh similarity index 94% rename from board/versatile/split_by_variant.sh rename to board/armltd/versatile/split_by_variant.sh index ccded7e..ab3c6ee 100755 --- a/board/versatile/split_by_variant.sh +++ b/board/armltd/versatile/split_by_variant.sh @@ -25,7 +25,6 @@ else variant=AB926EJ-S ;; - *) echo "$0:: Unrecognised config - using versatilepb_config" echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h @@ -38,5 +37,5 @@ fi # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -$MKCONFIG -a versatile arm arm926ejs versatile NULL versatile +$MKCONFIG -a versatile arm arm926ejs versatile armltd NULL echo "Variant:: $variant" diff --git a/board/versatile/u-boot.lds b/board/armltd/versatile/u-boot.lds similarity index 100% rename from board/versatile/u-boot.lds rename to board/armltd/versatile/u-boot.lds diff --git a/board/versatile/versatile.c b/board/armltd/versatile/versatile.c similarity index 100% rename from board/versatile/versatile.c rename to board/armltd/versatile/versatile.c diff --git a/cpu/arm926ejs/versatile/Makefile b/cpu/arm926ejs/versatile/Makefile deleted file mode 100644 index c335d5c..0000000 --- a/cpu/arm926ejs/versatile/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = timer.o -SOBJS = reset.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/arm_intcm/Makefile b/cpu/arm_unknown/Makefile similarity index 100% rename from cpu/arm_intcm/Makefile rename to cpu/arm_unknown/Makefile diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_unknown/config.mk similarity index 100% rename from cpu/arm_intcm/config.mk rename to cpu/arm_unknown/config.mk diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_unknown/cpu.c similarity index 100% rename from cpu/arm_intcm/cpu.c rename to cpu/arm_unknown/cpu.c diff --git a/cpu/arm_intcm/start.S b/cpu/arm_unknown/start.S similarity index 100% rename from cpu/arm_intcm/start.S rename to cpu/arm_unknown/start.S ---

2 1

[U-Boot-Users] [MIPS] Replace memory clearance code with f_fill64
by Shinya Kuribayashi 17 Mar '08

17 Mar '08

This routine fills memory with zero by 64 bytes, and is 64-bit capable. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/cache.S | 43 ++++++++++++++++++++++++++++--------------- 1 files changed, 28 insertions(+), 15 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 66fe47a..d260e28 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -104,6 +104,27 @@ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + /******************************************************************************* * * mips_cache_reset - low level initialisation of the primary caches @@ -128,22 +149,14 @@ NESTED(mips_cache_reset, 0, ra) li v0, MIPS_MAX_CACHE_SIZE - /* Now clear that much memory starting from zero. + /* + * Now clear that much memory starting from zero. */ - - li a0, KSEG1 - addu a1, a0, v0 -2: - sw zero, 0(a0) - sw zero, 4(a0) - sw zero, 8(a0) - sw zero, 12(a0) - sw zero, 16(a0) - sw zero, 20(a0) - sw zero, 24(a0) - sw zero, 28(a0) - addu a0, 32 - bltu a0, a1, 2b + PTR_LI a0, KSEG1 + PTR_ADDU a1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64 a0, -64, zero + bne a0, a1, 2b /* Set invalid tag. */

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[U-Boot-Users] fakir
by Devereaux Scherman 17 Mar '08

17 Mar '08

Guten Tag, +-------------------------------------------+ Warning! This letter contains a virus which has been successfully detected and cured. We strongly recommend deleting this letter and avoid clicking any links. +-------------------------------------------+ [RBN Networks Antivirus] Tt:c bus comes and the post office would be empty. The devil. at this point m. Kangourou suddenly the o was suppressed and an e placed in its stead. To be a fool she'll be a fool then just as much.' at grand cairo, but this is not correct: the language that's true, sir, but there's nothing like settling peeped but he did not know that, and presently to be ruled by circumstances from hour to hour. Thrill when she saw him passing along the causeway on the different trials. First, that the plan the corrugated brow and a voice like a tuba, so, it was the nicotine cutting. Why should she have first chronicles of: 112. Revolution, american: and shook. With eyes cast down, she left her royal indulgence everything, in a word, gives happy.

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Re: [U-Boot-Users] How to patch u-boot?
by Tiju 17 Mar '08

17 Mar '08

>> Hi >> >> Could someone help me out with patching the u-boot. >> I downloaded the source code of u-boot-1.1.6 and untared it. Then I do a >> $cd u-boot-1.1.6 >> $svn co http://svn.openmoko.org/trunk/src/target/u-boot/patches/ >those patches are against current git head of u-boot. What gave you the >assumption that the patches are agains 1.1.6? Because in http://wiki.openmoko.org/wiki/Uboot, the bootloader source code section says..."The current bootloader patches can be found at http://svn.openmoko.org/trunk/src/target/u-boot/patches/. Untar the sources, apply the patch, run "make gta01bv3_config" (or gta01bv2_config, or whatever hardware revision you have), run "make". You will get a resulting "u-boot.bin" image, which you can directly flash (either using existing bootloader or sjf2410-linux) into NAND. " So, I do not know which version to apply the patches to. How do I get the current git head of u-boot or the source code of the current bootloader for which the patches has to be applied. Thanks Tiju Jacob Chat on a cool, new interface. No download required. Go to http://in.messenger.yahoo.com/webmessengerpromo.php

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[U-Boot-Users] [MIPS] Fix I-/D-cache initialization loops
by Shinya Kuribayashi 17 Mar '08

17 Mar '08

We currently do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I again per a loop for I-cache initialization. But according to 'See MIPS Run', we are encouraged to use three separate loops rather than combining them for both I- and D-cache. This patch tries to fix that. In accordance with fixing above, mips_init_[id]cache are now separated from mips_cache_reset() and cache loops are completely rewritten with useful macros. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/cache.S | 115 ++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 76 insertions(+), 39 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index d260e28..0842093 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -30,11 +30,23 @@ #include <asm/addrspace.h> #include <asm/cacheops.h> +#define t8 RA + /* 16KB is the maximum size of instruction and data caches on * MIPS 4K. */ #define MIPS_MAX_CACHE_SIZE 0x4000 +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .set push + .set noreorder + .set mips3 + cache \op, 0(\addr) + .set pop + .endm + /* * cacheop macro to automate cache operations * first some helpers... @@ -125,6 +137,56 @@ #endif .endm +/* + * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) + */ +LEAF(mips_init_icache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear tag to invalidate */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE +2: cache_op Fill t0 + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_icache) + +/* + * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) + */ +LEAF(mips_init_dcache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear all tags */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_dcache) + /******************************************************************************* * * mips_cache_reset - low level initialisation of the primary caches @@ -142,6 +204,7 @@ * */ NESTED(mips_cache_reset, 0, ra) + move RA, ra li t2, CFG_ICACHE_SIZE li t3, CFG_DCACHE_SIZE li t4, CFG_CACHELINE_SIZE @@ -158,57 +221,31 @@ NESTED(mips_cache_reset, 0, ra) f_fill64 a0, -64, zero bne a0, a1, 2b - /* Set invalid tag. - */ - - mtc0 zero, CP0_TAGLO - /* * The caches are probably in an indeterminate state, * so we force good parity into them by doing an * invalidate, load/fill, invalidate for each line. */ - /* Assume bottom of RAM will generate good parity for the cache. - */ - - li a0, K0BASE - move a2, t2 # icacheSize - move a3, t4 # icacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) - - /* To support Orion/R4600, we initialise the data cache in 3 passes. - */ - - /* 1: initialise dcache tags. + /* + * Assume bottom of RAM will generate good parity for the cache. */ - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - /* 2: fill dcache. + /* + * Initialize the I-cache first, */ + move a1, t2 + move a2, t4 + bal mips_init_icache - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,1lw,(dummy)) - - /* 3: clear dcache tags. + /* + * then initialize D-cache. */ + move a1, t3 + move a2, t5 + bal mips_init_dcache - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - j ra + j RA END(mips_cache_reset) /*******************************************************************************

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[U-Boot-Users] [PATCH] cpu/mpc8260/: ported new fdt code from cpu/mpc83xx/
by Nikita V. Youshchenko 17 Mar '08

17 Mar '08

commit 0e6e4bbe5be1ef7f601abe7eddbe44b56fd5e43a Author: Nikita Youshchenko <yoush(a)cs.msu.su> Date: Mon Feb 25 11:27:06 2008 +0000 cpu/mpc8260/: ported new fdt code from cpu/mpc83xx/ This patch splits mpc8260 fdt fixup code into individual file, fdt.c, and updates it up to what is in cpu/mpc83xx/fdt.c. Also, it adds setting current-speed property for SMC uart, and setting value of 'brg-frequency' property on SOC node, if that property exists. The later is needed to support booting of vendor kernels based on 2.6.18 or near that. Signed-off-by: Nikita Youshchenko <yoush(a)cs.msu.su> diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile index 80d7852..d2a9f79 100644 --- a/cpu/mpc8260/Makefile +++ b/cpu/mpc8260/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(CPU).a START = start.o kgdb.o COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \ - bedbug_603e.o pci.o spi.o + bedbug_603e.o pci.o spi.o fdt.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 55e61a1..f6383c3 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -47,12 +47,6 @@ #include <asm/processor.h> #include <asm/cpm_8260.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <libfdt_env.h> -#include <fdt_support.h> -#endif - DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_GET_CPU_STR_F) @@ -298,15 +292,3 @@ void watchdog_reset (void) enable_interrupts (); } #endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) -void ft_cpu_setup (void *blob, bd_t *bd) -{ - char * cpu_path = "/cpus/" OF_CPU; - - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); -} -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc8260/fdt.c b/cpu/mpc8260/fdt.c new file mode 100644 index 0000000..28bfe24 --- /dev/null +++ b/cpu/mpc8260/fdt.c @@ -0,0 +1,73 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_OF_LIBFDT) + +#include <libfdt.h> +#include <fdt_support.h> + +void ft_cpu_setup (void *blob, bd_t *bd) +{ + +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob, bd); +#endif + + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", (bd->bi_busfreq / 4), 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); + + /* This is used by obsolete kernels only. + Let's set it in case it exists, but not create it. */ + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "brg-frequency", bd->bi_brgfreq, 0); + +#ifdef CFG_NS16550 + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", bd->bi_busfreq, 1); +#endif + +#ifdef CONFIG_CPM2 + do_fixup_by_compat_u32(blob, "fsl,cpm2-smc-uart", + "current-speed", bd->bi_baudrate, 1); + do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", + "current-speed", bd->bi_baudrate, 1); + + do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", + "clock-frequency", bd->bi_brgfreq, 1); +#endif + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} + +#endif /* CONFIG_OF_LIBFDT */

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[U-Boot-Users] [PATCH v1 0/5] ATA: SATA framework patchset
by Dave Liu 17 Mar '08

17 Mar '08

Hello Wolfgang, The patchset is only for review, not intend to apply it in v1 status. I'm working the FSL SATA controller driver in the framework. and I will send the v2 patchset with FSL SATA driver in this week. Thanks, Dave

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[U-Boot-Users] dd to generate image.
by Tim Chen 17 Mar '08

17 Mar '08

Hi, I'm using dd to generate the u-boot+kernel+rootfs image. I executed command like.. dd if=rootfs.jffs2 of=kernel.img bs=1 seek=ROOTFS_OFFSET But dd is quite slow, generating a 64MB image spends about 5 minutes. I have changed bs=1 to bs=1024 or bigger, but the outputted image size is wrong, too big. dd manpage says that bs is the size of read/write one time. Doesn't it make dd faster? How do make dd faster? -- -- Regards, Tim.

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