March 2008 - U-Boot

[U-Boot-Users] [PATCH 5/8] SPARC: Added AMBA PnP Information listing command for LEON3
by Daniel Hellstrom 13 Mar '08

13 Mar '08

This patch adds an U-Boot command, ambapp, which prints a summary of AMBA Bus Plug & Play information. AMBA is a bus specified by ARM. AMBA with Plug and Play information is a Gaisler extension to that bus. See www.gaisler.com. ###################### U-Boot 1.3.2-g6bc2ec61-dirty (Mar 12 2008 - 21:24:14)Gaisler GRSIM CPU: LEON3 Board: GRSIM/TSIM Using default environment In: serial Out: serial Err: serial Net: PHY info not available GRETH 10/100 Type "run flash_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 => ambapp --------- AHB Masters --------- 0x00:0x01:0x03: VENDOR_GAISLER GAISLER_LEON3 irq: 0 (ver: 0) --------- AHB Slaves --------- 0x00:0x04:0x0f: VENDOR_ESA ESA_MCTRL mem: 0x00000000 - 0x10000000 mem: 0x20000000 - 0x30000000 mem: 0x40000000 - 0x70000000 irq: 1 (ver: 0) 0x01:0x01:0x06: VENDOR_GAISLER GAISLER_APBMST mem: 0xc0000000 - 0xc0100000 irq: 3 (ver: 0) --------- APB Slaves --------- 0x00:0x04:0x0f: VENDOR_ESA ESA_MCTRL apb: 0xc0000000 - 0xc0000100 irq: 1 (ver: 0 ) 0x01:0x01:0x0c: VENDOR_GAISLER GAISLER_APBUART apb: 0xc0000100 - 0xc0000200 irq: 3 (ver: 0 ) 0x02:0x01:0x0d: VENDOR_GAISLER GAISLER_IRQMP apb: 0xc0000200 - 0xc0000300 irq: 7 (ver: 0 ) 0x03:0x01:0x11: VENDOR_GAISLER GAISLER_GPTIMER apb: 0xc0000300 - 0xc0000400 irq: 8 (ver: 0 ) 0x04:0x01:0x1d: VENDOR_GAISLER GAISLER_ETHMAC apb: 0xc0000800 - 0xc0001000 irq: 12 (ver: 0 ) => ###################### Best Regards, Daniel Hellstrom commit 8e2783598c9270a17140930c99b3eb76f892de51 Author: Daniel Hellstrom <daniel(a)gaisler.com> Date: Wed Mar 12 21:26:31 2008 +0100 SPARC/LEON3: Added AMBA Bus Plug&Play information print command (ambapp). It can print available cores (type: AHB Master, AHB Slave, APB Slave), their address ranges, IRQ number and version. Signed-off-by: Daniel Hellstrom <daniel(a)gaisler.com> common/Makefile | 1 + common/cmd_ambapp.c | 292 ++++++++++++++++++++++++++++++ include/ambapp.h | 443 ++++++++++++++++++++++++++++++++++++++++++++++ include/config_cmd_all.h | 1 + 4 files changed, 737 insertions(+), 0 deletions(-) diff --git a/common/Makefile b/common/Makefile index a88d1ef..3d369ff 100644 --- a/common/Makefile +++ b/common/Makefile @@ -91,6 +91,7 @@ COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o COBJS-$(CONFIG_CMD_USB) += cmd_usb.o +COBJS-y += cmd_ambapp.o COBJS-y += cmd_vfd.o COBJS-y += command.o COBJS-y += console.o diff --git a/common/cmd_ambapp.c b/common/cmd_ambapp.c new file mode 100644 index 0000000..5329a3a --- /dev/null +++ b/common/cmd_ambapp.c @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel(a)gaisler.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * AMBA Plug&Play information list command + */ +#include <common.h> +#include <command.h> + +#if defined(CONFIG_CMD_AMBAPP) + +#ifndef CONFIG_LEON3 +#error Only LEON3 processors support the AMBA Plug&Play bus +#endif + +#include <ambapp.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* We put these variables into .data section so that they are + * zero when entering the AMBA Plug & Play Section the first time. + * BSS is not garantueed to be zero since BSS hasn't been cleared + * the first times entering the AMBA functions. + */ +int ambapp_apb_print __attribute__ ((section (".data"))) = 0; +int ambapp_ahb_print __attribute__ ((section (".data"))) = 0; + +typedef struct { + int device_id; + char *name; +} ambapp_device_name; + +static ambapp_device_name gaisler_devices[] = +{ + {GAISLER_LEON3, "GAISLER_LEON3"}, + {GAISLER_LEON3DSU, "GAISLER_LEON3DSU"}, + {GAISLER_ETHAHB, "GAISLER_ETHAHB"}, + {GAISLER_ETHMAC, "GAISLER_ETHMAC"}, + {GAISLER_APBMST, "GAISLER_APBMST"}, + {GAISLER_AHBUART, "GAISLER_AHBUART"}, + {GAISLER_SRCTRL, "GAISLER_SRCTRL"}, + {GAISLER_SDCTRL, "GAISLER_SDCTRL"}, + {GAISLER_APBUART, "GAISLER_APBUART"}, + {GAISLER_IRQMP, "GAISLER_IRQMP"}, + {GAISLER_AHBRAM, "GAISLER_AHBRAM"}, + {GAISLER_GPTIMER, "GAISLER_GPTIMER"}, + {GAISLER_PCITRG, "GAISLER_PCITRG"}, + {GAISLER_PCISBRG, "GAISLER_PCISBRG"}, + {GAISLER_PCIFBRG, "GAISLER_PCIFBRG"}, + {GAISLER_PCITRACE, "GAISLER_PCITRACE"}, + {GAISLER_AHBTRACE, "GAISLER_AHBTRACE"}, + {GAISLER_ETHDSU, "GAISLER_ETHDSU"}, + {GAISLER_PIOPORT, "GAISLER_PIOPORT"}, + {GAISLER_AHBJTAG, "GAISLER_AHBJTAG"}, + {GAISLER_ATACTRL, "GAISLER_ATACTRL"}, + {GAISLER_VGA, "GAISLER_VGA"}, + {GAISLER_KBD, "GAISLER_KBD"}, + {GAISLER_L2TIME, "GAISLER_L2TIME"}, + {GAISLER_L2C, "GAISLER_L2C"}, + {GAISLER_PLUGPLAY, "GAISLER_PLUGPLAY"}, + {GAISLER_SPW, "GAISLER_SPW"}, + {GAISLER_SPW2, "GAISLER_SPW2"}, + {GAISLER_EHCI, "GAISLER_EHCI"}, + {GAISLER_UHCI, "GAISLER_UHCI"}, + {GAISLER_AHBSTAT, "GAISLER_AHBSTAT"}, + {GAISLER_DDR2SPA, "GAISLER_DDR2SPA"}, + {GAISLER_DDRSPA, "GAISLER_DDRSPA"}, + {0, NULL} +}; + +static ambapp_device_name esa_devices[] = +{ + {ESA_LEON2, "ESA_LEON2"}, + {ESA_MCTRL, "ESA_MCTRL"}, + {0, NULL} +}; + +static ambapp_device_name opencores_devices[] = +{ + {OPENCORES_PCIBR, "OPENCORES_PCIBR"}, + {OPENCORES_ETHMAC, "OPENCORES_ETHMAC"}, + {0, NULL} +}; + +typedef struct { + unsigned int vendor_id; + char *name; + ambapp_device_name *devices; +} ambapp_vendor_devnames; + +static ambapp_vendor_devnames vendors[] = +{ + {VENDOR_GAISLER, "VENDOR_GAISLER", gaisler_devices}, + {VENDOR_ESA, "VENDOR_ESA", esa_devices}, + {VENDOR_OPENCORES, "VENDOR_OPENCORES", opencores_devices}, + {0, NULL, 0} +}; + +static char *ambapp_get_devname(ambapp_device_name *devs, int id) +{ + if ( !devs ) + return NULL; + + while( devs->device_id > 0 ){ + if ( devs->device_id == id ) + return devs->name; + devs++; + } + return NULL; +} + +char *ambapp_device_id2str(int vendor, int id) +{ + ambapp_vendor_devnames *ven = &vendors[0]; + + while( ven->vendor_id > 0 ){ + if ( ven->vendor_id == vendor ){ + return ambapp_get_devname(ven->devices,id); + } + ven++; + } + return NULL; +} + +char *ambapp_vendor_id2str(int vendor) +{ + ambapp_vendor_devnames *ven = &vendors[0]; + + while( ven->vendor_id > 0 ){ + if ( ven->vendor_id == vendor ){ + return ven->name; +/* return ambapp_get_devname(ven->devices,ven->vendor_id);*/ + } + ven++; + } + return NULL; +} + +static char *unknown = "unknown"; + +/* Print one APB device */ +void ambapp_print_apb( + apbctrl_pp_dev *apb, + ambapp_ahbdev *apbmst, + int index) +{ + char *dev_str, *ven_str; + int irq, ver, vendor, deviceid; + unsigned int address, apbmst_base, mask; + + vendor = amba_vendor(apb->conf); + deviceid = amba_device(apb->conf); + irq = amba_irq(apb->conf); + ver = amba_ver(apb->conf); + apbmst_base = apbmst->address[0] & LEON3_IO_AREA; + address = (apbmst_base | (((apb->bar & 0xfff00000)>> 12))) & + (((apb->bar & 0x0000fff0) <<4) | 0xfff00000); + + mask = amba_membar_mask(apb->bar) << 8; + mask = ((~mask)&0x000fffff)+1; + + ven_str = ambapp_vendor_id2str(vendor); + if ( !ven_str ){ + ven_str = unknown; + dev_str = unknown; + }else{ + dev_str = ambapp_device_id2str(vendor,deviceid); + if ( !dev_str ) + dev_str = unknown; + } + + printf("0x%02x:0x%02x:0x%02x: %s %s\n" + " apb: 0x%08x - 0x%08x\n" + " irq: %-2d (ver: %-2d)\n", + index,vendor,deviceid,ven_str,dev_str,address, + address+mask,irq,ver); +} + +void ambapp_print_ahb(ahbctrl_pp_dev *ahb, int index) +{ + char *dev_str, *ven_str; + int irq, ver, vendor, deviceid; + unsigned int addr, mask; + int j; + + vendor = amba_vendor(ahb->conf); + deviceid = amba_device(ahb->conf); + irq = amba_irq(ahb->conf); + ver = amba_ver(ahb->conf); + + ven_str = ambapp_vendor_id2str(vendor); + if ( !ven_str ){ + ven_str = unknown; + dev_str = unknown; + }else{ + dev_str = ambapp_device_id2str(vendor,deviceid); + if ( !dev_str ) + dev_str = unknown; + } + + printf("0x%02x:0x%02x:0x%02x: %s %s\n", + index,vendor,deviceid,ven_str,dev_str); + + for(j=0; j<4; j++) + { + addr = amba_membar_start(ahb->bars[j]); + if ( amba_membar_type(ahb->bars[j]) == 0 ) + continue; + if (amba_membar_type(ahb->bars[j]) == AMBA_TYPE_AHBIO) + addr = AMBA_TYPE_AHBIO_ADDR(addr); + mask = amba_membar_mask(ahb->bars[j]) << 20; + printf(" mem: 0x%08x - 0x%08x\n",addr,addr+((~mask)+1)); + } + + printf(" irq: %-2d (ver: %d)\n",irq,ver); +} + +int +do_ambapp_print (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + /* Print AHB Masters */ + puts("--------- AHB Masters ---------\n"); + ambapp_apb_print = 0; + ambapp_ahb_print = 1; + ambapp_ahbmst_count(99,99); /* Get vendor&device 99 = nonexistent... */ + + /* Print AHB Slaves */ + puts("--------- AHB Slaves ---------\n"); + ambapp_ahbslv_count(99,99); /* Get vendor&device 99 = nonexistent... */ + + /* Print APB Slaves */ + puts("--------- APB Slaves ---------\n"); + ambapp_apb_print = 1; + ambapp_ahb_print = 0; + ambapp_apb_count(99,99); /* Get vendor&device 99 = nonexistent... */ + + /* Reset, no futher printing */ + ambapp_apb_print = 0; + ambapp_ahb_print = 0; + puts("\n"); + return 0; +} + +int ambapp_init_reloc(void) +{ + ambapp_vendor_devnames *vend = vendors; + ambapp_device_name *dev; + + while( vend->vendor_id && vend->name ){ + vend->name = (char *)((unsigned int)vend->name + gd->reloc_off); + vend->devices = (ambapp_device_name *)((unsigned int)vend->devices + gd->reloc_off);; + dev = vend->devices; + vend++; + if ( !dev ) + continue; + while( dev->device_id && dev->name ){ + dev->name = (char *)((unsigned int)dev->name + gd->reloc_off);; + dev++; + } + } + return 0; +} + +U_BOOT_CMD( + ambapp, 1, 1, do_ambapp_print, + "ambapp - list AMBA Plug&Play information\n", + "ambapp\n" + " - lists AMBA (AHB & APB) Plug&Play devices present on the system\n" +); + +#endif /* CFG_CMD_AMBAPP */ diff --git a/include/ambapp.h b/include/ambapp.h new file mode 100644 index 0000000..7bdbc9a --- /dev/null +++ b/include/ambapp.h @@ -0,0 +1,443 @@ +/* Interface for accessing Gaisler AMBA Plug&Play Bus. + * The AHB bus can be interfaced with a simpler bus - + * the APB bus, also freely available in GRLIB at + * www.gaisler.com. + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel(a)gaisler.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + + +#ifndef __AMBAPP_H__ +#define __AMBAPP_H__ + +/* Default location of Plug&Play info + * normally 0xfffff000 for AHB masters + * and 0xfffff800 for AHB slaves. + * Normally no need to change this. + */ +#define LEON3_IO_AREA 0xfff00000 +#define LEON3_CONF_AREA 0xff000 +#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11) + +/* Max devices this software will support */ +#define LEON3_AHB_MASTERS 16 +#define LEON3_AHB_SLAVES 16 +/*#define LEON3_APB_MASTERS 1*/ /* Number of APB buses that has Plug&Play */ +#define LEON3_APB_SLAVES 16 /* Total number of APB slaves per APB bus */ + +/* Vendor codes */ +#define VENDOR_GAISLER 1 +#define VENDOR_PENDER 2 +#define VENDOR_ESA 4 +#define VENDOR_ASTRIUM 6 +#define VENDOR_OPENCHIP 7 +#define VENDOR_OPENCORES 8 +#define VENDOR_CONTRIB 9 +#define VENDOR_EONIC 11 +#define VENDOR_RADIONOR 15 +#define VENDOR_GLEICHMANN 16 +#define VENDOR_MENTA 17 +#define VENDOR_SUN 19 +#define VENDOR_EMBEDDIT 234 +#define VENDOR_CAL 202 + +/* Gaisler Research device id's */ +#define GAISLER_LEON3 0x003 +#define GAISLER_LEON3DSU 0x004 +#define GAISLER_ETHAHB 0x005 +#define GAISLER_APBMST 0x006 +#define GAISLER_AHBUART 0x007 +#define GAISLER_SRCTRL 0x008 +#define GAISLER_SDCTRL 0x009 +#define GAISLER_APBUART 0x00C +#define GAISLER_IRQMP 0x00D +#define GAISLER_AHBRAM 0x00E +#define GAISLER_GPTIMER 0x011 +#define GAISLER_PCITRG 0x012 +#define GAISLER_PCISBRG 0x013 +#define GAISLER_PCIFBRG 0x014 +#define GAISLER_PCITRACE 0x015 +#define GAISLER_PCIDMA 0x016 +#define GAISLER_AHBTRACE 0x017 +#define GAISLER_ETHDSU 0x018 +#define GAISLER_PIOPORT 0x01A +#define GAISLER_AHBJTAG 0x01c +#define GAISLER_SPW 0x01f +#define GAISLER_ATACTRL 0x024 +#define GAISLER_VGA 0x061 +#define GAISLER_KBD 0X060 +#define GAISLER_ETHMAC 0x01D +#define GAISLER_DDRSPA 0x025 +#define GAISLER_EHCI 0x026 +#define GAISLER_UHCI 0x027 +#define GAISLER_SPW2 0x029 +#define GAISLER_DDR2SPA 0x02E +#define GAISLER_AHBSTAT 0x052 +#define GAISLER_FTMCTRL 0x054 + +#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */ +#define GAISLER_L2C 0xffe /* internal device: leon2compat */ +#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */ + + +/* European Space Agency device id's */ +#define ESA_LEON2 0x2 +#define ESA_MCTRL 0xF + +/* Opencores device id's */ +#define OPENCORES_PCIBR 0x4 +#define OPENCORES_ETHMAC 0x5 + +/* Vendor codes */ + +/* + * + * Macros for manipulating Configuration registers + * + */ + +#define amba_vendor(x) (((x) >> 24) & 0xff) + +#define amba_device(x) (((x) >> 12) & 0xfff) + +#define amba_membar_start(mbar) \ + (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16)) + +#define amba_iobar_start(base, iobar) \ + ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) ) + +#define amba_irq(conf) ((conf) & 0xf) + +#define amba_ver(conf) (((conf)>>5) & 0x1f) + +#define amba_membar_type(mbar) ((mbar) & 0xf) + +#define amba_membar_mask(mbar) (((mbar)>>4) & 0xfff) + +#define AMBA_TYPE_APBIO 0x1 +#define AMBA_TYPE_MEM 0x2 +#define AMBA_TYPE_AHBIO 0x3 + +#define AMBA_TYPE_AHBIO_ADDR(addr) (LEON3_IO_AREA | ((addr) >> 12)) + +#ifndef __ASSEMBLER__ + +#ifdef CONFIG_CMD_AMBAPP + +/* AMBA Plug&Play relocation & initialization */ +int ambapp_init_reloc(void); + +/* AMBA Plug&Play Name of Vendors and devices */ + +/* Return name of device */ +char *ambapp_device_id2str(int vendor, int id); + +/* Return name of vendor */ +char *ambapp_vendor_id2str(int vendor); +#endif + +/* + * Types and structure used for AMBA Plug & Play bus scanning + */ + +/* AMBA Plug&Play AHB information layout */ +typedef struct { + unsigned int conf; + unsigned int userdef[3]; + unsigned int bars[4]; +} ahbctrl_pp_dev; + +/* Prototypes for scanning AMBA Plug&Play bus for AMBA + * i) AHB Masters + * ii) AHB Slaves + * iii) APB Slaves (APB MST is a AHB Slave) + */ + +typedef struct { + unsigned char irq; + unsigned char ver; + unsigned int address; +} ambapp_apbdev; + +typedef struct { + unsigned char irq; + unsigned char ver; + unsigned int userdef[3]; + unsigned int address[4]; +} ambapp_ahbdev; + +/* AMBA Plug&Play AHB Masters & Slaves information locations + * Max devices is 64 supported by HW, however often only 8 + * are used. + */ +typedef struct { + ahbctrl_pp_dev masters[64]; + ahbctrl_pp_dev slaves[64]; +} ahbctrl_info; + +/* AMBA Plug&Play AHB information layout */ +typedef struct { + unsigned int conf; + unsigned int bar; +} apbctrl_pp_dev; + +/* All functions return the number of found devices + * 0 = no devices found + */ + +/****************************** APB SLAVES ******************************/ +int ambapp_apb_count( + unsigned int vendor, + unsigned int driver + ); + +int ambapp_apb_first( + unsigned int vendor, + unsigned int driver, + ambapp_apbdev *dev + ); + +int ambapp_apb_next( + unsigned int vendor, + unsigned int driver, + ambapp_apbdev *dev, + int index + ); + +int ambapp_apbs_first( + unsigned int vendor, + unsigned int driver, + ambapp_apbdev *dev, + int max_cnt + ); + +/****************************** AHB MASTERS ******************************/ +int ambapp_ahbmst_count( + unsigned int vendor, + unsigned int driver + ); + +int ambapp_ahbmst_first( + unsigned int vendor, + unsigned int driver, + ambapp_ahbdev *dev + ); + +int ambapp_ahbmst_next( + unsigned int vendor, + unsigned int driver, + ambapp_ahbdev *dev, + int index + ); + +int ambapp_ahbmsts_first( + unsigned int vendor, + unsigned int driver, + ambapp_ahbdev *dev, + int max_cnt + ); + +/****************************** AHB SLAVES ******************************/ +int ambapp_ahbslv_count( + unsigned int vendor, + unsigned int driver + ); + +int ambapp_ahbslv_first( + unsigned int vendor, + unsigned int driver, + ambapp_ahbdev *dev + ); + +int ambapp_ahbslv_next( + unsigned int vendor, + unsigned int driver, + ambapp_ahbdev *dev, + int index + ); + +int ambapp_ahbslvs_first( + unsigned int vendor, + unsigned int driver, + ambapp_ahbdev *dev, + int max_cnt + ); + +/*************************** AHB/APB only regs functions ************************* + * During start up, no memory is available we can use the simplified functions + * to get to the memory controller. + * + * Functions uses no stack/memory, only registers. + */ +unsigned int ambapp_apb_next_nomem( + register unsigned int vendor, /* Plug&Play Vendor ID */ + register unsigned int driver, /* Plug&Play Device ID */ + register int index); + +ahbctrl_pp_dev *ambapp_ahb_next_nomem( + register unsigned int vendor, /* Plug&Play Vendor ID */ + register unsigned int driver, /* Plug&Play Device ID */ + register unsigned int opts, /* scan for AHB 1=slave, 0=masters */ + register int index); + + +unsigned int ambapp_ahb_get_info(ahbctrl_pp_dev *ahb, int info); + +/*************************** AMBA Plug&Play device register MAPS *****************/ + +/* + * The following defines the bits in the LEON UART Status Registers. + */ + +#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ +#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ +#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ +#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ +#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ +#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ +#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ +#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ + +/* + * The following defines the bits in the LEON UART Ctrl Registers. + */ + +#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ +#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ +#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ +#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ +#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ +#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ +#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ +#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ +#define LEON_REG_UART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */ + +#define LEON3_GPTIMER_EN 1 +#define LEON3_GPTIMER_RL 2 +#define LEON3_GPTIMER_LD 4 +#define LEON3_GPTIMER_IRQEN 8 + +/* + * The following defines the bits in the LEON PS/2 Status Registers. + */ + +#define LEON_REG_PS2_STATUS_DR 0x00000001 /* Data Ready */ +#define LEON_REG_PS2_STATUS_PE 0x00000002 /* Parity error */ +#define LEON_REG_PS2_STATUS_FE 0x00000004 /* Framing error */ +#define LEON_REG_PS2_STATUS_KI 0x00000008 /* Keyboard inhibit */ + + +/* + * The following defines the bits in the LEON PS/2 Ctrl Registers. + */ + +#define LEON_REG_PS2_CTRL_RE 0x00000001 /* Receiver enable */ +#define LEON_REG_PS2_CTRL_TE 0x00000002 /* Transmitter enable */ +#define LEON_REG_PS2_CTRL_RI 0x00000004 /* Keyboard receive interrupt */ +#define LEON_REG_PS2_CTRL_TI 0x00000008 /* Keyboard transmit interrupt */ + +typedef struct { + volatile unsigned int ilevel; + volatile unsigned int ipend; + volatile unsigned int iforce; + volatile unsigned int iclear; + volatile unsigned int mstatus; + volatile unsigned int notused[11]; + volatile unsigned int cpu_mask[16]; + volatile unsigned int cpu_force[16]; +} ambapp_dev_irqmp; + +typedef struct { + volatile unsigned int data; + volatile unsigned int status; + volatile unsigned int ctrl; + volatile unsigned int scaler; +} ambapp_dev_apbuart; + +typedef struct { + volatile unsigned int val; + volatile unsigned int rld; + volatile unsigned int ctrl; + volatile unsigned int unused; +} ambapp_dev_gptimer_element; + +#define LEON3_GPTIMER_CTRL_EN 0x1 /* Timer enable */ +#define LEON3_GPTIMER_CTRL_RS 0x2 /* Timer reStart */ +#define LEON3_GPTIMER_CTRL_LD 0x4 /* Timer reLoad */ +#define LEON3_GPTIMER_CTRL_IE 0x8 /* interrupt enable */ +#define LEON3_GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */ +#define LEON3_GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */ + + +typedef struct { + volatile unsigned int scalar; + volatile unsigned int scalar_reload; + volatile unsigned int config; + volatile unsigned int unused; + volatile ambapp_dev_gptimer_element e[8]; +} ambapp_dev_gptimer; + +typedef struct { + volatile unsigned int iodata; + volatile unsigned int ioout; + volatile unsigned int iodir; + volatile unsigned int irqmask; + volatile unsigned int irqpol; + volatile unsigned int irqedge; +} ambapp_dev_ioport; + +typedef struct { + volatile unsigned int write; + volatile unsigned int dummy; + volatile unsigned int txcolor; + volatile unsigned int bgcolor; +} ambapp_dev_textvga; + +typedef struct { + volatile unsigned int data; + volatile unsigned int status; + volatile unsigned int ctrl; +} ambapp_dev_apbps2; + +typedef struct { + unsigned int mcfg1,mcfg2,mcfg3; +} ambapp_dev_mctrl; + +typedef struct { + unsigned int sdcfg; +} ambapp_dev_sdctrl; + +typedef struct { + unsigned int cfg1; + unsigned int cfg2; + unsigned int cfg3; +} ambapp_dev_ddr2spa; + +typedef struct { + unsigned int ctrl; + unsigned int cfg; +} ambapp_dev_ddrspa; + +#endif + +#endif diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index f3965ef..3387612 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -13,6 +13,7 @@ * Alphabetical list of all possible commands. */ +#define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */ #define CONFIG_CMD_ASKENV /* ask for env variable */ #define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ #define CONFIG_CMD_BDI /* bdinfo */

3 3

[U-Boot-Users] [PATCH 7/8] SPARC: Added GRETH Ethernet 10/100/1000 support for LEON3
by Daniel Hellstrom 13 Mar '08

13 Mar '08

GRETH is an Ethernet 10/100 or 10/100/1000 MAC with out without a debug link (EDCL). The GRETH core is documented in GRIP.pdf available at www.gaisler.com. If the GRETH has GigaBit support (GBIT, Scatter gather, checksum offloading etc.) can be determined by a bit in the control register. The GBIT MAC is supported by operating in GRTEH 10/100 legacy mode. Best Regards, Daniel Hellstrom drivers/net/Makefile | 1 + drivers/net/greth.c | 644 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/greth.h | 97 ++++++++ net/eth.c | 4 + 4 files changed, 746 insertions(+), 0 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b9723fa..be3a232 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -57,6 +57,7 @@ COBJS-y += tigon3.o COBJS-y += tsec.o COBJS-y += tsi108_eth.o COBJS-y += uli526x.o +COBJS-y += greth.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/greth.c b/drivers/net/greth.c new file mode 100644 index 0000000..3084771 --- /dev/null +++ b/drivers/net/greth.c @@ -0,0 +1,644 @@ +/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver + * + * Driver use polling mode (no Interrupt) + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel(a)gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <net.h> + +#ifdef CONFIG_GRETH + +#include <malloc.h> +#include <asm/processor.h> +#include <ambapp.h> +#include <asm/leon.h> + +/* #define DEBUG */ + +#include "greth.h" + +/* Default to 3s timeout on autonegotiation */ +#ifndef GRETH_PHY_TIMEOUT_MS + #define GRETH_PHY_TIMEOUT_MS 3000 +#endif + +/* ByPass Cache when reading regs */ +#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr) +/* Write-through cache ==> no bypassing needed on writes */ +#define GRETH_REGSAVE(addr,data) (*(unsigned int *)(addr) = (data)) +#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data) +#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data) + +#define GRETH_RXBD_CNT 4 +#define GRETH_TXBD_CNT 1 + +#define GRETH_RXBUF_SIZE 1540 +#define GRETH_BUF_ALIGN 4 +#define GRETH_RXBUF_EFF_SIZE \ + ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN ) + +typedef struct { + greth_regs *regs; + int irq; + struct eth_device *dev; + + /* Hardware info */ + unsigned char phyaddr; + int gbit_mac; + + /* Current operating Mode */ + int gb; /* GigaBit */ + int fd; /* Full Duplex */ + int sp; /* 10/100Mbps speed (1=100,0=10) */ + int auto_neg; /* Auto negotiate done */ + + unsigned char hwaddr[6]; /* MAC Address */ + + /* Descriptors */ + greth_bd *rxbd_base, *rxbd_max; + greth_bd *txbd_base, *txbd_max; + + greth_bd *rxbd_curr; + + /* rx buffers in rx descriptors */ + void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */ + + /* unused for gbit_mac, temp buffer for sending packets with unligned + * start. + * Pointer to packet allocated with malloc. + */ + void *txbuf; + + struct { + /* rx status */ + unsigned int rx_packets, + rx_crc_errors, + rx_frame_errors, + rx_length_errors, + rx_errors; + + /* tx stats*/ + unsigned int tx_packets, + tx_latecol_errors, + tx_underrun_errors, + tx_limit_errors, + tx_errors; + } stats; +} greth_priv; + +/* Read MII register 'addr' from core 'regs' */ +static int read_mii(int addr, volatile greth_regs *regs) +{ + while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {} + + GRETH_REGSAVE(&regs->mdio, (0 << 11) | ((addr&0x1F) << 6) | 2); + + while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {} + + if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) { + return (GRETH_REGLOAD(&regs->mdio)>>16)&0xFFFF; + } + else { + return -1; + } +} + +static void write_mii(int addr, int data, volatile greth_regs *regs) +{ + while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {} + + GRETH_REGSAVE(&regs->mdio, + ((data&0xFFFF)<<16) | (0 << 11) | ((addr&0x1F) << 6) | 1); + + while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {} + +} + +/* init/start hardware and allocate descriptor buffers for rx side + * + */ +int greth_init(struct eth_device *dev, bd_t * bis) +{ + int i; + + greth_priv *greth = dev->priv; + greth_regs *regs = greth->regs; +#ifdef DEBUG + printf("greth_init\n"); +#endif + + GRETH_REGSAVE(&regs->control,0); + + if ( !greth->rxbd_base ){ + + /* allocate descriptors */ + greth->rxbd_base = (greth_bd *) + memalign(0x1000,GRETH_RXBD_CNT*sizeof(greth_bd)); + greth->txbd_base = (greth_bd *) + memalign(0x1000,GRETH_RXBD_CNT*sizeof(greth_bd)); + + /* allocate buffers to all descriptors */ + greth->rxbuf_base = + malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT); + } + + /* initate rx decriptors */ + for(i=0; i<GRETH_RXBD_CNT; i++){ + greth->rxbd_base[i].addr = (unsigned int) + greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE*i); + /* enable desciptor & set wrap bit if last descriptor */ + if ( i >= (GRETH_RXBD_CNT-1) ){ + greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR; + }else{ + greth->rxbd_base[i].stat = GRETH_BD_EN; + } + } + + /* initiate indexes */ + greth->rxbd_curr = greth->rxbd_base; + greth->rxbd_max = greth->rxbd_base+(GRETH_RXBD_CNT-1); + greth->txbd_max = greth->txbd_base+(GRETH_TXBD_CNT-1); + /* + * greth->txbd_base->addr = 0; + * greth->txbd_base->stat = GRETH_BD_WR; + */ + + /* initate tx decriptors */ + for(i=0; i<GRETH_TXBD_CNT; i++){ + greth->txbd_base[i].addr = 0; + /* enable desciptor & set wrap bit if last descriptor */ + if ( i >= (GRETH_RXBD_CNT-1) ){ + greth->txbd_base[i].stat = GRETH_BD_WR; + }else{ + greth->txbd_base[i].stat = 0; + } + } + + /**** SET HARDWARE REGS ****/ + + /* Set pointer to tx/rx descriptor areas */ + GRETH_REGSAVE(&regs->rx_desc_p,(unsigned int)&greth->rxbd_base[0]); + GRETH_REGSAVE(&regs->tx_desc_p,(unsigned int)&greth->txbd_base[0]); + + /* Enable Transmitter, GRETH will now scan descriptors for packets + * to transmitt */ +#ifdef DEBUG + printf("greth_init: enabling receiver\n"); +#endif + GRETH_REGORIN(&regs->control, GRETH_RXEN); + + return 0; +} + +/* Initiate PHY to a relevant speed + * return: + * - 0 = success + * - 1 = timeout/fail + */ +int greth_init_phy(greth_priv *dev, bd_t * bis) +{ + greth_regs *regs = dev->regs; + int tmp,tmp1,tmp2,i; + unsigned int start, timeout; + + /* X msecs to ticks */ + timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS*1000); + + /* Get system timer0 current value + * Total timeout is 5s + */ + start = get_timer(0); + + /* get phy control register default values */ + + while ((tmp = read_mii(0, regs)) & 0x8000) { + if ( get_timer(start) > timeout ) + return 1; /* Fail */ + } + + /* reset PHY and wait for completion */ + write_mii(0, 0x8000 | tmp, regs); + + while (((tmp = read_mii(0, regs))) & 0x8000) { + if ( get_timer(start) > timeout ) + return 1; /* Fail */ + } + + /* Check if PHY is autoneg capable and then determine operating + * mode, otherwise force it to 10 Mbit halfduplex + */ + dev->gb = 0; + dev->fd = 0; + dev->sp = 0; + dev->auto_neg = 0; + if (!((tmp >> 12) & 1)) { + write_mii(0, 0, regs); + } else { + /* wait for auto negotiation to complete and then check operating mode */ + dev->auto_neg = 1; + i = 0; + while (!(((tmp = read_mii(1, regs)) >> 5) & 1)) { + if ( get_timer(start) > timeout ) { + printf("Auto negotiation timed out. " + "Selecting default config\n"); + tmp = read_mii(0, regs); + dev->gb = ((tmp >> 6) & 1) && !((tmp >> 13) & 1); + dev->sp = !((tmp >> 6) & 1) && ((tmp >> 13) & 1); + dev->fd = (tmp >> 8) & 1; + goto auto_neg_done; + } + } + if ((tmp >> 8) & 1) { + tmp1 = read_mii(9, regs); + tmp2 = read_mii(10, regs); + if ( (tmp1 & GRETH_MII_EXTADV_1000FD) && + (tmp2 & GRETH_MII_EXTPRT_1000FD)) { + dev->gb = 1; + dev->fd = 1; + } + if ( (tmp1 & GRETH_MII_EXTADV_1000HD) && + (tmp2 & GRETH_MII_EXTPRT_1000HD)) { + dev->gb = 1; + dev->fd = 0; + } + } + if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) { + tmp1 = read_mii(4, regs); + tmp2 = read_mii(5, regs); + if ( (tmp1 & GRETH_MII_100TXFD) && + (tmp2 & GRETH_MII_100TXFD)) { + dev->sp = 1; + dev->fd = 1; + } + if ( (tmp1 & GRETH_MII_100TXHD) && + (tmp2 & GRETH_MII_100TXHD)) { + dev->sp = 1; + dev->fd = 0; + } + if ( (tmp1 & GRETH_MII_10FD) && + (tmp2 & GRETH_MII_10FD)) { + dev->fd = 1; + } + if ((dev->gb == 1) && (dev->gbit_mac == 0)) { + dev->gb = 0; + dev->fd = 0; + write_mii(0, dev->sp << 13, regs); + } + } + + } +auto_neg_done: +#ifdef DEBUG + printf("%s GRETH Ethermac at [0x%x] irq %d. Running \ + %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000":"10/100", + (unsigned int)(regs), (unsigned int)(dev->irq), + dev->gb ? 1000:(dev->sp ? 100:10), dev->fd ? "full":"half"); +#endif + /* Read out PHY info if extended registers are available */ + if (tmp & 1) { + tmp1 = read_mii(2, regs); + tmp2 = read_mii(3, regs); + tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F); + tmp = tmp2 & 0xF; + + tmp2 = (tmp2 >> 4) & 0x3F; +#ifdef DEBUG + printf("PHY: Vendor %x Device %x Revision %d\n", tmp1, tmp2, tmp); +#endif + } else { + printf("PHY info not available\n"); + } + + /* set speed and duplex bits in control register */ + GRETH_REGORIN(&regs->control, (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4)); + + return 0; +} + +void greth_halt(struct eth_device *dev) +{ + greth_priv *greth; + greth_regs *regs; + int i; +#ifdef DEBUG + printf("greth_halt\n"); +#endif + if ( !dev || !dev->priv) + return; + + greth = dev->priv; + regs = greth->regs; + + if ( !regs ) + return; + + /* disable receiver/transmitter by clearing the enable bits */ + GRETH_REGANDIN(&regs->control,~(GRETH_RXEN|GRETH_TXEN)); + + /* reset rx/tx descriptors */ + if ( greth->rxbd_base ){ + for(i=0; i<GRETH_RXBD_CNT; i++){ + greth->rxbd_base[i].stat = (i >= (GRETH_RXBD_CNT-1)) ? GRETH_BD_WR : 0; + } + } + + if ( greth->txbd_base ){ + for(i=0; i<GRETH_TXBD_CNT; i++){ + greth->txbd_base[i].stat = (i >= (GRETH_TXBD_CNT-1)) ? GRETH_BD_WR : 0; + } + } +} + +int greth_send(struct eth_device *dev, volatile void *eth_data, + int data_length) +{ + greth_priv *greth = dev->priv; + greth_regs *regs = greth->regs; + greth_bd *txbd; + void *txbuf; + unsigned int status; +#ifdef DEBUG + printf("greth_send\n"); +#endif + /* send data, wait for data to be sent, then return */ + if ( ((unsigned int)eth_data&(GRETH_BUF_ALIGN-1)) && !greth->gbit_mac ){ + /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer + * and copy data to before giving it to GRETH. + */ + if ( !greth->txbuf ){ + greth->txbuf = malloc(GRETH_RXBUF_SIZE); +#ifdef DEBUG + printf("GRETH: allocated aligned tx-buf\n"); +#endif + } + + txbuf = greth->txbuf; + + /* copy data info buffer */ + memcpy((char *)txbuf,(char *)eth_data,data_length); + + /* keep buffer to next time */ + }else{ + txbuf = (void *)eth_data; + } + /* get descriptor to use, only 1 supported... hehe easy */ + txbd = greth->txbd_base; + + /* setup descriptor to wrap around to it self */ + txbd->addr = (unsigned int)txbuf; + txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length; + + /* Remind Core which descriptor to use when sending */ + GRETH_REGSAVE(&regs->tx_desc_p,(unsigned int)txbd); + + /* initate send by enabling transmitter */ + GRETH_REGORIN(&regs->control,GRETH_TXEN); + + /* Wait for data to be sent */ + while( (status=GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN ){ + ; + } + + /* was the packet transmitted succesfully? */ + if ( status & GRETH_TXBD_ERR_AL ){ + greth->stats.tx_limit_errors++; + } + + if ( status & GRETH_TXBD_ERR_UE ){ + greth->stats.tx_underrun_errors++; + } + + if ( status & GRETH_TXBD_ERR_LC ){ + greth->stats.tx_latecol_errors++; + } + + if ( status & (GRETH_TXBD_ERR_LC|GRETH_TXBD_ERR_UE|GRETH_TXBD_ERR_AL) ){ + /* any error */ + greth->stats.tx_errors++; + return -1; + } + + /* bump tx packet counter */ + greth->stats.tx_packets++; + + /* return succefully */ + return 0; +} + +int greth_recv(struct eth_device *dev) +{ + greth_priv *greth = dev->priv; + greth_regs *regs = greth->regs; + greth_bd *rxbd; + unsigned int status, len = 0, bad; + unsigned char *d; + int enable = 0; + int i; +#ifdef DEBUG +/* printf("greth_recv\n"); */ +#endif + /* Receive One packet only, but clear as many error packets as there are + * available. + */ + { + /* current receive descriptor */ + rxbd = greth->rxbd_curr; + + /* get status of next received packet */ + status = GRETH_REGLOAD(&rxbd->stat); + + bad = 0; + + /* stop if no more packets received */ + if (status & GRETH_BD_EN){ + goto done; + } + +#ifdef DEBUG + printf("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",(unsigned int)rxbd,status, status&GRETH_BD_LEN); +#endif + + /* Check status for errors. + */ + if (status & GRETH_RXBD_ERR_FT) { + greth->stats.rx_length_errors++; + bad = 1; + } + if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) { + greth->stats.rx_frame_errors++; + bad = 1; + } + if (status & GRETH_RXBD_ERR_CRC) { + greth->stats.rx_crc_errors++; + bad = 1; + } + if (bad) { + greth->stats.rx_errors++; + printf("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",greth->stats.rx_length_errors,greth->stats.rx_frame_errors,greth->stats.rx_crc_errors,status,greth->stats.rx_packets); + /* print all rx descriptors */ + for(i=0; i<GRETH_RXBD_CNT ; i++){ + printf("[%d]: Stat=0x%lx, Addr=0x%lx\n",i,GRETH_REGLOAD(&greth->rxbd_base[i].stat),GRETH_REGLOAD(&greth->rxbd_base[i].addr)); + } + }else{ + /* Process the incoming packet. */ + len = status & GRETH_BD_LEN; + d = (char *)rxbd->addr; +#ifdef DEBUG + printf("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",len,d[0],d[1],d[2],d[3],d[4],d[5],d[6],d[7]); +#endif + /* flush all data cache to make sure we're not reading old packet data */ + sparc_dcache_flush_all(); + + /* pass packet on to network subsystem */ + NetReceive((void *)d,len); + + /* bump stats counters */ + greth->stats.rx_packets++; + + /* bad is now 0 ==> will stop loop */ + } + + /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */ + rxbd->stat = GRETH_BD_EN | (((unsigned int)greth->rxbd_curr >= (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0); + enable = 1; + + /* increase index */ + greth->rxbd_curr = ((unsigned int)greth->rxbd_curr >= (unsigned int)greth->rxbd_max) ? greth->rxbd_base : (greth->rxbd_curr+1); + + }; + + if ( enable ){ + GRETH_REGORIN(&regs->control, GRETH_RXEN); + } +done: + /* return positive length of packet or 0 if non recieved */ + return len; +} + +void greth_set_hwaddr(greth_priv *greth, unsigned char *mac) +{ + /* save new MAC address */ + greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0]; + greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1]; + greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2]; + greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3]; + greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4]; + greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5]; + greth->regs->esa_msb = (mac[0]<<8) | mac[1]; + greth->regs->esa_lsb = (mac[2]<<24) | (mac[3]<<16) | (mac[4]<<8) | mac[5]; +#ifdef DEBUG + printf("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); +#endif +} + +int greth_initialize(bd_t * bis) +{ + greth_priv *greth; + ambapp_apbdev apbdev; + struct eth_device *dev; + int i; + char *addr_str, *end; + unsigned char addr[6]; +#ifdef DEBUG + printf("Scanning for GRETH\n"); +#endif + /* Find Device & IRQ via AMBA Plug&Play information */ + if ( ambapp_apb_first(VENDOR_GAISLER,GAISLER_ETHMAC,&apbdev) != 1 ){ + return -1; /* GRETH not found */ + } + + greth = (greth_priv *)malloc(sizeof(greth_priv)); + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + memset(dev, 0, sizeof(struct eth_device)); + memset(greth, 0, sizeof(greth_priv)); + + greth->regs = (greth_regs *)apbdev.address; + greth->irq = apbdev.irq; +#ifdef DEBUG + printf("Found GRETH at 0x%lx, irq %d\n",greth->regs,greth->irq); +#endif + dev->priv = (void *)greth; + dev->iobase = (unsigned int)greth->regs; + dev->init = greth_init; + dev->halt = greth_halt; + dev->send = greth_send; + dev->recv = greth_recv; + greth->dev = dev; + + /* Reset Core */ + GRETH_REGSAVE(&greth->regs->control, GRETH_RESET); + + /* Wait for core to finish reset cycle */ + while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) + ; + + /* Get the phy address which assumed to have been set + correctly with the reset value in hardware */ + greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F; + + /* Check if mac is gigabit capable */ + greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1; + + /* Make descriptor string */ + if ( greth->gbit_mac ){ + sprintf(dev->name, "GRETH 10/100/GB"); + }else{ + sprintf(dev->name, "GRETH 10/100"); + } + + /* initiate PHY, select speed/duplex depending on connected PHY */ + if ( greth_init_phy(greth, bis) ){ + /* Failed to init PHY (timedout) */ + return -1; + } + + /* Register Device to EtherNet subsystem */ + eth_register(dev); + + /* Get MAC address */ + if ( (addr_str=getenv("ethaddr")) != NULL ) { + for (i=0; i<6; i++) { + addr[i] = addr_str ? simple_strtoul(addr_str, &end, 16) : 0; + if (addr_str){ + addr_str = (*end) ? end+1 : end; + } + } + }else{ + /* HW Address not found in environment, Set default HW address */ + addr[0] = GRETH_HWADDR_0; /* MSB */ + addr[1] = GRETH_HWADDR_1; + addr[2] = GRETH_HWADDR_2; + addr[3] = GRETH_HWADDR_3; + addr[4] = GRETH_HWADDR_4; + addr[5] = GRETH_HWADDR_5; /* LSB */ + } + + /* set and remember MAC address */ + greth_set_hwaddr(greth,addr); + + return 1; +} + +#endif diff --git a/drivers/net/greth.h b/drivers/net/greth.h new file mode 100644 index 0000000..7f75b74 --- /dev/null +++ b/drivers/net/greth.h @@ -0,0 +1,97 @@ +/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel(a)gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define GRETH_FD 0x10 +#define GRETH_RESET 0x40 +#define GRETH_MII_BUSY 0x8 +#define GRETH_MII_NVALID 0x10 + +/* MII registers */ +#define GRETH_MII_EXTADV_1000FD 0x00000200 +#define GRETH_MII_EXTADV_1000HD 0x00000100 +#define GRETH_MII_EXTPRT_1000FD 0x00000800 +#define GRETH_MII_EXTPRT_1000HD 0x00000400 + +#define GRETH_MII_100T4 0x00000200 +#define GRETH_MII_100TXFD 0x00000100 +#define GRETH_MII_100TXHD 0x00000080 +#define GRETH_MII_10FD 0x00000040 +#define GRETH_MII_10HD 0x00000020 + +#define GRETH_BD_EN 0x800 +#define GRETH_BD_WR 0x1000 +#define GRETH_BD_IE 0x2000 +#define GRETH_BD_LEN 0x7FF + +#define GRETH_TXEN 0x1 +#define GRETH_INT_TX 0x8 +#define GRETH_TXI 0x4 +#define GRETH_TXBD_STATUS 0x0001C000 +#define GRETH_TXBD_MORE 0x20000 +#define GRETH_TXBD_IPCS 0x40000 +#define GRETH_TXBD_TCPCS 0x80000 +#define GRETH_TXBD_UDPCS 0x100000 +#define GRETH_TXBD_ERR_LC 0x10000 +#define GRETH_TXBD_ERR_UE 0x4000 +#define GRETH_TXBD_ERR_AL 0x8000 +#define GRETH_TXBD_NUM 128 +#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1) +#define GRETH_TX_BUF_SIZE 2048 + +#define GRETH_INT_RX 0x4 +#define GRETH_RXEN 0x2 +#define GRETH_RXI 0x8 +#define GRETH_RXBD_STATUS 0xFFFFC000 +#define GRETH_RXBD_ERR_AE 0x4000 +#define GRETH_RXBD_ERR_FT 0x8000 +#define GRETH_RXBD_ERR_CRC 0x10000 +#define GRETH_RXBD_ERR_OE 0x20000 +#define GRETH_RXBD_ERR_LE 0x40000 +#define GRETH_RXBD_IP_DEC 0x80000 +#define GRETH_RXBD_IP_CSERR 0x100000 +#define GRETH_RXBD_UDP_DEC 0x200000 +#define GRETH_RXBD_UDP_CSERR 0x400000 +#define GRETH_RXBD_TCP_DEC 0x800000 +#define GRETH_RXBD_TCP_CSERR 0x1000000 + +#define GRETH_RXBD_NUM 128 +#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1) +#define GRETH_RX_BUF_SIZE 2048 + +/* Ethernet configuration registers */ +typedef struct _greth_regs { + volatile unsigned int control; + volatile unsigned int status; + volatile unsigned int esa_msb; + volatile unsigned int esa_lsb; + volatile unsigned int mdio; + volatile unsigned int tx_desc_p; + volatile unsigned int rx_desc_p; +} greth_regs; + +/* Ethernet buffer descriptor */ +typedef struct _greth_bd { + volatile unsigned int stat; + unsigned int addr; /* Buffer address not changed by HW */ +} greth_bd; diff --git a/net/eth.c b/net/eth.c index 16a6dcb..3b86f87 100644 --- a/net/eth.c +++ b/net/eth.c @@ -60,6 +60,7 @@ extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); +extern int greth_initialize(bd_t *); extern int atngw100_eth_initialize(bd_t *); extern int mcffec_initialize(bd_t*); extern int mcdmafec_initialize(bd_t*); @@ -275,6 +276,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_ATSTK1000) atstk1000_eth_initialize(bis); #endif +#if defined(CONFIG_GRETH) + greth_initialize(bis); +#endif #if defined(CONFIG_ATNGW100) atngw100_eth_initialize(bis); #endif

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[U-Boot-Users] [PATCH 8/8] SPARC: Added LEON2 and LEON3 boards and simulators
by Daniel Hellstrom 13 Mar '08

13 Mar '08

This patch adds support for three LEON3 boards: * GR-XC3S-1500 (Low cost Xilinx Spartan FPGA board) * GR-CPCI-AX2000 (AX system with switchable AX FPGA) * ALTERA NIOS Development board, Stratix II edition The simulators GRSIM and TSIM for LEON2 and LEON3 has been added as a board. A separate board is needed due to that the FLASH CFI interface has not been implemented in the simulators. Configuring the GR-XC3S-1500 board without FLASH support should run in the simulator. Note that by board support I mean support for the pre synthezied template design for the board in question. Supporting any configuration is not possible but almost, due to the Plug & Play system... The FPGA can be programmed with the template design by: $ cd grlib/designs/BOARD $ make ise-prog-prom-ref Best Regards, Daniel Hellstrom MAKEALL | 2 +- Makefile | 21 ++ board/gaisler/gr_cpci_ax2000/Makefile | 52 ++++ board/gaisler/gr_cpci_ax2000/config.mk | 37 +++ board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c | 54 ++++ board/gaisler/gr_cpci_ax2000/u-boot.lds | 160 ++++++++++ board/gaisler/gr_ep2s60/Makefile | 52 ++++ board/gaisler/gr_ep2s60/config.mk | 35 +++ board/gaisler/gr_ep2s60/gr_ep2s60.c | 54 ++++ board/gaisler/gr_ep2s60/u-boot.lds | 160 ++++++++++ board/gaisler/gr_xc3s_1500/Makefile | 52 ++++ board/gaisler/gr_xc3s_1500/config.mk | 34 ++ board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c | 54 ++++ board/gaisler/gr_xc3s_1500/u-boot.lds | 162 ++++++++++ board/gaisler/grsim/Makefile | 50 +++ board/gaisler/grsim/config.mk | 34 ++ board/gaisler/grsim/grsim.c | 43 +++ board/gaisler/grsim/u-boot.lds | 161 ++++++++++ board/gaisler/grsim_leon2/Makefile | 50 +++ board/gaisler/grsim_leon2/config.mk | 34 ++ board/gaisler/grsim_leon2/grsim_leon2.c | 44 +++ board/gaisler/grsim_leon2/u-boot.lds | 159 ++++++++++ include/configs/gr_cpci_ax2000.h | 398 +++++++++++++++++++++++++ include/configs/gr_ep2s60.h | 348 +++++++++++++++++++++ include/configs/grsim.h | 388 ++++++++++++++++++++++++ include/configs/grsim_leon2.h | 378 +++++++++++++++++++++++ include/configs/grxc3s1500.h | 334 +++++++++++++++++++++ 27 files changed, 3349 insertions(+), 1 deletions(-) The patch is larger than 40Kb, you can find it at ftp://ftp.gaisler.com/gaisler.com/u-boot/patches/8_sparc_boards.patch

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[U-Boot-Users] [PATCH 6/8] SPARC: Added SMC91111 support for LEON2 and LEON3 processors
by Daniel Hellstrom 13 Mar '08

13 Mar '08

This patch makes SPARC/LEON processors able to read and write to the SMC91111 chip using the chip external I/O bus of the memory controller. This patchs defines the standard in and out macros expected by the SMC9111 driver. To access that I/O bus one must set up the memory controller (MCTRL or FTMCTRL) correctly. It is assumed that the user sets up this correctly when the other MCTRL parameters are set up. It can be set up from the board configuration header file. Best Regards, Daniel Hellstrom drivers/net/smc91111.h | 74 +++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 73 insertions(+), 1 deletions(-) diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index d03cbc3..8d3976a 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -176,7 +176,79 @@ typedef unsigned long int dword; }; \ }) -#else /* if not CONFIG_PXA250 */ +#elif defined(CONFIG_LEON) /* if not CONFIG_PXA250 */ + +#define SMC_LEON_SWAP16(_x_) \ + ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) + +#define SMC_LEON_SWAP32(_x_) \ + ({ dword _x = (_x_); \ + ((_x << 24) | \ + ((0x0000FF00UL & _x) << 8) | \ + ((0x00FF0000UL & _x) >> 8) | \ + (_x >> 24)); }) + +#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))) +#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))) +#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))) +#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))) +#define SMC_inb(p) ({ \ + word ___v = SMC_inw((p) & ~1); \ + if (p & 1) ___v >>= 8; \ + else ___v &= 0xff; \ + ___v; }) +#define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d)) +#define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) +#define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d)) +#define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl_nosw( *(__b2 + __i), r); \ + } \ + }) +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw_nosw( *(__b2 + __i), r); \ + } \ + }) +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl_nosw(r); \ + SMC_inl(0); \ + }; \ + }) + +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw_nosw(r); \ + SMC_inw(0); \ + }; \ + }) + +#define SMC_insb(r,b,l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb(r); \ + SMC_inb(0); \ + }; \ + }) + +#else /* if not CONFIG_PXA250 and not CONFIG_LEON */ #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ /*

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[U-Boot-Users] [PATCH 4/8] SPARC: Added SPARC board information to bdinfo command
by Daniel Hellstrom 13 Mar '08

13 Mar '08

This patch adds support for the U-Boot command 'bdinfo' for SPARC boards, the output is as shown below. ###################### U-Boot 1.3.2-gb42c95ff-dirty (Mar 12 2008 - 21:07:56)Gaisler GRSIM CPU: LEON3 Board: GRSIM/TSIM Using default environment In: serial Out: serial Err: serial Net: GRETH 10/100 Type "run flash_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 => bdinfo memstart = 0x40000000 memsize = 0x04000000 flashstart = 0x00000000 CFG_MONITOR_BASE = 0x00000000 CFG_ENV_ADDR = 0x007F8000 CFG_RELOC_MONITOR_BASE = 0x43f8e000 (262144) CFG_MALLOC_BASE = 0x43fce000 (131072) CFG_INIT_SP_OFFSET = 0x43ffdfe0 (65504) CFG_PROM_OFFSET = 0x43ffe000 (8064) CFG_GBL_DATA_OFFSET = 0x43ffff80 (128) ethaddr = 00:00:7A:CC:00:12 IP addr = 192.168.0.80 baudrate = 38400 bps => ###################### Best Regards, Daniel Hellstrom commit 6bc2ec61fd40610461266f6a7f21a01a4a47016c Author: Daniel Hellstrom <daniel(a)gaisler.com> Date: Wed Mar 12 21:16:14 2008 +0100 SPARC: added SPARC board information to the command bdinfo. Signed-off-by: Daniel Hellstrom <daniel(a)gaisler.com> common/cmd_bdinfo.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index bbb0192..838c103 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -208,6 +208,40 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } +#elif defined(CONFIG_SPARC) /* SPARC */ +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + bd_t *bd = gd->bd; +#if defined(CONFIG_CMD_NET) + int i; +#endif + +#ifdef DEBUG + print_num ("bd address ",(ulong)bd); +#endif + print_num ("memstart ",bd->bi_memstart); + print_num ("memsize ",bd->bi_memsize); + print_num ("flashstart ",bd->bi_flashstart); + print_num ("CFG_MONITOR_BASE ",CFG_MONITOR_BASE); + print_num ("CFG_ENV_ADDR ",CFG_ENV_ADDR); + printf ("CFG_RELOC_MONITOR_BASE = 0x%lx (%d)\n",CFG_RELOC_MONITOR_BASE,CFG_MONITOR_LEN); + printf ("CFG_MALLOC_BASE = 0x%lx (%d)\n",CFG_MALLOC_BASE,CFG_MALLOC_LEN); + printf ("CFG_INIT_SP_OFFSET = 0x%lx (%d)\n",CFG_INIT_SP_OFFSET,CFG_STACK_SIZE); + printf ("CFG_PROM_OFFSET = 0x%lx (%d)\n",CFG_PROM_OFFSET,CFG_PROM_SIZE); + printf ("CFG_GBL_DATA_OFFSET = 0x%lx (%d)\n",CFG_GBL_DATA_OFFSET,CFG_GBL_DATA_SIZE); + +#if defined(CONFIG_CMD_NET) + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + puts ("\nIP addr = "); + print_IPaddr (bd->bi_ip_addr); +#endif + printf ("\nbaudrate = %6ld bps\n", bd->bi_baudrate ); + return 0; +} + #elif defined(CONFIG_M68K) /* M68K */ static void print_str(const char *, const char *);

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[U-Boot-Users] [PATCH 3/8] SPARC: Added support for SPARC/LEON2 and SPARC/LEON3 processors
by Daniel Hellstrom 13 Mar '08

13 Mar '08

This patch adds support for SPARC/LEON2 and SPARC/LEON3 to U-Boot. LEON2/3 boards are added with an extra patch, this patch must be applied first (before 8_sparc_boards.patch). This patch does not support LEON3 SMP system. Linux for SPARC assumes that there is a Sun Boot prom available. The boot prom is used as monitor to support basic features such as rebooting, printing to the system console (serial terminal in the LEON case) and getting information about the hardware (baudrate, main memory etc.). So, in order to boot SPARC Linux on LEON a standard boot prom is emulated. This is done in cpu/leon?/prom.c. The boot prom must be placed at a higher address that the stack to avoid that it gets overwritten. Some chip designs has UHCI and EHI USB. UHCI has been implemented for U-Boot on LEON3 systems. LEON3 processors is on an extended AMBA bus (with Plug&Play support), whereas LEON2 uses hardcoded addresses since it is on an AMBA bus without Plug&Play. ABOUT LEON3 and GRLIB --------------------- LEON3 is an open source (GPL) SPARC V7 and/or V8 processor part of GRLIB. GRLIB is a free comprehensive open source (GPL) Portable IP library (written in VHDL) featuring cores such as Ethernet 10/100/1000, SpaceWire, PCI, CAN, 1553, I2C, USB 1.1 and 2.0, SPI, DMA ATA, SVGA, PS/2, UART, Timer, SDRAM, SRAM, SSRAM, DDR, DDR2, FLASH/PROM, CPU Debug Unit, FPU, GPIO and many more. More info available at www.gaisler.com. ABOUT SPARC-ELF COMPILER ------------------------ Compiling u-boot for LEON3 and LEON2 has only been has only been tested with GCC 3.4.4 compiler with added LEON2 and LEON3 support available from www.gaisler.com or ftp://ftp.gaisler.com/gaisler.com/bcc/bin/linux/sparc-elf-3.4.4-1.0.30.tar.…, installation instructions can be found in bcc/doc/bcc.pdf. (extract to /opt/ and add /opt/sparc-elf-3.4.4/bin to PATH). U-BOOT support tested --------------------- - LEON3 (and LEON3FT Fault tolerant version) - LEON3 Simmulator (GRSIM and TSIM) - LEON2 Simmulator (GRSIM and TSIM) - Network (GRETH and SMC91111 and USB) - USB 1.1 (UHCI) - Linux and RTEMS booting - booting UBOOT from RAM and FLASH by changing board/gaisler/xxx/config.mk - DDR, DDR2, SRAM, FT-SRAM - UART, IRQ, Timer Best Regards, Daniel Hellstrom MAKEALL | 7 + Makefile | 16 +- README | 3 + cpu/leon2/Makefile | 54 ++ cpu/leon2/config.mk | 26 + cpu/leon2/cpu.c | 59 ++ cpu/leon2/cpu_init.c | 133 ++++ cpu/leon2/interrupts.c | 219 +++++++ cpu/leon2/prom.c | 1062 ++++++++++++++++++++++++++++++++ cpu/leon2/serial.c | 138 +++++ cpu/leon2/start.S | 657 ++++++++++++++++++++ cpu/leon3/Makefile | 54 ++ cpu/leon3/ambapp.c | 380 ++++++++++++ cpu/leon3/config.mk | 26 + cpu/leon3/cpu.c | 60 ++ cpu/leon3/cpu_init.c | 257 ++++++++ cpu/leon3/interrupts.c | 222 +++++++ cpu/leon3/prom.c | 1099 +++++++++++++++++++++++++++++++++ cpu/leon3/serial.c | 145 +++++ cpu/leon3/start.S | 616 +++++++++++++++++++ cpu/leon3/usb_uhci.c | 1275 +++++++++++++++++++++++++++++++++++++++ cpu/leon3/usb_uhci.h | 184 ++++++ examples/Makefile | 3 + examples/sparc.lds | 61 ++ examples/stubs.c | 16 + include/asm-sparc/asi.h | 137 +++++ include/asm-sparc/asmmacro.h | 45 ++ include/asm-sparc/atomic.h | 29 + include/asm-sparc/bitops.h | 32 + include/asm-sparc/byteorder.h | 35 ++ include/asm-sparc/cache.h | 113 ++++ include/asm-sparc/errno.h | 162 +++++ include/asm-sparc/global_data.h | 97 +++ include/asm-sparc/io.h | 95 +++ include/asm-sparc/irq.h | 43 ++ include/asm-sparc/leon.h | 37 ++ include/asm-sparc/leon2.h | 237 ++++++++ include/asm-sparc/leon3.h | 40 ++ include/asm-sparc/machines.h | 92 +++ include/asm-sparc/page.h | 43 ++ include/asm-sparc/posix_types.h | 134 ++++ include/asm-sparc/processor.h | 118 ++++ include/asm-sparc/prom.h | 300 +++++++++ include/asm-sparc/psr.h | 109 ++++ include/asm-sparc/ptrace.h | 181 ++++++ include/asm-sparc/srmmu.h | 311 ++++++++++ include/asm-sparc/stack.h | 163 +++++ include/asm-sparc/string.h | 55 ++ include/asm-sparc/types.h | 71 +++ include/asm-sparc/u-boot.h | 74 +++ include/asm-sparc/winmacro.h | 151 +++++ lib_sparc/Makefile | 45 ++ lib_sparc/board.c | 525 ++++++++++++++++ lib_sparc/cache.c | 33 + lib_sparc/interrupts.c | 119 ++++ lib_sparc/sparc_linux.c | 229 +++++++ lib_sparc/time.c | 77 +++ sparc_config.mk | 24 + 58 files changed, 10727 insertions(+), 1 deletions(-) The patch is larger than 40Kb, you can find it at ftp://ftp.gaisler.com/gaisler.com/u-boot/patches/3_sparc.patch

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[U-Boot-Users] [PATCH 2/8] SPARC: SPARC cfi-flash support for 64-bit reads
by Daniel Hellstrom 13 Mar '08

13 Mar '08

For current SPARC architectures (LEON2 and LEON3) each read from the FLASH must lead to a cache miss. This is because FLASH can not be set non-cacheable since program code resides there, and alternatively disabling cache is poor from performance view, or doing a cache flush between each read is even poorer. Forcing a cache miss on a SPARC is done by a special instruction "lda" - load alternative space, the alternative space number (ASI) is processor implementation spcific and can be found by including <asm/processor.h>. SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address. Best Regards, Daniel Hellstrom drivers/mtd/cfi_flash.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 439c950..6fc6bc4 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -241,8 +241,12 @@ static u32 flash_read32(void *addr) static u64 flash_read64(void *addr) { +#ifdef CONFIG_SPARC + return __raw_readq(addr); +#else /* No architectures currently implement __raw_readq() */ return *(volatile u64 *)addr; +#endif } /*-----------------------------------------------------------------------

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[U-Boot-Users] Gaining inches the permanent way
by Les Flaherty 13 Mar '08

13 Mar '08

Locker room envy is a thing of the past - with this you'll be the new Alpha Male http://www.Fantastifives.com/ Hung loose and large

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[U-Boot-Users] [PATCH 01/15 v2] rtc: Add M41T62 support
by Stefan Roese 13 Mar '08

13 Mar '08

This patch add support for the STM M41T62 RTC. It is used and tested on the AMCC Canyonlands 406EX platform. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/rtc/Makefile | 1 + drivers/rtc/m41t62.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/m41t62.c diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af2bf4..17c0f86 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -41,6 +41,7 @@ COBJS-y += ds174x.o COBJS-y += ds3231.o COBJS-y += m41t11.o COBJS-y += m41t60.o +COBJS-$(CONFIG_RTC_M41T62) += m41t62.o COBJS-y += max6900.o COBJS-y += m48t35ax.o COBJS-y += mc146818.o diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c new file mode 100644 index 0000000..002ebba --- /dev/null +++ b/drivers/rtc/m41t62.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * based on a the Linux rtc-m41t80.c driver which is: + * Alexander Bigga <ab(a)mycable.de>, 2006 (c) mycable GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for STMicroelectronics M41T62 + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> +#include <bcd.h> + +#if defined(CONFIG_CMD_DATE) + +#define M41T62_REG_SSEC 0 +#define M41T62_REG_SEC 1 +#define M41T62_REG_MIN 2 +#define M41T62_REG_HOUR 3 +#define M41T62_REG_WDAY 4 +#define M41T62_REG_DAY 5 +#define M41T62_REG_MON 6 +#define M41T62_REG_YEAR 7 +#define M41T62_REG_ALARM_MON 0xa +#define M41T62_REG_ALARM_DAY 0xb +#define M41T62_REG_ALARM_HOUR 0xc +#define M41T62_REG_ALARM_MIN 0xd +#define M41T62_REG_ALARM_SEC 0xe +#define M41T62_REG_FLAGS 0xf + +#define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1) +#define M41T62_ALARM_REG_SIZE \ + (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON) + +#define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */ +#define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */ +#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */ +#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ +#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */ +#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */ + +#define M41T62_FEATURE_HT (1 << 0) +#define M41T62_FEATURE_BL (1 << 1) + +void rtc_get(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + + debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " + "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", + __FUNCTION__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + tm->tm_sec = BCD2BIN(buf[M41T62_REG_SEC] & 0x7f); + tm->tm_min = BCD2BIN(buf[M41T62_REG_MIN] & 0x7f); + tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f); + tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f); + tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; + tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1; + + /* assume 20YY not 19YY, and ignore the Century Bit */ + /* U-Boot needs to add 1900 here */ + tm->tm_year = BCD2BIN(buf[M41T62_REG_YEAR]) + 100 + 1900; + + debug("%s: tm is secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __FUNCTION__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); +} + +void rtc_set(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + + /* Merge time-data and register flags into buf[0..7] */ + buf[M41T62_REG_SSEC] = 0; + buf[M41T62_REG_SEC] = + BIN2BCD(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f); + buf[M41T62_REG_MIN] = + BIN2BCD(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f); + buf[M41T62_REG_HOUR] = + BIN2BCD(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ; + buf[M41T62_REG_WDAY] = + (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07); + buf[M41T62_REG_DAY] = + BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); + buf[M41T62_REG_MON] = + BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f); + /* assume 20YY not 19YY */ + buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); + + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) + printf("I2C write failed in %s()\n", __func__); +} + +void rtc_reset(void) +{ + /* + * Nothing to do + */ +} + +#endif -- 1.5.4.4

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[U-Boot-Users] U-Boot hangs when try to access PCI window beyond 256 MB using md command
by vivek.trivedi＠wipro.com 13 Mar '08

13 Mar '08

Hi , We are using U-Boot-1.1.3 on a custom MPC8349ADS board with 2 PCI buses configured in Host mode.We have 256 MB DDR2 in our board. We have connected 8 DSPs on PCI bus 1. U-Boot is assigning base address for DSPs from 0x80000000 to 0x93800000. We are able to access any location from 0x80000000 to 0x0x8FFFFFFF i.e first 256 MB using md command in U-BOOT. But when i try to access any location starting from 0x90000000 to 0x93800000(next 256 MB), U-Boot hangs : =>md 0x90000000 90000000: Even though PCI LAWBARs and Outbound window is configured for 512 MB starting from 0x80000000. I am not able to understand why i am not able to access any location starting from 0x90000000. Please help me in as i have already wasted too much time in debugging this issue. I am also attaching the U-Boot PCI settings: We are Configuring PCI bus in Host mode with following settings: /* PCI window setting in include/configs/MPC8349ADS.h start */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ /* PCI window setting in MPC8349ADS.h start */ PCI LAWBARas setting: /* PCI LAWBARs setting in cpu/83xx/pci.c : start*/ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; /* base: 0x80000000 */ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; /* base: 0xe2000000 */ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; /* PCI LAWBARs setting in cpu/83xx/pci.c :end*/ PCI Outbound translation register setting: /* PCI1 mem space */ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; /* base: 0x80000000 */ pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; /* base: 0x80000000 */ pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); /* PCI1 IO space */ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); hose->first_busno = 0; hose->last_busno = 0xff; /* PCI memory space */ pci_set_region(hose->regions + 0, CFG_PCI1_MEM_BASE, /* base: 0x80000000 */ CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, /* Size is 512 MB */ PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 1, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 2, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); hose->region_count = 3; pci_setup_indirect(hose, (CFG_IMMRBAR+0x8300), (CFG_IMMRBAR+0x8304)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); Thanks & Regards, Vivek Trivedi

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