March 2008 - U-Boot

[U-Boot-Users] [PATCH 1/3] 8xx : Add of support to Adder875 board port - resubmit
by Bryan O'Donoghue 25 Mar '08

25 Mar '08

Greetings. Adds OF support to the Adder875 board port. Re: some stuff pointed out by Scott Wood, have removed some superfluous stuff from Adder.h as against last submission Signed-off-by: Bryan O'Donoghue <bodonoghue(a)codehermit.ie> --- diff --git a/board/adder/adder.c b/board/adder/adder.c index aa78158..5a2f752 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -26,6 +26,9 @@ #include <common.h> #include <mpc8xx.h> +#if defined(CONFIG_OF_LIBFDT) + #include <libfdt.h> +#endif /* * SDRAM is single Samsung K4S643232F-T70 chip (8MB) @@ -111,3 +114,12 @@ int checkboard( void ) return 0; } + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +} +#endif + diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 4304ecc..7919991 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -37,6 +37,8 @@ #define CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY @@ -212,4 +214,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */

2 1

[U-Boot-Users] [PATCH v2] Add setexpr command
by Kumar Gala 25 Mar '08

25 Mar '08

Add a simple expr style command that will set an env variable as the result of the command. This allows us to do simple math in shell. The following operations are supported: &, |, ^, +, -, *, /. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- docs will be added online since that appears to be where all detailed command docs are located right now. common/Makefile | 1 + common/cmd_setexpr.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ include/config_cmd_all.h | 1 + 3 files changed, 72 insertions(+), 0 deletions(-) create mode 100644 common/cmd_setexpr.c diff --git a/common/Makefile b/common/Makefile index 00934ca..6d9e38e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -88,6 +88,7 @@ COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o COBJS-y += cmd_sata.o COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o +COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c new file mode 100644 index 0000000..2e49b6d --- /dev/null +++ b/common/cmd_setexpr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file provides a shell like 'expr' function to return. + */ + +#include <common.h> +#include <config.h> +#include <command.h> + +int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong a, b; + char buf[16]; + + /* Validate arguments */ + if ((argc != 5) || (strlen(argv[3]) != 1)) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + a = simple_strtoul(argv[2], NULL, 16); + b = simple_strtoul(argv[4], NULL, 16); + + switch (argv[3][0]) { + case '|': sprintf(buf, "%lx", (a | b)); break; + case '&': sprintf(buf, "%lx", (a & b)); break; + case '+': sprintf(buf, "%lx", (a + b)); break; + case '^': sprintf(buf, "%lx", (a ^ b)); break; + case '-': sprintf(buf, "%lx", (a - b)); break; + case '*': sprintf(buf, "%lx", (a * b)); break; + case '/': sprintf(buf, "%lx", (a / b)); break; + case '%': sprintf(buf, "%lx", (a % b)); break; + default: + printf("invalid op\n"); + return 1; + } + + setenv(argv[1], buf); + + return 0; +} + +U_BOOT_CMD( + setexpr, 5, 0, do_setexpr, + "setexpr - set environment variable as the result of eval expression\n", + "name value1 <op> value2\n" + " - set environment variable 'name' to the result of the evaluated\n" + " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n" +); diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index f3965ef..69276a3 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_CMD_SNTP /* SNTP support */ #define CONFIG_CMD_SPI /* SPI utility */ -- 1.5.3.8

2 1

[U-Boot-Users] [PATCH] Add setexpr command
by Kumar Gala 25 Mar '08

25 Mar '08

Add a simple expr style command that will set an env variable as the result of the command. This allows us to do simple math in shell. The following operations are supported: &, |, ^, +, -, *, /. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- this was the expr patch, but renamed based on comments on the list. Still open issue about should this be in config_cmd_default.h - k common/cmd_setexpr.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) create mode 100644 common/cmd_setexpr.c diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c new file mode 100644 index 0000000..2e49b6d --- /dev/null +++ b/common/cmd_setexpr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file provides a shell like 'expr' function to return. + */ + +#include <common.h> +#include <config.h> +#include <command.h> + +int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong a, b; + char buf[16]; + + /* Validate arguments */ + if ((argc != 5) || (strlen(argv[3]) != 1)) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + a = simple_strtoul(argv[2], NULL, 16); + b = simple_strtoul(argv[4], NULL, 16); + + switch (argv[3][0]) { + case '|': sprintf(buf, "%lx", (a | b)); break; + case '&': sprintf(buf, "%lx", (a & b)); break; + case '+': sprintf(buf, "%lx", (a + b)); break; + case '^': sprintf(buf, "%lx", (a ^ b)); break; + case '-': sprintf(buf, "%lx", (a - b)); break; + case '*': sprintf(buf, "%lx", (a * b)); break; + case '/': sprintf(buf, "%lx", (a / b)); break; + case '%': sprintf(buf, "%lx", (a % b)); break; + default: + printf("invalid op\n"); + return 1; + } + + setenv(argv[1], buf); + + return 0; +} + +U_BOOT_CMD( + setexpr, 5, 0, do_setexpr, + "setexpr - set environment variable as the result of eval expression\n", + "name value1 <op> value2\n" + " - set environment variable 'name' to the result of the evaluated\n" + " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n" +); -- 1.5.3.8

4 10

[U-Boot-Users] Delete all env vars except read onlys
by Matthias Fuchs 25 Mar '08

25 Mar '08

Hi, I am wondering if there is a way to delete all environment variables but not the readonly ones. The common way to delete all variables is to make the environment CRC invalid an do a reset. After reset a saveenv saves a default environment. What I want to do is to delete all variables (preferable from an autoscr script) but not the vendor variables like serial# and eth?addr. Wildcards in the setenv parameters would solve this issue, but chars like '*' or '?' are valid chars for environment variables. Any idea? Matthias

9 35

[U-Boot-Users] [PATCH 1/3] 8xx: Add FDT support to 8xx
by Bryan O'Donoghue 25 Mar '08

25 Mar '08

Minimal - just a bare bones copy of code already done by others. Adds the get_brgclk - for the purposes of enumerating a brg clock-frequency entry in a of tree. Adds fdt.c so that 8xx will have a ft_cpu_setup function. Signed-off-by: Bryan O'Donoghue <bodonoghue(a)codehermit.ie> --- diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile index 223b30c..dbdc2e0 100644 --- a/cpu/mpc8xx/Makefile +++ b/cpu/mpc8xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o kgdb.o COBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ - fec.o i2c.o interrupts.o lcd.o scc.o \ + fec.o fdt.o i2c.o interrupts.o lcd.o scc.o \ serial.o speed.o spi.o \ traps.o upatch.o video.o SOBJS = plprcr_write.o diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 11b0893..070babc 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -174,6 +174,27 @@ unsigned long measure_gclk(void) #endif +void get_brgclk(uint sccr) +{ + uint divider = 0; + + switch((sccr&SCCR_DFBRG11)>>11){ + case 0: + divider = 1; + break; + case 1: + divider = 4; + break; + case 2: + divider = 16; + break; + case 3: + divider = 64; + break; + } + gd->brg_clk = gd->cpu_clk/divider; +} + #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) /* @@ -223,6 +244,8 @@ int get_clocks (void) gd->bus_clk = gd->cpu_clk / 2; } + get_brgclk(sccr); + return (0); } @@ -254,6 +277,8 @@ int get_clocks_866 (void) gd->cpu_clk = measure_gclk (); #endif + get_brgclk(immr->im_clkrst.car_sccr); + /* if cpu clock <= 66 MHz then set bus division factor to 1, * otherwise set it to 2 */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 05aee74..9e8018a 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -42,6 +42,9 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; +#if defined(CONFIG_8xx) + unsigned long brg_clk; +#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; diff --git a/cpu/mpc8xx/fdt.c b/cpu/mpc8xx/fdt.c new file mode 100644 index 0000000..1e3dc7a --- /dev/null +++ b/cpu/mpc8xx/fdt.c @@ -0,0 +1,46 @@ +/* + * Copyright 2008 (C) Bryan O'Donoghue + * + * Code copied & edited from Freescale mpc85xx stuff. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 8, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", + gd->brg_clk, 1); + + /* Fixup ethernet MAC addresses */ + fdt_fixup_ethernet(blob, bd); + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +}

3 2

[U-Boot-Users] [PATCH] ColdFire: Add dspi and serial flash support for MCF5445x
by Tsi-Chung Liew 25 Mar '08

25 Mar '08

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- board/freescale/m54455evb/flash.c | 449 +++++++++++++++++++++++++++++++------ cpu/mcf5445x/Makefile | 2 +- cpu/mcf5445x/dspi.c | 73 ++++++ include/asm-m68k/coldfire/dspi.h | 10 + include/configs/M54455EVB.h | 28 +++- 5 files changed, 492 insertions(+), 70 deletions(-) create mode 100644 cpu/mcf5445x/dspi.c diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c index de2cca8..6b50e8d 100644 --- a/board/freescale/m54455evb/flash.c +++ b/board/freescale/m54455evb/flash.c @@ -95,6 +95,11 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV; #define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */ #define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */ +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) +#define STM_ID_M25P16 0x20152015 +#define FLASH_M25P16 0x0055 +#endif + #define SYNC __asm__("nop") /*----------------------------------------------------------------------- @@ -111,6 +116,12 @@ void inline spin_wheel(void); void flash_sync_real_protect(flash_info_t * info); uchar intel_sector_protected(flash_info_t * info, ushort sector); +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) +int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt); +int serial_flash_read_status(int chipsel); +static int ser_flash_cs = 0; +#endif + flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ulong flash_init(void) @@ -119,6 +130,10 @@ ulong flash_init(void) ulong size = 0; ulong fbase = 0; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + dspi_init(); +#endif + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { memset(&flash_info[i], 0, sizeof(flash_info_t)); @@ -129,6 +144,11 @@ ulong flash_init(void) case 1: fbase = (ulong) CFG_FLASH1_BASE; break; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + case 2: + fbase = (ulong) CFG_FLASH2_BASE; + break; +#endif } flash_get_size((FPWV *) fbase, &flash_info[i]); @@ -152,7 +172,6 @@ int flash_get_offsets(ulong base, flash_info_t * info) { int i, j, k; int sectors, bs, banks; - ulong start; if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) { int sect[] = CFG_ATMEL_SECT; @@ -196,6 +215,15 @@ int flash_get_offsets(ulong base, flash_info_t * info) *addr16 = (FPW) INTEL_RESET; /* restore read mode */ } +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) { + info->start[0] = CFG_FLASH2_BASE; + for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) { + info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ; + info->protect[k] = 0; + } + } +#endif return ERR_OK; } @@ -211,6 +239,11 @@ void flash_print_info(flash_info_t * info) case FLASH_MAN_ATM: printf("ATMEL "); break; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + case FLASH_MAN_STM: + printf("ST "); + break; +#endif default: printf("Unknown Vendor "); break; @@ -221,8 +254,13 @@ void flash_print_info(flash_info_t * info) printf("AT49BV040A\n"); break; case FLASH_28F128J3A: - printf("Intel 28F128J3A\n"); + printf("28F128J3A\n"); + break; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + case FLASH_M25P16: + printf("M25P16\n"); break; +#endif default: printf("Unknown Chip Type\n"); return; @@ -267,6 +305,45 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info) u16 value; int i; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + if ((ulong) addr == CFG_FLASH2_BASE) { + int manufactId = 0; + int deviceId = 0; + + ser_flash_cs = 1; + + dspi_tx(ser_flash_cs, 0x80, SER_RDID); + dspi_tx(ser_flash_cs, 0x80, 0); + dspi_tx(ser_flash_cs, 0x80, 0); + dspi_tx(ser_flash_cs, 0x80, 0); + + dspi_rx(); + manufactId = dspi_rx(); + deviceId = dspi_rx() << 8; + deviceId |= dspi_rx(); + + dspi_tx(ser_flash_cs, 0x00, 0); + dspi_rx(); + + switch (manufactId) { + case (u8) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + } + + switch (deviceId) { + case (u16) STM_ID_M25P16: + info->flash_id += FLASH_M25P16; + break; + } + + info->sector_count = CFG_STM_SECT; + info->size = CFG_STM_SECT * CFG_STM_SECTSZ; + + return (info->size); + } +#endif + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ @@ -383,6 +460,21 @@ int flash_cmd_rd(volatile u16 * addr, int index) return (int)addr[index]; } +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) +int serial_flash_read_status(int chipsel) +{ + u16 status; + + dspi_tx(chipsel, 0x80, SER_RDSR); + dspi_rx(); + + dspi_tx(chipsel, 0x00, 0); + status = dspi_rx(); + + return status; +} +#endif + /* * This function gets the u-boot flash sector protection status * (flash_info_t.protect[]) in sync with the sector protection @@ -462,8 +554,11 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; ulong type, start, last; - int rcode = 0, intel = 0; - + int rcode = 0, flashtype = 0; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + int count; + u16 status; +#endif if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) printf("- missing\n"); @@ -474,19 +569,25 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) type = (info->flash_id & FLASH_VENDMASK); - if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) { - type = (info->flash_id & FLASH_VENDMASK); - printf - ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } + switch (type) { + case FLASH_MAN_ATM: + flashtype = 1; + break; + case FLASH_MAN_INTEL: + flashtype = 2; + break; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + case FLASH_MAN_STM: + flashtype = 3; + break; +#endif + default: + type = (info->flash_id & FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; } - if (type == FLASH_MAN_INTEL) - intel = 1; - prot = 0; for (sect = s_first; sect <= s_last; ++sect) { if (info->protect[sect]) { @@ -503,6 +604,51 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) start = get_timer(0); last = start; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + /* Perform bulk erase */ + if (flashtype == 3) { + if ((s_last - s_first) == (CFG_STM_SECT - 1)) { + if (prot == 0) { + dspi_tx(ser_flash_cs, 0x00, SER_WREN); + dspi_rx(); + + status = serial_flash_read_status(ser_flash_cs); + if (((status & 0x9C) != 0) + && ((status & 0x02) != 0x02)) { + printf("Can't erase flash\n"); + return 1; + } + + dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE); + dspi_rx(); + + count = 0; + start = get_timer(0); + do { + status = + serial_flash_read_status + (ser_flash_cs); + + if (count++ > 0x10000) { + spin_wheel(); + count = 0; + } + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + } while (status & 0x01); + + printf("\b. done\n"); + return 0; + } else if (prot == CFG_STM_SECT) { + return 1; + } + } + } +#endif /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ @@ -515,65 +661,116 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* arm simple, non interrupt dependent timer */ start = get_timer(0); - if (intel) { - *addr = (FPW) INTEL_READID; - min = addr[INTEL_CFI_TERB] & 0xff; - min = 1 << min; /* ms */ - min = (min / info->sector_count) * 1000; - - /* start erase block */ - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - while ((*addr & (FPW) INTEL_FINISHED) != - (FPW) INTEL_FINISHED) { - - if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ - *addr = (FPW) INTEL_RESET; /* reset to read mode */ - - rcode = 1; - break; + switch (flashtype) { + case 1: + { + FPWV *base; /* first address in bank */ + FPWV *atmeladdr; + + flag = disable_interrupts(); + + atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ + base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + *atmeladdr = (u8) 0x00300030; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*atmeladdr & (u8) 0x00800080) != + (u8) 0x00800080) { + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } } - } - - *addr = (FPW) INTEL_RESET; /* resest to read mode */ - } else { - FPWV *base; /* first address in bank */ - FPWV *atmeladdr; - - flag = disable_interrupts(); - atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ - base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ - - base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ - *atmeladdr = (u8) 0x00300030; /* erase sector */ + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + break; + } - if (flag) - enable_interrupts(); + case 2: + { + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB] & 0xff; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } - while ((*atmeladdr & (u8) 0x00800080) != - (u8) 0x00800080) { - if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + break; + } - rcode = 1; - break; +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + case 3: + { + u8 sec = ((ulong) addr >> 16) & 0xFF; + + dspi_tx(ser_flash_cs, 0x00, SER_WREN); + dspi_rx(); + status = + serial_flash_read_status + (ser_flash_cs); + if (((status & 0x9C) != 0) + && ((status & 0x02) != 0x02)) { + printf("Error Programming\n"); + return 1; } - } - *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ - } /* Atmel or Intel */ + dspi_tx(ser_flash_cs, 0x80, + SER_SECT_ERASE); + dspi_tx(ser_flash_cs, 0x80, sec); + dspi_tx(ser_flash_cs, 0x80, 0); + dspi_tx(ser_flash_cs, 0x00, 0); + + dspi_rx(); + dspi_rx(); + dspi_rx(); + dspi_rx(); + + do { + status = + serial_flash_read_status + (ser_flash_cs); + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + } while (status & 0x01); + + break; + } +#endif + } /* switch (flashtype) */ } } printf(" done\n"); @@ -583,6 +780,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { + int count; + if (info->flash_id == FLASH_UNKNOWN) return 4; @@ -623,7 +822,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { ulong cp, wp; u16 data; - int count, i, l, rc, port_width; + int i, l, rc, port_width; /* get lower word aligned address */ wp = addr; @@ -724,6 +923,51 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) } /* case FLASH_MAN_INTEL */ +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) + case FLASH_MAN_STM: + { + ulong wp; + u8 *data = (u8 *) src; + int left; /* number of bytes left to program */ + + wp = addr; + + /* page align, each page is 256 bytes */ + if ((wp % 0x100) != 0) { + left = (0x100 - (wp & 0xFF)); + write_ser_data(info, wp, data, left); + cnt -= left; + wp += left; + data += left; + } + + /* page program - 256 bytes at a time */ + if (cnt > 255) { + count = 0; + while (cnt >= 0x100) { + write_ser_data(info, wp, data, 0x100); + cnt -= 0x100; + wp += 0x100; + data += 0x100; + + if (count++ > 0x400) { + spin_wheel(); + count = 0; + } + } + } + + /* remainint bytes */ + if (cnt && (cnt < 256)) { + write_ser_data(info, wp, data, cnt); + wp += cnt; + data += cnt; + cnt -= cnt; + } + + printf("\b."); + } +#endif } /* switch */ return ERR_OK; @@ -844,6 +1088,75 @@ int write_data(flash_info_t * info, ulong dest, FPW data) return (0); } +#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) +int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt) +{ + ulong start; + int status, i; + u8 flashdata; + + /* Check if Flash is (sufficiently) erased */ + dspi_tx(ser_flash_cs, 0x80, SER_READ); + dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF); + dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF); + dspi_tx(ser_flash_cs, 0x80, dest & 0xFF); + dspi_rx(); + dspi_rx(); + dspi_rx(); + dspi_rx(); + dspi_tx(ser_flash_cs, 0x80, 0); + flashdata = dspi_rx(); + dspi_tx(ser_flash_cs, 0x00, 0); + dspi_rx(); + + if ((flashdata & *data) != *data) { + printf("not erased at %08lx (%lx)\n", (ulong) dest, + (ulong) flashdata); + return (2); + } + + dspi_tx(ser_flash_cs, 0x00, SER_WREN); + dspi_rx(); + + status = serial_flash_read_status(ser_flash_cs); + if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) { + printf("Error Programming\n"); + return 1; + } + + start = get_timer(0); + + dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG); + dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16)); + dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8)); + dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF)); + dspi_rx(); + dspi_rx(); + dspi_rx(); + dspi_rx(); + + for (i = 0; i < (cnt - 1); i++) { + dspi_tx(ser_flash_cs, 0x80, *data); + dspi_rx(); + data++; + } + + dspi_tx(ser_flash_cs, 0x00, *data); + dspi_rx(); + + do { + status = serial_flash_read_status(ser_flash_cs); + + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + } while (status & 0x01); + + return (0); +} +#endif + /*----------------------------------------------------------------------- * Write a word to Flash for ATMEL FLASH * A word is 16 bits, whichever the bus width of the flash bank diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile index 26ec298..a549fdd 100644 --- a/cpu/mcf5445x/Makefile +++ b/cpu/mcf5445x/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c new file mode 100644 index 0000000..44d8505 --- /dev/null +++ b/cpu/mcf5445x/dspi.c @@ -0,0 +1,73 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> + +#if defined(CONFIG_CF_DSPI) +#include <asm/immap.h> +void dspi_init(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 | + GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 | + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; + + dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 | + DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 | + DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | + DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; + + dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA | + DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) | + DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) | + DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) | + DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1); +} + +void dspi_tx(int chipsel, u8 attrib, u16 data) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->dsr & 0x0000F000) >= 4) ; + + dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data; +} + +u16 dspi_rx(void) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->dsr & 0x000000F0) == 0) ; + + return (dspi->drfr & 0xFFFF); +} + +#endif /* CONFIG_HARD_SPI */ diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h index 3c579d3..8327e1b 100644 --- a/include/asm-m68k/coldfire/dspi.h +++ b/include/asm-m68k/coldfire/dspi.h @@ -64,10 +64,15 @@ typedef struct dspi { #define DSPI_DMCR_CTXF (0x00000800) #define DSPI_DMCR_DRXF (0x00001000) #define DSPI_DMCR_DTXF (0x00002000) +#define DSPI_DMCR_MDIS (0x00004000) #define DSPI_DMCR_CSIS0 (0x00010000) +#define DSPI_DMCR_CSIS1 (0x00020000) #define DSPI_DMCR_CSIS2 (0x00040000) #define DSPI_DMCR_CSIS3 (0x00080000) +#define DSPI_DMCR_CSIS4 (0x00100000) #define DSPI_DMCR_CSIS5 (0x00200000) +#define DSPI_DMCR_CSIS6 (0x00400000) +#define DSPI_DMCR_CSIS7 (0x00800000) #define DSPI_DMCR_ROOE (0x01000000) #define DSPI_DMCR_PCSSE (0x02000000) #define DSPI_DMCR_MTFE (0x04000000) @@ -92,6 +97,7 @@ typedef struct dspi { #define DSPI_DCTAR_CPHA (0x02000000) #define DSPI_DCTAR_CPOL (0x04000000) #define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) +#define DSPI_DCTAR_DBR (0x80000000) #define DSPI_DCTAR_PCSSCK_1CLK (0x00000000) #define DSPI_DCTAR_PCSSCK_3CLK (0x00400000) #define DSPI_DCTAR_PCSSCK_5CLK (0x00800000) @@ -153,4 +159,8 @@ typedef struct dspi { /* Bit definitions and macros for DRFDR group */ #define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) +void dspi_init(void); +void dspi_tx(int chipsel, u8 attrib, u16 data); +u16 dspi_rx(void); + #endif /* __DSPI_H__ */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index f5edddf..a3c71e3 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -171,6 +171,10 @@ #define CFG_I2C_OFFSET 0x58000 #define CFG_IMMR CFG_MBAR +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH + /* PCI */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCI 1 @@ -309,7 +313,7 @@ #else -# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ # define CFG_ATMEL_REGION 4 # define CFG_ATMEL_TOTALSECT 11 @@ -326,6 +330,28 @@ # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ # define CFG_FLASH_CHECKSUM +#ifdef CONFIG_SERIAL_FLASH +# define CFG_FLASH2_BASE 0x01000000 +# define CFG_STM_SECT 32 +# define CFG_STM_SECTSZ 0x10000 + +# undef CFG_FLASH_ERASE_TOUT +# define CFG_FLASH_ERASE_TOUT 20000 + +# define SER_WREN 0x06 +# define SER_WRDI 0x04 +# define SER_RDID 0x9F +# define SER_RDSR 0x05 +# define SER_WRSR 0x01 +# define SER_READ 0x03 +# define SER_F_READ 0x0B +# define SER_PAGE_PROG 0x02 +# define SER_SECT_ERASE 0xD8 +# define SER_BULK_ERASE 0xC7 +# define SER_DEEP_PWRDN 0xB9 +# define SER_RES 0xAB +#endif + #endif /* -- 1.5.4.1

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[U-Boot-Users] Large initramfs
by Templeton, Bill 25 Mar '08

25 Mar '08

Hello, I'm having trouble getting U-boot (based on 1.3.0) to boot a MV Pro 5.0 (based on 2.6.18) kernel image with a large built-in initramfs on the PPC440 Taishan eval board. The boot process hangs after the output of "Finalizing device tree..." I'm attempting to boot the cuImage target. I've made modifications to U-boot for preparations for our own PPC440 design. One of the changes was to the file ../lib_ppc/board.c to remove the logic that forces the command line and bd_info structure into the first 8 MB of memory. However, that didn't help. I can boot the kernel image if it's built without the initramfs. That is, I can get past this hang scenario. Obviously things aren't all that great without out an initramfs or initrd but it seems to prove that the built kernel and my U-boot modifications fundamentally works and leads me to believe the problem is related to the initramfs or its size. Does anybody have any experience using a kernel+initramfs that is larger than 8MB? Larger than 16MB? Any help/comments would be greatly appreciated. Bill T. Boot progress 80 (0x50) Using ppc_4xx_eth0 device TFTP from server 10.10.5.112; our IP address is 10.10.5.207 Filename 'cuImage.taishan3'. Load address: 0x8000000 Loading: ##############################################################. .... done Bytes transferred = 25962438 (18c27c6 hex) Boot progress 81 (0x51) Boot progress 84 (0x54) Boot progress 1 (0x1) ## Booting image at 08000000 ... Boot progress 2 (0x2) Boot progress 3 (0x3) Image Name: Linux-2.6.18_pro500-440gx_taisha Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 25962374 Bytes = 24.8 MB Load Address: 01c00000 Entry Point: 01c0040c Verifying Checksum ... OK Boot progress 4 (0x4) Boot progress 5 (0x5) Boot progress 6 (0x6) Uncompressing Kernel Image ... OK Boot progress 7 (0x7) Boot progress 8 (0x8) ## Current stack ends at 0x0FEBE180 => set upper limit to 0x0FEBD980 ## cmdline at 0x0FEBD880 ... 0x0FEBD8DE Boot progress 14 (0xe) No initrd ## Transferring control to Linux (at address 01c0040c) ... Boot progress 15 (0xf) Calling kernel(0x1c0040c): (0febd7d0, 00000000, 00000000, 0febd880, 0febd8de) CPU clock-frequency <- 0x2f34f600 (792MHz) CPU timebase-frequency <- 0x2f34f600 (792MHz) /plb: clock-frequency <- bcd3d80 (198MHz) /plb/opb: clock-frequency <- 3ef1480 (66MHz) /plb/opb/ebc: clock-frequency <- 3ef1480 (66MHz) /plb/opb/serial@40000200: clock-frequency <- a8c000 (11MHz) /plb/opb/serial@40000300: clock-frequency <- a8c000 (11MHz) Memory <- <0x0 0x0 0x10000000> (256MB) ENET0: local-mac-address <- 02:0c:4f:35:00:16 ENET1: local-mac-address <- 31:2e:32:00:55:2d zImage starting: loaded at 0x01c00000 (sp: 0x03732ed0) Allocating 0x1b27ea4 bytes for kernel ... gunzipping (0x00000000 <- 0x01c0e000:0x03731378)...done 0x1afa0c0 bytes Linux/PowerPC load: ip=10.10.5.207:10.10.5.112:10.10.5.1:255.255.255.0:eval1:eth0:off panic=1 console=ttyS1,115200 Finalizing device tree... flat tree at 0x373f3a0

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[U-Boot-Users] PCI broken on MPC8323ERDB
by Michael Barkowski 25 Mar '08

25 Mar '08

This commit in U-Boot tree breaks the PCI in Linux MPC8323ERDB. Do I need to define CONFIG_PCI_SKIP_HOST_BRIDGE now? I don't see any other boards defining it. commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 Author: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Date: Fri Mar 7 16:04:25 2008 +0900 pci: Add CONFIG_PCI_SKIP_HOST_BRIDGE config option In current source code, when the device number of PCI is 0, process PCI bridge without fail. However, when the device number is 0, it is not PCI always bridge. There are times when device of PCI allocates. When CONFIG_PCI_SKIP_HOST_BRIDGE is enable, this problem is solved when use this patch. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> On Linus' master, default config, this U-boot change has this effect on Linux boot: usbmon: debugfs is not available ehci_hcd 0000:00:10.1: EHCI Host Controller ehci_hcd 0000:00:10.1: new USB bus registered, assigned bus number 1 -ehci_hcd 0000:00:10.1: irq 17, io mem 0x90001000 +ehci_hcd 0000:00:10.1: irq 17, io mem 0x90201000 ehci_hcd 0000:00:10.1: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 3 ports detected ohci_hcd 0000:00:10.0: OHCI Host Controller ohci_hcd 0000:00:10.0: new USB bus registered, assigned bus number 2 -ohci_hcd 0000:00:10.0: irq 17, io mem 0x90000000 +ohci_hcd 0000:00:10.0: irq 17, io mem 0x90200000 +ohci_hcd 0000:00:10.0: OHCI Unrecoverable Error, scheduling NEC chip restart usb usb2: configuration #1 chosen from 1 choice -hub 2-0:1.0: USB hub found -hub 2-0:1.0: 3 ports detected -Initializing USB Mass Storage driver... -usbcore: registered new interface driver usb-storage -USB Mass Storage support registered. +usb usb2: can't set config #1, error -108 +ohci_hcd 0000:00:10.0: HC died; cleaning up +Unable to handle kernel paging request for data at address 0x00000050 +Faulting instruction address: 0xc01a53c0 +Oops: Kernel access of bad area, sig: 11 [#1] +MPC832x RDB +Modules linked in: +NIP: c01a53c0 LR: c01a7ce4 CTR: c0166fec +REGS: c3821d10 TRAP: 0300 Not tainted (2.6.25-rc6-00333-ga4083c9) +MSR: 00001032 <ME,IR,DR> CR: 22044048 XER: 00000000 +DAR: 00000050, DSISR: 20000000 +TASK = c381d000[1] 'swapper' THREAD: c3820000 +GPR00: c01a7cdc c3821dc0 c381d000 c38a9000 00000000 ffffffff c016a158 00004000 +GPR08: 00000001 00000000 000012b1 c5002500 22044042 100aeba0 c02c8b10 c02d8dd8 +GPR16: c02c8b8c c02c8b74 c0334ab4 c02c8bb4 c02c8ba0 c0330000 00000000 03ff8354 +GPR24: 000000a0 00000011 c034ca90 c3812858 c38a9000 c38a9000 c391fc00 00009032 +NIP [c01a53c0] usb_kick_khubd+0x4/0x10 +LR [c01a7ce4] usb_hc_died+0x6c/0x84 +Call Trace: +[c3821dc0] [c01a7cdc] usb_hc_died+0x64/0x84 (unreliable) +[c3821dd0] [c01a8a00] usb_add_hcd+0x5a8/0x600 +[c3821e00] [c01b3bf8] usb_hcd_pci_probe+0x19c/0x2b0 +[c3821e30] [c01538a4] pci_device_probe+0x84/0xbc +[c3821e50] [c016f07c] driver_probe_device+0xb8/0x1e8 +[c3821e70] [c016f3a4] __driver_attach+0xcc/0xf8 +[c3821e90] [c016e0f8] bus_for_each_dev+0x5c/0x98 +[c3821ec0] [c016ee84] driver_attach+0x24/0x34 +[c3821ed0] [c016ecdc] bus_add_driver+0x1d8/0x258 +[c3821f00] [c016f650] driver_register+0x48/0x114 +[c3821f20] [c0153b14] __pci_register_driver+0x4c/0xac +[c3821f40] [c0329e90] ohci_hcd_mod_init+0x88/0x9c +[c3821f60] [c03121b8] kernel_init+0xb4/0x294 +[c3821ff0] [c000fb64] kernel_thread+0x44/0x60 +Instruction dump: +7c0903a6 4e800421 2f9e0000 3bdeffff 409effd0 4bffff2c 80010024 bb810010 +38210020 7c0803a6 4bfffab8 81230190 <81690050> 806b00dc 4bfff9fc 9421fff0 +---[ end trace c793972ed4e617c5 ]--- +Kernel panic - not syncing: Attempted to kill init! +Rebooting in 180 seconds..

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[U-Boot-Users] [PATCH 2/2] Freescale eLBC FCM NAND driver
by Scott Wood 25 Mar '08

25 Mar '08

This is a driver for the Flash Control Machine of the enhanched Local Bus Controller found on some Freescale chips (such as the mpc8313 and the mpc8379). Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- This patch applies to the mtd-2.6.22.1 branch of the nand tree. drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsl_elbc_nand.c | 764 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 765 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsl_elbc_nand.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 244fa09..470f63f 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -32,6 +32,7 @@ COBJS-y += nand_ecc.o COBJS-y += nand_bbt.o COBJS-y += nand_util.o +COBJS-y += fsl_elbc_nand.o COBJS-y += fsl_upm.o COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c new file mode 100644 index 0000000..ceb3529 --- /dev/null +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -0,0 +1,764 @@ +/* Freescale Enhanced Local Bus Controller FCM NAND driver + * + * Copyright (c) 2006-2008 Freescale Semiconductor + * + * Authors: Nick Spence <nick.spence(a)freescale.com>, + * Scott Wood <scottwood(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_ELBC) + +#include <malloc.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +#include <asm/io.h> +#include <asm/errno.h> + +#ifdef VERBOSE_DEBUG +#define DEBUG_ELBC +#define vdbg(format, arg...) printf("DEBUG: " format, ##arg) +#else +#define vdbg(format, arg...) do {} while (0) +#endif + +/* Can't use plain old DEBUG because the linux mtd + * headers define it as a macro. + */ +#ifdef DEBUG_ELBC +#define dbg(format, arg...) printf("DEBUG: " format, ##arg) +#else +#define dbg(format, arg...) do {} while (0) +#endif + +#define MAX_BANKS 8 +#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ +#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */ + +#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) + +struct fsl_elbc_ctrl; + +/* mtd information per set */ + +struct fsl_elbc_mtd { + struct mtd_info mtd; + struct nand_chip chip; + struct fsl_elbc_ctrl *ctrl; + + struct device *dev; + int bank; /* Chip select bank number */ + u8 __iomem *vbase; /* Chip select base virtual address */ + int page_size; /* NAND page size (0=512, 1=2048) */ + unsigned int fmr; /* FCM Flash Mode Register value */ +}; + +/* overview of the fsl elbc controller */ + +struct fsl_elbc_ctrl { + struct nand_hw_control controller; + struct fsl_elbc_mtd *chips[MAX_BANKS]; + + /* device info */ + lbus83xx_t *regs; + u8 __iomem *addr; /* Address of assigned FCM buffer */ + unsigned int page; /* Last page written to / read from */ + unsigned int read_bytes; /* Number of bytes read during command */ + unsigned int column; /* Saved column from SEQIN */ + unsigned int index; /* Pointer to next byte to 'read' */ + unsigned int status; /* status read from LTESR after last op */ + unsigned int mdr; /* UPM/FCM Data Register value */ + unsigned int use_mdr; /* Non zero if the MDR is to be set */ + unsigned int oob; /* Non zero if operating on OOB data */ + uint8_t *oob_poi; /* Place to write ECC after read back */ +}; + +/* These map to the positions used by the FCM hardware ECC generator */ + +/* Small Page FLASH with FMR[ECCM] = 0 */ +static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { + .eccbytes = 3, + .eccpos = {6, 7, 8}, + .oobfree = { {0, 5}, {9, 7} }, + .oobavail = 12, +}; + +/* Small Page FLASH with FMR[ECCM] = 1 */ +static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { + .eccbytes = 3, + .eccpos = {8, 9, 10}, + .oobfree = { {0, 5}, {6, 2}, {11, 5} }, + .oobavail = 12, +}; + +/* Large Page FLASH with FMR[ECCM] = 0 */ +static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { + .eccbytes = 12, + .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, + .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, + .oobavail = 48, +}; + +/* Large Page FLASH with FMR[ECCM] = 1 */ +static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, + .oobavail = 48, +}; + +/*=================================*/ + +/* + * Set up the FCM hardware block and page address fields, and the fcm + * structure addr field to point to the correct FCM buffer in memory + */ +static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + int buf_num; + + ctrl->page = page_addr; + + out_be32(&lbc->fbar, + page_addr >> (chip->phys_erase_shift - chip->page_shift)); + + if (priv->page_size) { + out_be32(&lbc->fpar, + ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | + (oob ? FPAR_LP_MS : 0) | column); + buf_num = (page_addr & 1) << 2; + } else { + out_be32(&lbc->fpar, + ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | + (oob ? FPAR_SP_MS : 0) | column); + buf_num = page_addr & 7; + } + + ctrl->addr = priv->vbase + buf_num * 1024; + ctrl->index = column; + + /* for OOB data point to the second half of the buffer */ + if (oob) + ctrl->index += priv->page_size ? 2048 : 512; + + vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), " + "index %x, pes %d ps %d\n", + buf_num, ctrl->addr, priv->vbase, ctrl->index, + chip->phys_erase_shift, chip->page_shift); +} + +/* + * execute FCM command and wait for it to complete + */ +static int fsl_elbc_run_command(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + long long end_tick; + u32 ltesr; + + /* Setup the FMR[OP] to execute without write protection */ + out_be32(&lbc->fmr, priv->fmr | 3); + if (ctrl->use_mdr) + out_be32(&lbc->mdr, ctrl->mdr); + + vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", + in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); + vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x " + "fbcr=%08x bank=%d\n", + in_be32(&lbc->fbar), in_be32(&lbc->fpar), + in_be32(&lbc->fbcr), priv->bank); + + /* execute special operation */ + out_be32(&lbc->lsor, priv->bank); + + /* wait for FCM complete flag or timeout */ + end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks(); + + ltesr = 0; + while (end_tick > get_ticks()) { + ltesr = in_be32(&lbc->ltesr); + if (ltesr & LTESR_CC) + break; + } + + ctrl->status = ltesr & LTESR_NAND_MASK; + out_be32(&lbc->ltesr, ctrl->status); + out_be32(&lbc->lteatr, 0); + + /* store mdr value in case it was needed */ + if (ctrl->use_mdr) + ctrl->mdr = in_be32(&lbc->mdr); + + ctrl->use_mdr = 0; + + vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", + ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); + + /* returns 0 on success otherwise non-zero) */ + return ctrl->status == LTESR_CC ? 0 : -EIO; +} + +static void fsl_elbc_do_read(struct nand_chip *chip, int oob) +{ + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + + if (priv->page_size) { + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT)); + + out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); + } else { + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT)); + + if (oob) + out_be32(&lbc->fcr, + NAND_CMD_READOOB << FCR_CMD0_SHIFT); + else + out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); + } +} + +/* cmdfunc send commands to the FCM */ +static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + + ctrl->use_mdr = 0; + + /* clear the read buffer */ + ctrl->read_bytes = 0; + if (command != NAND_CMD_PAGEPROG) + ctrl->index = 0; + + switch (command) { + /* READ0 and READ1 read the entire buffer to use hardware ECC. */ + case NAND_CMD_READ1: + column += 256; + + /* fall-through */ + case NAND_CMD_READ0: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + + out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ + set_addr(mtd, 0, page_addr, 0); + + ctrl->read_bytes = mtd->writesize + mtd->oobsize; + ctrl->index += column; + + fsl_elbc_do_read(chip, 0); + fsl_elbc_run_command(mtd); + return; + + /* READOOB reads only the OOB because no ECC is performed. */ + case NAND_CMD_READOOB: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + + out_be32(&lbc->fbcr, mtd->oobsize - column); + set_addr(mtd, column, page_addr, 1); + + ctrl->read_bytes = mtd->writesize + mtd->oobsize; + + fsl_elbc_do_read(chip, 1); + fsl_elbc_run_command(mtd); + + return; + + /* READID must read all 5 possible bytes while CEB is active */ + case NAND_CMD_READID: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); + + out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_UA << FIR_OP1_SHIFT) | + (FIR_OP_RBW << FIR_OP2_SHIFT)); + out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); + /* 5 bytes for manuf, device and exts */ + out_be32(&lbc->fbcr, 5); + ctrl->read_bytes = 5; + ctrl->use_mdr = 1; + ctrl->mdr = 0; + + set_addr(mtd, 0, 0, 0); + fsl_elbc_run_command(mtd); + return; + + /* ERASE1 stores the block and page address */ + case NAND_CMD_ERASE1: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " + "page_addr: 0x%x.\n", page_addr); + set_addr(mtd, 0, page_addr, 0); + return; + + /* ERASE2 uses the block and page address from ERASE1 */ + case NAND_CMD_ERASE2: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); + + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_PA << FIR_OP1_SHIFT) | + (FIR_OP_CM1 << FIR_OP2_SHIFT)); + + out_be32(&lbc->fcr, + (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); + + out_be32(&lbc->fbcr, 0); + ctrl->read_bytes = 0; + + fsl_elbc_run_command(mtd); + return; + + /* SEQIN sets up the addr buffer and all registers except the length */ + case NAND_CMD_SEQIN: { + u32 fcr; + vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " + "page_addr: 0x%x, column: 0x%x.\n", + page_addr, column); + + ctrl->column = column; + ctrl->oob = 0; + + if (priv->page_size) { + fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | + (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); + + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_WB << FIR_OP3_SHIFT) | + (FIR_OP_CW1 << FIR_OP4_SHIFT)); + } else { + fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) | + (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CM2 << FIR_OP1_SHIFT) | + (FIR_OP_CA << FIR_OP2_SHIFT) | + (FIR_OP_PA << FIR_OP3_SHIFT) | + (FIR_OP_WB << FIR_OP4_SHIFT) | + (FIR_OP_CW1 << FIR_OP5_SHIFT)); + + if (column >= mtd->writesize) { + /* OOB area --> READOOB */ + column -= mtd->writesize; + fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; + ctrl->oob = 1; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; + } else { + /* Second 256 bytes --> READ1 */ + fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; + } + } + + out_be32(&lbc->fcr, fcr); + set_addr(mtd, column, page_addr, ctrl->oob); + return; + } + + /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ + case NAND_CMD_PAGEPROG: { + int full_page; + vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " + "writing %d bytes.\n", ctrl->index); + + /* if the write did not start at 0 or is not a full page + * then set the exact length, otherwise use a full page + * write so the HW generates the ECC. + */ + if (ctrl->oob || ctrl->column != 0 || + ctrl->index != mtd->writesize + mtd->oobsize) { + out_be32(&lbc->fbcr, ctrl->index); + full_page = 0; + } else { + out_be32(&lbc->fbcr, 0); + full_page = 1; + } + + fsl_elbc_run_command(mtd); + + /* Read back the page in order to fill in the ECC for the + * caller. Is this really needed? + */ + if (full_page && ctrl->oob_poi) { + out_be32(&lbc->fbcr, 3); + set_addr(mtd, 6, page_addr, 1); + + ctrl->read_bytes = mtd->writesize + 9; + + fsl_elbc_do_read(chip, 1); + fsl_elbc_run_command(mtd); + + memcpy_fromio(ctrl->oob_poi + 6, + &ctrl->addr[ctrl->index], 3); + ctrl->index += 3; + } + + ctrl->oob_poi = NULL; + return; + } + + /* CMD_STATUS must read the status byte while CEB is active */ + /* Note - it does not wait for the ready line */ + case NAND_CMD_STATUS: + out_be32(&lbc->fir, + (FIR_OP_CM0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT)); + out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); + out_be32(&lbc->fbcr, 1); + set_addr(mtd, 0, 0, 0); + ctrl->read_bytes = 1; + + fsl_elbc_run_command(mtd); + + /* The chip always seems to report that it is + * write-protected, even when it is not. + */ + out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); + return; + + /* RESET without waiting for the ready line */ + case NAND_CMD_RESET: + dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); + out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); + out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); + fsl_elbc_run_command(mtd); + return; + + default: + printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", + command); + } +} + +static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) +{ + /* The hardware does not seem to support multiple + * chips per bank. + */ +} + +/* + * Write buf to the FCM Controller Data Buffer + */ +static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + unsigned int bufsize = mtd->writesize + mtd->oobsize; + + if (len < 0) { + printf("write_buf of %d bytes", len); + ctrl->status = 0; + return; + } + + if ((unsigned int)len > bufsize - ctrl->index) { + printf("write_buf beyond end of buffer " + "(%d requested, %u available)\n", + len, bufsize - ctrl->index); + len = bufsize - ctrl->index; + } + + memcpy_toio(&ctrl->addr[ctrl->index], buf, len); + ctrl->index += len; +} + +/* + * read a byte from either the FCM hardware buffer if it has any data left + * otherwise issue a command to read a single byte. + */ +static u8 fsl_elbc_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + + /* If there are still bytes in the FCM, then use the next byte. */ + if (ctrl->index < ctrl->read_bytes) + return in_8(&ctrl->addr[ctrl->index++]); + + printf("read_byte beyond end of buffer\n"); + return ERR_BYTE; +} + +/* + * Read from the FCM Controller Data Buffer + */ +static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + int avail; + + if (len < 0) + return; + + avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); + memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); + ctrl->index += avail; + + if (len > avail) + printf("read_buf beyond end of buffer " + "(%d requested, %d available)\n", + len, avail); +} + +/* + * Verify buffer against the FCM Controller Data Buffer + */ +static int fsl_elbc_verify_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + int i; + + if (len < 0) { + printf("write_buf of %d bytes", len); + return -EINVAL; + } + + if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { + printf("verify_buf beyond end of buffer " + "(%d requested, %u available)\n", + len, ctrl->read_bytes - ctrl->index); + + ctrl->index = ctrl->read_bytes; + return -EINVAL; + } + + for (i = 0; i < len; i++) + if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) + break; + + ctrl->index += len; + return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; +} + +/* This function is called after Program and Erase Operations to + * check for success or failure. + */ +static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + + if (ctrl->status != LTESR_CC) + return NAND_STATUS_FAIL; + + /* Use READ_STATUS command, but wait for the device to be ready */ + ctrl->use_mdr = 0; + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT)); + out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); + out_be32(&lbc->fbcr, 1); + set_addr(mtd, 0, 0, 0); + ctrl->read_bytes = 1; + + fsl_elbc_run_command(mtd); + + if (ctrl->status != LTESR_CC) + return NAND_STATUS_FAIL; + + /* The chip always seems to report that it is + * write-protected, even when it is not. + */ + out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); + return fsl_elbc_read_byte(mtd); +} + +static int fsl_elbc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf) +{ + fsl_elbc_read_buf(mtd, buf, mtd->writesize); + fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) + mtd->ecc_stats.failed++; + + return 0; +} + +/* ECC will be calculated automatically, and errors will be detected in + * waitfunc. + */ +static void fsl_elbc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + + fsl_elbc_write_buf(mtd, buf, mtd->writesize); + fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + ctrl->oob_poi = chip->oob_poi; +} + +static struct fsl_elbc_ctrl *elbc_ctrl; + +static void fsl_elbc_ctrl_init(void) +{ + immap_t *im = (immap_t *)CFG_IMMR; + + elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL); + if (!elbc_ctrl) + return; + + elbc_ctrl->regs = &im->lbus; + + /* clear event registers */ + out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK); + out_be32(&elbc_ctrl->regs->lteatr, 0); + + /* Enable interrupts for any detected events */ + out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK); + + elbc_ctrl->read_bytes = 0; + elbc_ctrl->index = 0; + elbc_ctrl->addr = NULL; +} + +int board_nand_init(struct nand_chip *nand) +{ + struct fsl_elbc_mtd *priv; + uint32_t br, or; + + if (!elbc_ctrl) { + fsl_elbc_ctrl_init(); + if (!elbc_ctrl) + return -1; + } + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ctrl = elbc_ctrl; + priv->vbase = nand->IO_ADDR_R; + + /* Find which chip select it is connected to. It'd be nice + * if we could pass more than one datum to the NAND driver... + */ + for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { + br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); + or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); + + if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && + (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R) + break; + } + + if (priv->bank >= MAX_BANKS) { + printf("fsl_elbc_nand: address did not match any " + "chip selects\n"); + return -ENODEV; + } + + elbc_ctrl->chips[priv->bank] = priv; + + /* fill in nand_chip structure */ + /* set up function call table */ + nand->read_byte = fsl_elbc_read_byte; + nand->write_buf = fsl_elbc_write_buf; + nand->read_buf = fsl_elbc_read_buf; + nand->verify_buf = fsl_elbc_verify_buf; + nand->select_chip = fsl_elbc_select_chip; + nand->cmdfunc = fsl_elbc_cmdfunc; + nand->waitfunc = fsl_elbc_wait; + + /* set up nand options */ + nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR; + + nand->controller = &elbc_ctrl->controller; + nand->priv = priv; + + nand->ecc.read_page = fsl_elbc_read_page; + nand->ecc.write_page = fsl_elbc_write_page; + + /* If CS Base Register selects full hardware ECC then use it */ + if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + nand->ecc.mode = NAND_ECC_HW; + + nand->ecc.layout = (priv->fmr & FMR_ECCM) ? + &fsl_elbc_oob_sp_eccm1 : + &fsl_elbc_oob_sp_eccm0; + + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = 1; + } else { + /* otherwise fall back to default software ECC */ + nand->ecc.mode = NAND_ECC_SOFT; + } + + priv->fmr = (12 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); + + /* adjust Option Register and ECC to match Flash page size */ + if (or & OR_FCM_PGS) { + priv->page_size = 1; + + /* adjust ecc setup if needed */ + if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + nand->ecc.steps = 4; + nand->ecc.layout = (priv->fmr & FMR_ECCM) ? + &fsl_elbc_oob_lp_eccm1 : + &fsl_elbc_oob_lp_eccm0; + } + } + + return 0; +} + +#endif -- 1.5.3

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[U-Boot-Users] Problems on IDE
by Rodolfo Giometti 25 Mar '08

25 Mar '08

Hello, on my custom board (PXA270) I have an IDE bus on DoM (mapped at 0x14400000) and an IDE bus on PCMCIA/CF (mapped at 0x20000000). The DoM works while CF not. Here my output (please, note that I modified a bit the cmd_ide code in order to remove a device from Standby Mode): equantum> pinit on CF Card CFA 128MB CHH 5.0 Fixed Disk Card IDE interface [silicon] [unique] [single] [sleep] [standby] [idle] [low power] equantum> ide reset Reset IDE: Bus 0: ide_outb (dev= 0, port= 0x1f6, val= 0xe0) : @ 0x144003ec ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x50 OK Bus 1: ide_outb (dev= 2, port= 0x1f6, val= 0xe0) : @ 0x200001f6 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x51 OK Device 0: ide_outb (dev= 0, port= 0x1f6, val= 0xe0) : @ 0x144003ec ide_inb (dev= 0, port= 0x1f2) : @ 0x144003e4 -> 0x01 ide_inb (dev= 0, port= 0x1f3) : @ 0x144003e6 -> 0x01 ide_inb (dev= 0, port= 0x1f4) : @ 0x144003e8 -> 0x00 ide_outb (dev= 0, port= 0x1f7, val= 0xec) : @ 0x144003ee ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0xd0 ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x58 in input data base for read is 144001f0 Model: PQI IDE DiskOnModule Firm: N050316D Ser#: OD4M0G000015 Type: Hard Disk Capacity: 499.5 MB = 0.4 GB (1023120 x 512) ide_read dev 0 start 0, blocks 1 buffer at A2EFF91C ide_outb (dev= 0, port= 0x1f6, val= 0xe0) : @ 0x144003ec ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x50 ide_outb (dev= 0, port= 0x1f7, val= 0xe5) : @ 0x144003ee ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x50 ide_inb (dev= 0, port= 0x1f2) : @ 0x144003e4 -> 0xff Powersaving FF ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x50 ide_outb (dev= 0, port= 0x1f2, val= 0x01) : @ 0x144003e4 ide_outb (dev= 0, port= 0x1f3, val= 0x00) : @ 0x144003e6 ide_outb (dev= 0, port= 0x1f4, val= 0x00) : @ 0x144003e8 ide_outb (dev= 0, port= 0x1f5, val= 0x00) : @ 0x144003ea ide_outb (dev= 0, port= 0x1f6, val= 0xe0) : @ 0x144003ec ide_outb (dev= 0, port= 0x1f7, val= 0x20) : @ 0x144003ee ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0xd0 ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x58 in input data base for read is 144001f0 ide_inb (dev= 0, port= 0x1f7) : @ 0x144003ee -> 0x50 Device 1: ide_outb (dev= 1, port= 0x1f6, val= 0xf0) : @ 0x144001f6 ide_inb (dev= 1, port= 0x1f2) : @ 0x144001f2 -> 0x00 ide_outb (dev= 1, port= 0x1f7, val= 0xec) : @ 0x144001f7 ide_inb (dev= 1, port= 0x1f7) : @ 0x144001f7 -> 0x00 Retrying... ide_outb (dev= 1, port= 0x1f6, val= 0xf0) : @ 0x144001f6 ide_outb (dev= 1, port= 0x1f7, val= 0x08) : @ 0x144001f7 ide_outb (dev= 1, port= 0x1f6, val= 0xf0) : @ 0x144001f6 ide_inb (dev= 1, port= 0x1f2) : @ 0x144001f2 -> 0x00 ide_outb (dev= 1, port= 0x1f7, val= 0xec) : @ 0x144001f7 ide_inb (dev= 1, port= 0x1f7) : @ 0x144001f7 -> 0x00 Retrying... ide_outb (dev= 1, port= 0x1f6, val= 0xf0) : @ 0x144001f6 ide_outb (dev= 1, port= 0x1f7, val= 0x08) : @ 0x144001f7 ide_outb (dev= 1, port= 0x1f6, val= 0xf0) : @ 0x144001f6 not available Device 2: ide_outb (dev= 2, port= 0x1f6, val= 0xe0) : @ 0x200001f6 ide_inb (dev= 2, port= 0x1f2) : @ 0x200001f2 -> 0x01 ide_inb (dev= 2, port= 0x1f3) : @ 0x200001f3 -> 0x01 ide_inb (dev= 2, port= 0x1f4) : @ 0x200001f4 -> 0x00 ide_outb (dev= 2, port= 0x1f7, val= 0xec) : @ 0x200001f7 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x58 in input data base for read is 200001f0 Model: 128MB CHH Firm: Rev 1.00 Ser#: 0524700CA802470033 Type: Removable Hard Disk Capacity: 122.2 MB = 0.1 GB (250368 x 512) ide_read dev 2 start 0, blocks 1 buffer at A2EFF91C ide_outb (dev= 2, port= 0x1f6, val= 0xe0) : @ 0x200001f6 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x51 ide_outb (dev= 2, port= 0x1f7, val= 0xe5) : @ 0x200001f7 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x50 ide_inb (dev= 2, port= 0x1f2) : @ 0x200001f2 -> 0x00 Powersaving 00 ide_outb (dev= 2, port= 0x1f7, val= 0xe3) : @ 0x200001f7 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x50 ide_outb (dev= 2, port= 0x1f7, val= 0xe5) : @ 0x200001f7 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x50 ide_inb (dev= 2, port= 0x1f2) : @ 0x200001f2 -> 0xff Powersaving FF ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x50 ide_outb (dev= 2, port= 0x1f2, val= 0x01) : @ 0x200001f2 ide_outb (dev= 2, port= 0x1f3, val= 0x00) : @ 0x200001f3 ide_outb (dev= 2, port= 0x1f4, val= 0x00) : @ 0x200001f4 ide_outb (dev= 2, port= 0x1f5, val= 0x00) : @ 0x200001f5 ide_outb (dev= 2, port= 0x1f6, val= 0xe0) : @ 0x200001f6 ide_outb (dev= 2, port= 0x1f7, val= 0x20) : @ 0x200001f7 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 2, port= 0x1f7) : @ 0x200001f7 -> 0x51 ide_inb (dev= 2, port= 0x1f1) : @ 0x200001f1 -> 0x10 Error (no IRQ) dev 2 blk 0: status 0x51/0x10 Device 3: ide_outb (dev= 3, port= 0x1f6, val= 0xf0) : @ 0x200001f6 ide_inb (dev= 3, port= 0x1f2) : @ 0x200001f2 -> 0x00 ide_outb (dev= 3, port= 0x1f7, val= 0xec) : @ 0x200001f7 ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0x58 in input data base for read is 200001f0 Model: 128MB CHH Firm: Rev 1.00 Ser#: 0524700CA802470033 Type: Removable Hard Disk Capacity: 122.2 MB = 0.1 GB (250368 x 512) ide_read dev 3 start 0, blocks 1 buffer at A2EFF91C ide_outb (dev= 3, port= 0x1f6, val= 0xf0) : @ 0x200001f6 ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0x00 ide_outb (dev= 3, port= 0x1f7, val= 0xe5) : @ 0x200001f7 ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0x50 ide_inb (dev= 3, port= 0x1f2) : @ 0x200001f2 -> 0xff Powersaving FF ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0x50 ide_outb (dev= 3, port= 0x1f2, val= 0x01) : @ 0x200001f2 ide_outb (dev= 3, port= 0x1f3, val= 0x00) : @ 0x200001f3 ide_outb (dev= 3, port= 0x1f4, val= 0x00) : @ 0x200001f4 ide_outb (dev= 3, port= 0x1f5, val= 0x00) : @ 0x200001f5 ide_outb (dev= 3, port= 0x1f6, val= 0xf0) : @ 0x200001f6 ide_outb (dev= 3, port= 0x1f7, val= 0x20) : @ 0x200001f7 ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0xd0 ide_inb (dev= 3, port= 0x1f7) : @ 0x200001f7 -> 0x51 ide_inb (dev= 3, port= 0x1f1) : @ 0x200001f1 -> 0x10 Error (no IRQ) dev 3 blk 0: status 0x51/0x10 As you can see device 0 is correctly recognized, device 1 is not present, and device 2 doesn't work while device 3, which is not present, gives answers similar to device 2! Device 2 is recognized but when the system tries to read the first sector it gets an error! Note also that on Linux the CF works correctly, so the PCMCIA memory settings should be ok. Here my board configuration: #define CONFIG_PXA_PCMCIA 1 #define CONFIG_PXA_IDE 1 #define CFG_IDE_MAXBUS 2 #define CFG_IDE_MAXDEVICE 4 #define CONFIG_PCMCIA_SLOT_A 1 /* just to keep build system happy */ #define CFG_PCMCIA_MEM_ADDR 0x28000000 #define CFG_PCMCIA_MEM_SIZE 0x04000000 /* Memory configuration */ #define CFG_MECR_VAL 0x00000002 #define CFG_MCMEM0_VAL 0x00010504 #define CFG_MCMEM1_VAL 0x00014511 #define CFG_MCATT0_VAL 0x00010504 #define CFG_MCATT1_VAL 0x00014511 #define CFG_MCIO0_VAL 0x00004715 #define CFG_MCIO1_VAL 0x00014511 #define CFG_ATA_BASE_ADDR 0x14000000 #define CFG_ATA_IDE0_OFFSET 0x00400000 /* for the DOM */ #define CFG_ATA_IDE1_OFFSET 0x0c000000 /* for the PCMCIA */ /* IDE device 0 is accessed at 16-bit only (A0 is not used) * while device 1 is accessed at 8-bit */ #define CFG_ATA_PORT_ADDR(dev, port) (((dev) < 1) ? ((port) << 1) : (port)) /* Offset for data I/O */ #define CFG_ATA_DATA_OFFSET 0x1f0 /* Offset for normal register accesses */ #define CFG_ATA_REG_OFFSET 0x1f0 /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET 0x3f0 /* We have ATAPI support */ #define CONFIG_ATAPI 1 Does someone know what's wrong? Thanks, Rodolfo -- GNU/Linux Solutions e-mail: giometti(a)enneenne.com Linux Device Driver giometti(a)gnudd.com Embedded Systems giometti(a)linux.it UNIX programming phone: +39 349 2432127

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