March 2008 - U-Boot

[U-Boot-Users] [PATCH v3 3/10] ata: make the ata_piix driver using new SATA framework
by Dave Liu 26 Mar '08

26 Mar '08

Original ata_piix driver is using the IDE framework, not real SATA framework. This patch makes the ata_piix driver use the new SATA framework, so - remove the duplicated command stuff - remove the CONFIG_CMD_IDE define in the sc520_cdp.h - add the CONFIG_CMD_SATA define to sc520_cdp.h Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- drivers/block/ata_piix.c | 161 +++++++------------------------------------ include/configs/sc520_cdp.h | 26 +------- include/sata.h | 4 +- 3 files changed, 28 insertions(+), 163 deletions(-) diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c index bf44e3d..db3922e 100644 --- a/drivers/block/ata_piix.c +++ b/drivers/block/ata_piix.c @@ -37,6 +37,9 @@ #ifdef CFG_ATA_PIIX /*ata_piix driver */ +extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE]; +extern int curr_device; + #define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ #define SATA_DECL @@ -144,19 +147,15 @@ sata_bus_probe (int port_no) } int -init_sata (void) +init_sata (int dev) { + static int done = 0; u8 i, rv = 0; - for (i = 0; i < CFG_SATA_MAXDEVICES; i++) { - sata_dev_desc[i].type = DEV_TYPE_UNKNOWN; - sata_dev_desc[i].if_type = IF_TYPE_IDE; - sata_dev_desc[i].dev = i; - sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; - sata_dev_desc[i].blksz = 0; - sata_dev_desc[i].lba = 0; - sata_dev_desc[i].block_read = sata_read; - } + if (!done) + done = 1; + else + return 0; rv = pci_sata_init (); if (rv == 1) { @@ -207,8 +206,8 @@ init_sata (void) dev_print (&sata_dev_desc[devno]); /* initialize partition type */ init_part (&sata_dev_desc[devno]); - if (curr_dev < 0) - curr_dev = + if (curr_device < 0) + curr_device = i * CFG_SATA_DEVS_PER_BUS + j; } } @@ -231,13 +230,13 @@ sata_outb (unsigned char val, unsigned long ioaddr) static void output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words) { -// outsw (ioaddr->data_addr, sect_buf, words << 1); + outsw (ioaddr->data_addr, sect_buf, words << 1); } static int input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words) { -// insw (ioaddr->data_addr, sect_buf, words << 1); + insw (ioaddr->data_addr, sect_buf, words << 1); return 0; } @@ -753,134 +752,24 @@ sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff) return n; } -block_dev_desc_t *sata_get_dev (int dev); - -block_dev_desc_t * -sata_get_dev (int dev) +int sata_low_level_read(int dev, u32 blknr, u32 blkcnt, void *buffer) { - return ((block_dev_desc_t *) & sata_dev_desc[dev]); + return sata_read(dev, blknr, blkcnt, buffer); } -int -do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int sata_low_level_write(int dev, u32 blknr, u32 blkcnt, void *buffer) { + return sata_write(dev, blknr, blkcnt, buffer); +} - switch (argc) { - case 0: - case 1: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 2: - if (strncmp (argv[1], "init", 4) == 0) { - int rcode = 0; - - rcode = init_sata (); - if (rcode) - printf ("Sata initialization Failed\n"); - return rcode; - } else if (strncmp (argv[1], "inf", 3) == 0) { - int i; - - putc ('\n'); - for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) { - /*List only known devices */ - if (sata_dev_desc[i].type == - DEV_TYPE_UNKNOWN) - continue; - printf ("sata dev %d: ", i); - dev_print (&sata_dev_desc[i]); - } - return 0; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 3: - if (strcmp (argv[1], "dev") == 0) { - int dev = (int) simple_strtoul (argv[2], NULL, 10); - - if (dev >= CFG_SATA_MAXDEVICES) { - printf ("\nSata dev %d not available\n", - dev); - return 1; - } - printf ("\nSATA dev %d: ", dev); - dev_print (&sata_dev_desc[dev]); - if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN) - return 1; - curr_dev = dev; - return 0; - } else if (strcmp (argv[1], "part") == 0) { - int dev = (int) simple_strtoul (argv[2], NULL, 10); - - if (dev >= CFG_SATA_MAXDEVICES) { - printf ("\nSata dev %d not available\n", - dev); - return 1; - } - PRINTF ("\nSATA dev %d: ", dev); - if (sata_dev_desc[dev].part_type != - PART_TYPE_UNKNOWN) { - print_part (&sata_dev_desc[dev]); - } else { - printf ("\nSata dev %d partition type " - "unknown\n", dev); - return 1; - } - return 0; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - default: - if (argc < 5) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - if (strcmp (argv[1], "read") == 0) { - ulong addr = simple_strtoul (argv[2], NULL, 16); - ulong cnt = simple_strtoul (argv[4], NULL, 16); - ulong n; - lbaint_t blk = simple_strtoul (argv[3], NULL, 16); - - memset ((int *) addr, 0, cnt * 512); - printf ("\nSATA read: dev %d blk # %ld," - "count %ld ... ", curr_dev, blk, cnt); - n = sata_read (curr_dev, blk, cnt, (ulong *) addr); - /* flush cache after read */ - flush_cache (addr, cnt * 512); - printf ("%ld blocks read: %s\n", n, - (n == cnt) ? "OK" : "ERR"); - if (n == cnt) - return 1; - else - return 0; - } else if (strcmp (argv[1], "write") == 0) { - ulong addr = simple_strtoul (argv[2], NULL, 16); - ulong cnt = simple_strtoul (argv[4], NULL, 16); - ulong n; - lbaint_t blk = simple_strtoul (argv[3], NULL, 16); - - printf ("\nSata write: dev %d blk # %ld," - "count %ld ... ", curr_dev, blk, cnt); - n = sata_write (curr_dev, blk, cnt, (ulong *) addr); - printf ("%ld blocks written: %s\n", n, - (n == cnt) ? "OK" : "ERR"); - if (n == cnt) - return 1; - else - return 0; - } else { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - } /*End OF SWITCH */ +int sata_low_level_init(int dev) +{ + return init_sata(dev); } -U_BOOT_CMD (sata, 5, 1, do_sata, - "sata init\n" - "sata info\n" - "sata part device\n" - "sata dev device\n" - "sata read addr blk# cnt\n" - "sata write addr blk# cnt\n", "cmd for init,rw and dev-info\n"); +int sata_low_level_scan(int dev) +{ + return 0; +} #endif diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 58d656c..4df461d 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -81,8 +81,8 @@ #include <config_cmd_default.h> #define CONFIG_CMD_PCI +#define CONFIG_CMD_SATA #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_IDE #define CONFIG_CMD_NET #define CONFIG_CMD_EEPROM @@ -173,36 +173,14 @@ #define PCNET_HAS_PROM 1 /************************************************************ - * IDE/ATA stuff - ************************************************************/ -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -/*#define CFG_ATA_IDE1_OFFSET 0x0170 /###* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ -#define CFG_ATA_BASE_ADDR 0 - -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ - -/************************************************************ *SATA/Native Stuff ************************************************************/ #define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ #define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ -#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) +#define CFG_SATA_MAX_DEVICE (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) #define CFG_ATA_PIIX 1 /*Supports ata_piix driver */ /************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ - -/************************************************************ * DISK Partition support ************************************************************/ #define CONFIG_DOS_PARTITION diff --git a/include/sata.h b/include/sata.h index bb1acb3..ed2e4d5 100644 --- a/include/sata.h +++ b/include/sata.h @@ -82,11 +82,9 @@ void msleep (int count); /************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/ #ifdef DRV_DECL /*Driver specific declaration */ -int init_sata (void); +int init_sata (int dev); #endif #ifdef DRV_DECL /*Defines Driver Specific variables */ struct sata_port port[CFG_SATA_MAXBUS]; -block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; -int curr_dev = -1; #endif -- 1.5.4.rc4

1 0

[U-Boot-Users] pio problem ngw100
by László Tóth 26 Mar '08

26 Mar '08

Hay I original firwmare in ngw 100 downloaded http://avr32linux.org/twiki/bin/view/Main/PramodeCE "pio led " blink compiled gcc and download device run program segmantation fault What a problem ? tothlaszloster(a)gmail.com

2 1

[U-Boot-Users] [PATCH] Add support for new AVR32 board
by Alex 26 Mar '08

26 Mar '08

Hi This patch adds support for our new AVR32 based board. diff -Nur old/u-boot-1.3.0/board/miromico/hammerhead/config.mk new/u-boot-1.3.0/board/miromico/hammerhead/config.mk --- old/u-boot-1.3.0/board/miromico/hammerhead/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/board/miromico/hammerhead/config.mk 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff -Nur old/u-boot-1.3.0/board/miromico/hammerhead/eth.c new/u-boot-1.3.0/board/miromico/hammerhead/eth.c --- old/u-boot-1.3.0/board/miromico/hammerhead/eth.c 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/board/miromico/hammerhead/eth.c 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Ethernet initialization for the AVR32 on Hammerhead + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/arch/memory-map.h> + +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#ifdef CONFIG_CMD_NET +void hammerhead_eth_initialize(bd_t *bi) +{ + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); +} +#endif diff -Nur old/u-boot-1.3.0/board/miromico/hammerhead/flash.c new/u-boot-1.3.0/board/miromico/hammerhead/flash.c --- old/u-boot-1.3.0/board/miromico/hammerhead/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/board/miromico/hammerhead/flash.c 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#ifdef CONFIG_HAMMERHEAD_EXT_FLASH +#include <asm/cacheflush.h> +#include <asm/io.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +flash_info_t flash_info[1]; + +static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + + writew(0xaa, flash + 0x555); + writew(0x55, flash + 0xaaa); + writew(0x90, flash + 0x555); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + if (flags) + enable_interrupts(); +} + +unsigned long flash_init(void) +{ + unsigned long addr; + unsigned int i; + + flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].sector_count = 135; + + flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CFG_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + info->flash_id >> 16, info->flash_id & 0xffff); + printf("Size: %ld MB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + unsigned long start_time; + uint16_t *fb, *sb; + unsigned int i; + int ret; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + printf("Erasing sector %3d...", i); + + sb = (uint16_t *)uncached(info->start[i]); + + flags = disable_interrupts(); + + start_time = get_timer(0); + + /* Unlock sector */ + writew(0xaa, fb + 0x555); + writew(0x70, sb); + + /* Erase sector */ + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x80, fb + 0x555); + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x30, sb); + + /* Wait for completion */ + ret = ERR_OK; + do { + /* TODO: Timeout */ + status = readw(sb); + } while ((status != 0xffff) && !(status & 0x28)); + + writew(0xf0, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + if (flags) + enable_interrupts(); + + if (status != 0xffff) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int __flashprog write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status, status1; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0xaa, base + 0x555); + writew(0x55, base + 0xaaa); + writew(0xa0, base + 0x555); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + status1 = readw(p); + do { + /* TODO: Timeout */ + status = status1; + status1 = readw(p); + } while (((status ^ status1) & 0x40) /* toggled */ + && !(status1 & 0x28)); /* error bits */ + + /* + * We'll need to check once again for toggle bit + * because the toggle bit may stop toggling as I/O5 + * changes to "1" (ref at49bv642.pdf p9) + */ + status1 = readw(p); + status = readw(p); + if ((status ^ status1) & 0x40) { + printf("Flash write error at address 0x%p: " + "0x%02x != 0x%02x\n", + p, status,word); + ret = ERR_PROG_ERROR; + writew(0xf0, base); + readw(base); + break; + } + + writew(0xf0, base); + readw(base); + } + + if (flags) + enable_interrupts(); + + return ret; +} + +#endif /* CONFIG_HAMMERHEAD_EXT_FLASH */ diff -Nur old/u-boot-1.3.0/board/miromico/hammerhead/hammerhead.c new/u-boot-1.3.0/board/miromico/hammerhead/hammerhead.c --- old/u-boot-1.3.0/board/miromico/hammerhead/hammerhead.c 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/board/miromico/hammerhead/hammerhead.c 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix2.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_info sdram = { + .phys_addr = CFG_SDRAM_BASE, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, +}; + +int board_early_init_f(void) +{ + /* Set the SDRAM_ENABLE bit in the HEBI SFR */ + hmatrix2_writel(SFR4, 1 << 1); + + gpio_enable_ebi(); + gpio_enable_usart1(); + +#if defined(CONFIG_MACB) + gpio_enable_macb0(); +#endif +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + +#ifdef CONFIG_HAMMERHEAD + /* Select GCLK3 as periph. We'll need it as clock + output for ethernet PHY */ + gpio_enable_gclk3(); +#endif + + return 0; +} + +long int initdram(int board_type) +{ + return sdram_init(&sdram); +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x01; +} diff -Nur old/u-boot-1.3.0/board/miromico/hammerhead/Makefile new/u-boot-1.3.0/board/miromico/hammerhead/Makefile --- old/u-boot-1.3.0/board/miromico/hammerhead/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/board/miromico/hammerhead/Makefile 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,40 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o flash.o eth.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -Nur old/u-boot-1.3.0/board/miromico/hammerhead/u-boot.lds new/u-boot-1.3.0/board/miromico/hammerhead/u-boot.lds --- old/u-boot-1.3.0/board/miromico/hammerhead/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/board/miromico/hammerhead/u-boot.lds 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,80 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.text) + *(.text.*) + } + + . = ALIGN(32); + __flashprog_start = .; + .flashprog : { + *(.flashprog) + } + . = ALIGN(32); + __flashprog_end = .; + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff -Nur old/u-boot-1.3.0/cpu/at32ap/at32ap700x/gpio.c new/u-boot-1.3.0/cpu/at32ap/at32ap700x/gpio.c --- old/u-boot-1.3.0/cpu/at32ap/at32ap700x/gpio.c 2008-03-06 07:56:03.000000000 +0100 +++ new/u-boot-1.3.0/cpu/at32ap/at32ap700x/gpio.c 2008-03-10 11:18:51.000000000 +0100 @@ -142,3 +142,14 @@ gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ } #endif + +#ifdef CONFIG_HAMMERHEAD +/* + * Hammerhead board uses GCLK3 (Periph A on PB29) as 25MHz clock output + * for ethernet PHY. + */ +void gpio_enable_gclk3(void) +{ + gpio_select_periph_A(GPIO_PIN_PB29, 0); /* GCLK3 */ +} +#endif diff -Nur old/u-boot-1.3.0/cpu/at32ap/cpu.c new/u-boot-1.3.0/cpu/at32ap/cpu.c --- old/u-boot-1.3.0/cpu/at32ap/cpu.c 2007-11-19 22:20:24.000000000 +0100 +++ new/u-boot-1.3.0/cpu/at32ap/cpu.c 2008-03-10 11:18:51.000000000 +0100 @@ -81,6 +81,16 @@ #endif } +#ifdef CONFIG_HAMMERHEAD +static void gclk_init(void) +{ + /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ + + /* Enable GCLK3 with no input divider, from OSC0 (crystal) */ + sm_writel( PM_GCCTRL3, SM_BIT(CEN) ); +} +#endif + int cpu_init(void) { extern void _evba(void); @@ -105,6 +115,10 @@ p += CFG_ICACHE_LINESZ) asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory"); +#ifdef CONFIG_HAMMERHEAD + gclk_init(); +#endif + return 0; } diff -Nur old/u-boot-1.3.0/cpu/at32ap/sm.h new/u-boot-1.3.0/cpu/at32ap/sm.h --- old/u-boot-1.3.0/cpu/at32ap/sm.h 2007-11-19 22:20:24.000000000 +0100 +++ new/u-boot-1.3.0/cpu/at32ap/sm.h 2008-03-10 11:18:51.000000000 +0100 @@ -21,7 +21,15 @@ #define SM_PM_IMR 0x0048 #define SM_PM_ISR 0x004c #define SM_PM_ICR 0x0050 -#define SM_PM_GCCTRL 0x0060 +#define SM_PM_GCCTRL0 0x0060 +#define SM_PM_GCCTRL1 0x0064 +#define SM_PM_GCCTRL2 0x0068 +#define SM_PM_GCCTRL3 0x006c +#define SM_PM_GCCTRL4 0x0070 +#define SM_PM_GCCTRL5 0x0074 +#define SM_PM_GCCTRL6 0x0078 +#define SM_PM_GCCTRL7 0x007c + #define SM_RTC_CTRL 0x0080 #define SM_RTC_VAL 0x0084 #define SM_RTC_TOP 0x0088 diff -Nur old/u-boot-1.3.0/include/asm-avr32/arch-at32ap700x/gpio.h new/u-boot-1.3.0/include/asm-avr32/arch-at32ap700x/gpio.h --- old/u-boot-1.3.0/include/asm-avr32/arch-at32ap700x/gpio.h 2008-03-06 07:56:04.000000000 +0100 +++ new/u-boot-1.3.0/include/asm-avr32/arch-at32ap700x/gpio.h 2008-03-10 11:18:50.000000000 +0100 @@ -217,4 +217,8 @@ void gpio_enable_mmci(void); #endif +#ifdef CONFIG_HAMMERHEAD +void gpio_enable_gclk3(void); +#endif + #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff -Nur old/u-boot-1.3.0/include/configs/hammerhead.h new/u-boot-1.3.0/include/configs/hammerhead.h --- old/u-boot-1.3.0/include/configs/hammerhead.h 1970-01-01 01:00:00.000000000 +0100 +++ new/u-boot-1.3.0/include/configs/hammerhead.h 2008-03-10 11:18:50.000000000 +0100 @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * Configuration settings for the AVR32 Network Gateway + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_HAMMERHEAD 1 + +#define CONFIG_HAMMERHEAD_EXT_FLASH 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 25000000 /* 25MHz crystal */ +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 5 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresse + * should be generated and assigned to the environment variables + * "ethaddr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + CFG_SDRAM_BASE + gd->sdram_size; \ + }) +#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) + +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ + +/* Add a wrapper around the values Buildroot sets. */ +#ifndef __BR2_ADDED_CONFIG_H +#define __BR2_ADDED_CONFIG_H +#define CONFIG_HOSTNAME hammerhead +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "fsload 0x90300000 /boot/uImage; bootm" +#endif /* __BR2_ADDED_CONFIG_H */ diff -Nur old/u-boot-1.3.0/MAINTAINERS new/u-boot-1.3.0/MAINTAINERS --- old/u-boot-1.3.0/MAINTAINERS 2008-03-06 07:56:03.000000000 +0100 +++ new/u-boot-1.3.0/MAINTAINERS 2008-03-10 11:18:50.000000000 +0100 @@ -636,6 +636,9 @@ ATSTK1004 AT32AP7002 ATNGW100 AT32AP7000 +Alex Raimondi <alex.raimondi(a)miromico.ch> + HAMMERHEAD AT32AP7000 + ######################################################################### # End of MAINTAINERS list # ######################################################################### diff -Nur old/u-boot-1.3.0/MAKEALL new/u-boot-1.3.0/MAKEALL --- old/u-boot-1.3.0/MAKEALL 2008-03-06 07:56:03.000000000 +0100 +++ new/u-boot-1.3.0/MAKEALL 2008-03-10 11:18:50.000000000 +0100 @@ -644,6 +644,7 @@ atstk1003 \ atstk1004 \ atngw100 \ + hammerhead \ " ######################################################################### diff -Nur old/u-boot-1.3.0/Makefile new/u-boot-1.3.0/Makefile --- old/u-boot-1.3.0/Makefile 2008-03-06 07:56:03.000000000 +0100 +++ new/u-boot-1.3.0/Makefile 2008-03-10 11:18:50.000000000 +0100 @@ -2618,6 +2618,9 @@ atngw100_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x +hammerhead_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap hammerhead miromico at32ap700x + ######################################################################### ######################################################################### ######################################################################### diff -Nur old/u-boot-1.3.0/net/eth.c new/u-boot-1.3.0/net/eth.c --- old/u-boot-1.3.0/net/eth.c 2008-03-06 07:56:04.000000000 +0100 +++ new/u-boot-1.3.0/net/eth.c 2008-03-10 11:18:50.000000000 +0100 @@ -61,6 +61,7 @@ extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); extern int atngw100_eth_initialize(bd_t *); +extern int hammerhead_eth_initialize(bd_t *); extern int mcffec_initialize(bd_t*); static struct eth_device *eth_devices, *eth_current; @@ -258,6 +259,9 @@ #if defined(CONFIG_ATNGW100) atngw100_eth_initialize(bis); #endif +#if defined(CONFIG_HAMMERHEAD) + hammerhead_eth_initialize(bis); +#endif #if defined(CONFIG_MCFFEC) mcffec_initialize(bis); #endif @@ -522,6 +526,7 @@ extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); extern int dm644x_eth_miiphy_initialize(bd_t *bis); +extern int hammerhead_eth_initialize(bd_t *); int eth_initialize(bd_t *bis) @@ -546,6 +551,9 @@ #if defined(CONFIG_DRIVER_TI_EMAC) dm644x_eth_miiphy_initialize(bis); #endif +#if defined(CONFIG_HAMMERHEAD) + hammerhead_eth_initialize(bis); +#endif return 0; } #endif

7 9

[U-Boot-Users] [PATCH v3] ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
by Stefan Roese 26 Mar '08

26 Mar '08

If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, that recalculate the memory size from the SDRAM controller setup will have to get fixed. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommendet to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr(a)denx.de> --- Changes in this version v3: - Changed value of CFG_MEM_TOP_HIDE from 256 to 4k so that memory end location is on a page boundary - Rebased on current git version Changes in this version v2: - Changed name of define to CFG_MEM_TOP_HIDE include/configs/korat.h | 2 ++ include/configs/lwmon5.h | 2 ++ include/configs/sequoia.h | 4 +++- lib_ppc/board.c | 13 +++++++++++++ 4 files changed, 20 insertions(+), 1 deletions(-) diff --git a/include/configs/korat.h b/include/configs/korat.h index dcec9b0..de672ea 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -144,6 +144,8 @@ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB #define CFG_DRAM_TEST +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* * I2C diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ced7ba6..3056cb0 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -86,6 +86,8 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) /* unused GPT0 COMP reg */ +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* Additional registers for watchdog timer post test */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index dfa8779..555316f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -221,6 +221,8 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* * I2C @@ -275,7 +277,7 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty addmisc;" \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 3ab22f8..f0a2c87 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -425,6 +425,7 @@ void board_init_f (ulong bootflag) * relocate the code and continue running from DRAM. * * Reserve memory at end of RAM for (top down in that order): + * - area that won't get touched by U-Boot and Linux (optional) * - kernel log buffer * - protected RAM * - LCD framebuffer @@ -433,6 +434,18 @@ void board_init_f (ulong bootflag) */ len = (ulong)&_end - CFG_MONITOR_BASE; + /* + * Subtract specified amount of memory to hide so that it won't + * get "touched" at all by U-Boot. By fixing up gd->ram_size + * the Linux kernel should now get passed the now "corrected" + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. + */ + gd->ram_size -= CFG_MEM_TOP_HIDE; + #ifndef CONFIG_MAX_MEM_MAPPED #define CONFIG_MAX_MEM_MAPPED (256 << 20) #endif -- 1.5.4.4

2 2

[U-Boot-Users] Pull request USB
by Markus Klotzbücher 26 Mar '08

26 Mar '08

The following changes since commit 18e69a35efbb078403db0c0063986470dad7d082: Anton Vorontsov (1): 83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role are available in the git repository at: git://www.denx.de/git/u-boot-usb.git master Aras Vaichas (1): USB Storage, add meaningful return value common/cmd_usb.c | 3 +-- common/usb_storage.c | 9 ++++++--- 2 files changed, 7 insertions(+), 5 deletions(-) Viele Grüße / Best regards Markus Klotzbücher -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de

2 1

[U-Boot-Users] [PATCH] ppc4xx: Add AMCC Glacier 406GT eval board support
by Stefan Roese 26 Mar '08

26 Mar '08

This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr(a)denx.de> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 9 ++- board/amcc/canyonlands/canyonlands.c | 25 ++++--- cpu/ppc4xx/4xx_enet.c | 51 +++++++++++++- include/configs/canyonlands.h | 125 +++++++++++++++++++++++++++++++--- include/ppc440.h | 4 + include/ppc4xx_enet.h | 4 + 8 files changed, 195 insertions(+), 25 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index e31ea06..d9ffebf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -322,6 +322,7 @@ Stefan Roese <sr(a)denx.de> bunbinga PPC405EP canyonlands PPC460EX ebony PPC440GP + glacier PPC460GT haleakala PPC405EXr katmai PPC440SPe kilauea PPC405EX diff --git a/MAKEALL b/MAKEALL index 01573da..b2ae35b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -185,6 +185,7 @@ LIST_4xx=" \ ERIC \ EXBITGEN \ G2000 \ + glacier \ haleakala \ haleakala_nand \ hcu4 \ diff --git a/Makefile b/Makefile index 4fde699..f3a0e47 100644 --- a/Makefile +++ b/Makefile @@ -1170,8 +1170,13 @@ bubinga_config: unconfig CANBT_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd -canyonlands_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc +# Canyonlands & Glacier use different U-Boot images +canyonlands_config \ +glacier_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ + tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h + @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc canyonlands_nand_config: unconfig @mkdir -p $(obj)include $(obj)board/amcc/canyonlands diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 36779f5..fa3ae85 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { u32 sdr0_cust0; + u32 pvr = get_pvr(); /*------------------------------------------------------------------+ * Setup the interrupt controller polarities, triggers, etc. @@ -105,14 +106,16 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) { + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + } return 0; } @@ -369,6 +372,7 @@ int misc_init_r(void) { u32 sdr0_srst1 = 0; u32 eth_cfg; + u32 pvr = get_pvr(); /* * Set EMAC mode/configuration (GMII, SGMII, RGMII...). @@ -382,7 +386,10 @@ int misc_init_r(void) /* Set the for 2 RGMII mode */ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) + eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + else + eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; mtsdr(SDR0_ETH_CFG, eth_cfg); /* diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index d990250..4541a14 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -275,6 +275,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; + u32 eth_cfg = 0; out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -308,6 +309,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) hw_p->print_speed = 1; /* print speed message again next time */ #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + eth_cfg &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, eth_cfg); +#endif + return; } @@ -494,11 +502,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) u32 zmiifer; /* ZMII0_FER reg. */ u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ + int mode; zmiifer = 0; rmiifer = 0; rmiifer1 = 0; +#if defined(CONFIG_460EX) + mode = 9; +#else + mode = 10; +#endif + /* TODO: * NOTE: 460GT has 2 RGMII bridge cores: * emac0 ------ RGMII0_BASE @@ -520,7 +535,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) * Right now only 2*RGMII is supported. Please extend when needed. * sr - 2008-02-19 */ - switch (9) { + switch (mode) { case 1: /* 1 MII - 460EX */ /* GMC0 EMAC4_0, ZMII Bridge */ @@ -836,10 +851,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = CONFIG_PHY1_ADDR; break; #endif -#if defined (CONFIG_440GX) +#if defined (CONFIG_PHY2_ADDR) case 2: reg = CONFIG_PHY2_ADDR; break; +#endif +#if defined (CONFIG_PHY3_ADDR) case 3: reg = CONFIG_PHY3_ADDR; break; @@ -1131,7 +1148,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx); + mtdcr (malrxctp8r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); #else @@ -1160,6 +1177,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ +#if defined (CONFIG_460GT) + case 2: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (malrxctp16r, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); + break; + case 3: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp3r, hw_p->tx_phys); + mtdcr (malrxctp24r, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); + break; +#endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ @@ -1866,14 +1903,22 @@ int ppc_4xx_eth_initialize (bd_t * bis) case 2: memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], bis->bi_enet2addr, 6); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x300; +#else hw_addr[eth_num] = 0x400; +#endif break; #endif #ifdef CONFIG_HAS_ETH3 case 3: memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], bis->bi_enet3addr, 6); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x400; +#else hw_addr[eth_num] = 0x600; +#endif break; #endif } diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index a4bcc65..76a2f7c 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -27,10 +27,14 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */ +/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */ +#ifndef CONFIG_CANYONLANDS +#define CONFIG_460GT 1 /* Specific PPC460GT */ +#else +#define CONFIG_460EX 1 /* Specific PPC460EX */ +#endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_460EX 1 /* Specific PPC460EX support */ #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ @@ -262,8 +266,15 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 -#define CONFIG_HAS_ETH0 1 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +/* Only Glacier (460GT) has 4 EMAC interfaces */ +#ifdef CONFIG_460GT +#define CONFIG_PHY2_ADDR 2 +#define CONFIG_PHY3_ADDR 3 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#endif #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ @@ -275,6 +286,8 @@ /*----------------------------------------------------------------------- * USB-OHCI *----------------------------------------------------------------------*/ +/* Only Canyonlands (460EX) has USB */ +#ifdef CONFIG_460EX #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */ @@ -283,6 +296,7 @@ #define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000) #define CFG_USB_OHCI_SLOT_NAME "ppc440" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#endif /*----------------------------------------------------------------------- * Default environment @@ -293,9 +307,21 @@ #undef CONFIG_BOOTARGS +/* Setup some board specific values for the default environment variables */ +#ifdef CONFIG_CANYONLANDS +#define CONFIG_HOSTNAME canyonlands +#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0" +#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0" +#else +#define CONFIG_HOSTNAME glacier +#define CFG_BOOTFILE "bootfile=glacier/uImage\0" +#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_DTBFILE \ "netdev=eth0\0" \ - "hostname=canyonlands\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -315,18 +341,16 @@ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "bootfile=canyonlands/uImage\0" \ - "fdt_file=canyonlands/canyonlands.dtb\0" \ "fdt_addr=400000\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc200000\0" \ "initrd_high=30000000\0" \ - "load=tftp 200000 canyonlands/u-boot.bin\0" \ + "load=tftp 200000 ${hostname}/u-boot.bin\0" \ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ "cp.b ${fileaddr} fffa0000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ - "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \ + "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" \ @@ -361,8 +385,6 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII @@ -373,7 +395,11 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM +#ifdef CONFIG_460EX +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_USB +#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -487,6 +513,8 @@ /* * PPC4xx GPIO Configuration */ +#ifdef CONFIG_460EX +/* 460EX: Use USB configuration */ #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ @@ -559,6 +587,81 @@ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ } \ } +#else +/* 460GT: Use EMAC2+3 configuration */ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} +#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 diff --git a/include/ppc440.h b/include/ppc440.h index 10517cb..642d1de 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -2023,9 +2023,13 @@ #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */ #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ #endif /* CONFIG_440GX */ diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 0208454..89ff26f 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st { #define RGMII_FER (RGMII_BASE + 0x00) #define RGMII_SSR (RGMII_BASE + 0x04) +#if defined(CONFIG_460GT) +#define RGMII1_BASE_OFFSET 0x100 +#endif + /* RGMII Function Enable (FER) Register Bit Definitions */ /* Note: for EMAC 2 and 3 only, 440GX only */ #define RGMII_FER_DIS (0x00) -- 1.5.4.4

1 0

[U-Boot-Users] How to download u-boot source code
by Chen Xue Yi, PB SHA 26 Mar '08

26 Mar '08

Hi,all I try to download the uboot as the following showed, but I failed. Is there anyone knows how to solve this problem? cmd: git-clone http://www.denx.de/git/u-boot.git <http://www.denx.de/git/u-boot.git> uboot the output is: Initialized empty Git repository in d:/04Src/00Uboot/uboot/.git/ Cannot get remote repository information. Perhaps git-update-server-info needs to be run there? Chen Xueyi R&D,Nokia-Siemens Networks Transport System CO. Building 89, 1122 Qin Zhou Bei Road, Shanghai Tel: + 86 21 34284528 Ext.7154 FAX: + 86 21 54264807

2 1

[U-Boot-Users] [PATCH] DM644x: (2nd try) This adds support for theProdrive PMDRA board, based on a DM6441
by Pieter Voorthuijsen 26 Mar '08

26 Mar '08

2nd try, previous one was wrapped: Double checked spaces and coding style... Original message: Hello, This patch adds support for the new Prodrive PMDR-A board. It is based on the DaVinci DM6441 processor, has 256M DDR2, 8M NOR and 256M of NAND. (This requires the previous patch that removes board specific code from /cpu/arm926ejs/davinci) Best regards, Pieter Pieter Voorthuijsen Prodrive B.V. Science Park Eindhoven P.O. box 28030 5602 JA Eindhoven The Netherlands Email pieter.voorthuijsen(a)prodrive.nl Tel: +31-40-2676258 Fax: +31-40-2676201

4 7

[U-Boot-Users] [PATCH 7/7] tsec: fix link detection for the RTL8211B PHY
by Anton Vorontsov 26 Mar '08

26 Mar '08

RTL8211B sets link state register after autonegotiation complete, so with bootdelay=0 RTL8211B will report lack of the link. To fix this, we should wait for aneg to complete, even if the link is currently down. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- drivers/net/tsec.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e91d9ea..431a8d2 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -583,10 +583,11 @@ uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) uint speed; mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); - if ((mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) && - !(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { + if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { int i = 0; + /* in case of timeout ->link is cleared */ + priv->link = 1; puts("Waiting for PHY realtime link"); while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { /* Timeout reached ? */ -- 1.5.2.2

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[U-Boot-Users] compile uboot error
by jie zhao 26 Mar '08

26 Mar '08

I compile u-boot1.2.0 using cross2.95.3 cross3.3.2 and cross3.4.1 ,but all failed. make[1]: Leaving directory `/home/jiejie/uboot/u-boot-1.2.0/post/cpu' make -C cpu/arm920t start.o make[1]: Entering directory `/home/jiejie/uboot/u-boot-1.2.0/cpu/arm920t' /usr/local/arm/3.3.2/bin/arm-linux-gcc -D__ASSEMBLY__ -g -Os -fno-strict-aliasing -fno-common -ffixed-r8 -msoft-float -mshort-load-bytes -D__KERNEL__ -DTEXT_BASE=0x33F80000 -I/home/jiejie/uboot/u-boot-1.2.0/include -fno-builtin -ffreestanding -nostdinc -isystem /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/include -pipe -DCONFIG_ARM -D__ARM__ -march=armv4 -mapcs-32 -c -o start.o start.S start.S: Assembler messages: start.S:185: Error: internal_relocation (type: OFFSET_IMM) not fixed up start.S:186: Error: internal_relocation (type: OFFSET_IMM) not fixed up start.S:188: Error: internal_relocation (type: OFFSET_IMM) not fixed up start.S:190: Error: internal_relocation (type: OFFSET_IMM) not fixed up start.S:200: Error: internal_relocation (type: OFFSET_IMM) not fixed up start.S:204: Error: internal_relocation (type: OFFSET_IMM) not fixed up start.S:206: Error: internal_relocation (type: OFFSET_IMM) not fixed up make[1]: *** [start.o] error 1 make[1]: Leaving directory `/home/jiejie/uboot/u-boot-1.2.0/cpu/arm920t' make: *** [cpu/arm920t/start.o] error 2 Please tell me why ,thankyou very much!

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