March 2008 - U-Boot

[U-Boot-Users] [PATCH 1/1] Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
by Joe D'Abbraccio 25 Mar '08

25 Mar '08

From: Joe D'Abbraccio <ljd015(a)freescale.com> With the original value of 1/2 clock cycle delay, the system ran relatively stable except when we run benchmarks that are intensive users of memory. When I run samba connected disk with a HDBENCH test, the system locks-up or reboots sporadically. Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio(a)freescale.com> --- include/configs/MPC8349ITX.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 0e50186..6b8b74d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -156,7 +156,7 @@ #define CFG_MEMTEST_END 0x2000 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ -- 1.5.4.4

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[U-Boot-Users] [PATCH 0/11] Few MPC8360E-RDK related patches
by Anton Vorontsov 25 Mar '08

25 Mar '08

This are few fixes and enhancements I have sitting in my rdk branch for a while now... -- Anton Vorontsov email: cboumailru(a)gmail.com irc://irc.freenode.net/bd2

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[U-Boot-Users] [PATCH 2/2] mpc83xx: MPC837XERDB: add support for PCI-Express
by Anton Vorontsov 25 Mar '08

25 Mar '08

This is largely based on the MDS boards' code (patch by Tony Li <tony.li(a)freescale.com>). Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc837xerdb/Makefile | 5 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 13 ++++- board/freescale/mpc837xerdb/pcie.c | 87 +++++++++++++++++++++++++++++ include/configs/MPC837XERDB.h | 28 +++++++++ 4 files changed, 131 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mpc837xerdb/pcie.c diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index 5ec7a87..5d9e188 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -25,8 +25,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_PCIE) += pcie.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 70f52da..78e208f 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -19,7 +19,7 @@ #include <asm/fsl_serdes.h> #include <spd_sdram.h> #include <vsc7385.h> - +#include "pcie.h" #if defined(CFG_DRAM_TEST) int @@ -170,6 +170,17 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ + immap_t *immr = (immap_t *)CFG_IMMR; + u32 part = in_be32(&immr->sysconf.spridr) >> 16; + + if (part != SPR_8379E_REV10 >> 16 && part != SPR_8379_REV10 >> 16) + pcie_init_board(); + + return 0; +} + /* * Miscellaneous late-boot configurations * diff --git a/board/freescale/mpc837xerdb/pcie.c b/board/freescale/mpc837xerdb/pcie.c new file mode 100644 index 0000000..2fba8b9 --- /dev/null +++ b/board/freescale/mpc837xerdb/pcie.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Tony Li <tony.li(a)freescale.com> + * Copyright (C) 2008 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov(a)ru.mvista.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <asm/mmu.h> +#include <asm/io.h> +#include <asm/mpc83xx_pcie.h> +#include <common.h> +#include <mpc83xx.h> +#include <pci.h> + +static struct pci_region pci_regions_0[] = { + { + bus_start: CFG_PCIE1_MEM_BASE, + phys_start: CFG_PCIE1_MEM_PHYS, + size: CFG_PCIE1_MEM_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCIE1_IO_BASE, + phys_start: CFG_PCIE1_IO_PHYS, + size: CFG_PCIE1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +static struct pci_region pci_regions_1[] = { + { + bus_start: CFG_PCIE2_MEM_BASE, + phys_start: CFG_PCIE2_MEM_PHYS, + size: CFG_PCIE2_MEM_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCIE2_IO_BASE, + phys_start: CFG_PCIE2_IO_PHYS, + size: CFG_PCIE2_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pcie_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *reg[] = { pci_regions_0, pci_regions_1 }; + extern void disable_addr_trans(void); /* start.S */ + + disable_addr_trans(); + + /* Configure the clock for PCIE controller */ + clk->sccr &= ~0x003C0000; + clk->sccr |= 0x00140000; + + /* Deassert the resets in the control register */ + sysconf->pecr1 = 0xE0008000; +#if !defined(CONFIG_PCIE_X2) + sysconf->pecr2 = 0xE0008000; +#endif + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + pcie_law[0].bar = CFG_PCIE1_BASE & LAWBAR_BAR; + pcie_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pcie_law[1].bar = CFG_PCIE2_BASE & LAWBAR_BAR; + pcie_law[1].ar = LBLAWAR_EN | LBLAWAR_512MB; + +#if defined(CONFIG_PCIE_X2) + mpc83xx_pcie_init(1, reg, 0); +#else + mpc83xx_pcie_init(2, reg, 0); +#endif +} diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 3b5d035..b628f38 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -31,8 +31,10 @@ #define CONFIG_MPC837XERDB 1 #define CONFIG_PCI 1 +#define CONFIG_PCIE 1 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R /* @@ -380,6 +382,32 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#ifdef CONFIG_PCIE +#define CONFIG_83XX_GENERIC_PCIE 1 /* Use generic PCIE setup*/ + +/* PCIE address map */ +#define CFG_PCIE1_BASE 0xA0000000 +#define CFG_PCIE1_MEM_BASE CFG_PCIE1_BASE +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x10000000 +#define CFG_PCIE1_CFG_BASE (CFG_PCIE1_MEM_BASE + CFG_PCIE1_MEM_SIZE) +#define CFG_PCIE1_CFG_SIZE 0x01000000 +#define CFG_PCIE1_IO_BASE 0x0 +#define CFG_PCIE1_IO_PHYS (CFG_PCIE1_CFG_BASE + CFG_PCIE1_CFG_SIZE) +#define CFG_PCIE1_IO_SIZE 0x00800000 + +#define CFG_PCIE2_BASE 0xC0000000 +#define CFG_PCIE2_MEM_BASE CFG_PCIE2_BASE +#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE +#define CFG_PCIE2_MEM_SIZE 0x10000000 +#define CFG_PCIE2_CFG_BASE (CFG_PCIE2_MEM_BASE + CFG_PCIE2_MEM_SIZE) +#define CFG_PCIE2_CFG_SIZE 0x01000000 +#define CFG_PCIE2_IO_BASE 0x0 +#define CFG_PCIE2_IO_PHYS (CFG_PCIE2_CFG_BASE + CFG_PCIE2_CFG_SIZE) +#define CFG_PCIE2_IO_SIZE 0x00800000 + +#endif /* CONFIG_PCIE */ #endif /* CONFIG_PCI */ /* -- 1.5.2.2

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[U-Boot-Users] [PATCH] lwmon5 SYSMON POST: fix handling of negative temperatures
by Wolfgang Denk 25 Mar '08

25 Mar '08

From: Yuri Tikhonov <yur(a)emcraft.com> Fix errors in the LWMON5 Sysmon POST for negative temperatures. Signed-off-by: Yuri Tikhonov <yur(a)emcraft.com> --- post/board/lwmon5/dspic.c | 27 ++++++++++++++------------- post/board/lwmon5/sysmon.c | 33 ++++++++++++++++++++++----------- 2 files changed, 36 insertions(+), 24 deletions(-) diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c index dbaa074..fcbbc60 100644 --- a/post/board/lwmon5/dspic.c +++ b/post/board/lwmon5/dspic.c @@ -59,25 +59,27 @@ int dspic_init_post_test(int flags) #if CONFIG_POST & CFG_POST_BSPEC2 /* Read a register from the dsPIC. */ -int dspic_read(ushort reg) +int dspic_read(ushort reg, ushort *data) { - uchar buf[2]; + uchar buf[sizeof(*data)]; + int rval; - if (i2c_read(CFG_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2)) - return -1; + rval = i2c_read(CFG_I2C_DSPIC_IO_ADDR, reg, sizeof(reg), + buf, sizeof(*data)); - return (uint)((buf[0] << 8) | buf[1]); + *data = (buf[0] << 8) | buf[1]; + + return rval; } /* Verify error codes regs, display version */ int dspic_post_test(int flags) { - int data; + ushort data; int ret = 0; post_log("\n"); - data = dspic_read(DSPIC_VERSION_REG); - if (data == -1) { + if (dspic_read(DSPIC_VERSION_REG, &data)) { post_log("dsPIC : failed read version\n"); ret = 1; } else { @@ -85,16 +87,15 @@ int dspic_post_test(int flags) (data >> 8) & 0xFF, data & 0xFF); } - data = dspic_read(DSPIC_POST_ERROR_REG); - if (data != 0) ret = 1; - if (data == -1) { + if (dspic_read(DSPIC_POST_ERROR_REG, &data)) { post_log("dsPIC : failed read POST code\n"); } else { post_log("dsPIC POST code 0x%04X\n", data); } + if (data != 0) + ret = 1; - data = dspic_read(DSPIC_SYS_ERROR_REG); - if (data == -1) { + if (dspic_read(DSPIC_SYS_ERROR_REG, &data)) { post_log("dsPIC : failed read system error\n"); ret = 1; } else if (data != 0) { diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index f7e51a3..b1b81c6 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -58,7 +58,7 @@ DECLARE_GLOBAL_DATA_PTR; /* from dspic.c */ -extern int dspic_read(ushort reg); +extern int dspic_read(ushort reg, ushort *data); #define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) @@ -67,6 +67,7 @@ typedef struct sysmon_table_s sysmon_table_t; static void sysmon_dspic_init (sysmon_t * this); static int sysmon_dspic_read (sysmon_t * this, uint addr); +static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr); static void sysmon_backlight_disable (sysmon_table_t * this); struct sysmon_s @@ -79,9 +80,13 @@ struct sysmon_s static sysmon_t sysmon_dspic = {CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read}; +static sysmon_t sysmon_dspic_sgn = + {CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read_sgn}; + static sysmon_t * sysmon_list[] = { &sysmon_dspic, + &sysmon_dspic_sgn, NULL }; @@ -109,17 +114,17 @@ struct sysmon_table_s static sysmon_table_t sysmon_table[] = { - {"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, + {"Temperature", " C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable, 1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0, 0x8000-30, 0x8000+80, 0, 0x12BC}, {"+ 5 V", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0, - 0x8000+4750, 0x8000+5250, 0, 0x12CA}, + 100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0, + 4750, 5250, 0, 0x12CA}, {"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0, - 0x8000+4750, 0x8000+5250, 0, 0x12C6}, + 100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0, + 4750, 5250, 0, 0x12C6}, }; static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); @@ -156,9 +161,7 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val) static char buf[32]; char *p, sign; int decimal, frac; - int unit_val; - - unit_val = + int unit_val = s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask; if (val == -1) @@ -194,10 +197,18 @@ static void sysmon_dspic_init (sysmon_t * this) static int sysmon_dspic_read (sysmon_t * this, uint addr) { - int res = dspic_read(addr); + ushort data; + + return (dspic_read(addr, &data)) ? -1 : data; +} + +static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr) +{ + ushort data; /* To fit into the table range we should add 0x8000 */ - return (res == -1) ? -1 : (res + 0x8000); + return (dspic_read(addr, &data)) ? -1 : + (signed short)data + 0x8000; } static void sysmon_backlight_disable (sysmon_table_t * this) -- 1.5.4.2

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[U-Boot-Users] [PATCH] Add brackets to if condition in tools/setlocalversion
by Tsi-Chung Liew 24 Mar '08

24 Mar '08

The long condition in the script causes all ColdFire platforms unable to compile correctly. By adding square brackets, all compile without error. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- tools/setlocalversion | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/setlocalversion b/tools/setlocalversion index 9bbdafd..2c27291 100755 --- a/tools/setlocalversion +++ b/tools/setlocalversion @@ -11,8 +11,8 @@ cd "${1:-.}" || usage # Check for git and a git repo. if head=`git rev-parse --verify HEAD 2>/dev/null`; then # Do we have an untagged version? - if git name-rev --tags HEAD | \ - grep -E '^HEAD[[:space:]]+(.*~[0-9]*|undefined)$' > /dev/null; then + if [git name-rev --tags HEAD | \ + grep -E '^HEAD[[:space:]]+(.*~[0-9]*|undefined)$' > /dev/null]; then git describe | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}' fi -- 1.5.4.1

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[U-Boot-Users] U-Boot 1.3.2 crashes after interrupt_init() on PPC405EP board
by Reto Stalder 24 Mar '08

24 Mar '08

Hi I'm setting up U-Boot 1.3.2 on a PowerPC 405EP based prototype board. The execution stops shortly after returning from 'interrupt_init()' on line 998 in 'lib_ppc/board.c'. When I comment out this function call or line 104 in 'ppc_lib/interrupts.c' (set_msr(get_msr() | MSR_EE) I get the U-Boot prompt. All interrupt sources are disabled in 'board_early_init_f' and should therefore not make problems (I hope at least, that I did it correctly): mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); mtdcr(uicpr, 0xF7FF7F00); /* set int polarities */ mtdcr(uictr, 0x00000000); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicvcr, 0x00000001); So my assumption is that the board crashes on the first occurance of the PIT interrupt, but I am not sure. Has anybody seen something similar and could give me a hint? Thank you in advance, Reto

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[U-Boot-Users] [PATCH 5/5] 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards
by Anton Vorontsov 24 Mar '08

24 Mar '08

This is primarily for the early console support. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- Rebased on top of today's u-boot-mpc83xx. include/configs/MPC837XERDB.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c2e7701..3b5d035 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -338,6 +338,7 @@ /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ -- 1.5.2.2

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[U-Boot-Users] [PATCH 4/5] 83xx: initialize serdes for MPC837XRDB boards
by Anton Vorontsov 24 Mar '08

24 Mar '08

On the MPC8377ERDB: 2 SATA and 2 PCI-E. On the MPC8378ERDB: 2 PCI-E On the MPC8379ERDB: 4 SATA Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- Rebased on top of today's u-boot-mpc83xx. board/freescale/mpc837xerdb/mpc837xerdb.c | 37 +++++++++++++++++++++++++++++ include/configs/MPC837XERDB.h | 6 ++++ 2 files changed, 43 insertions(+), 0 deletions(-) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index a3b20b8..d091538 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -15,6 +15,7 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd_sdram.h> #include <vsc7385.h> @@ -132,6 +133,42 @@ int checkboard(void) return 0; } +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + immap_t *immr = (immap_t *)CFG_IMMR; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (spridr >> 16) { + case SPR_8379E_REV10 >> 16: + case SPR_8379_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378E_REV10 >> 16: + case SPR_8378_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8377E_REV10 >> 16: + case SPR_8377_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + /* * Miscellaneous late-boot configurations * diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index e3cb3c7..c2e7701 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -32,6 +32,7 @@ #define CONFIG_PCI 1 +#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R /* @@ -323,6 +324,11 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 + /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER -- 1.5.2.2

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[U-Boot-Users] [PATCH 3/5] 83xx: serdes setup routines
by Anton Vorontsov 24 Mar '08

24 Mar '08

This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- Rebased on top of today's u-boot-mpc83xx. cpu/mpc83xx/Makefile | 1 + cpu/mpc83xx/serdes.c | 145 ++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/fsl_serdes.h | 21 ++++++ 3 files changed, 167 insertions(+), 0 deletions(-) create mode 100644 cpu/mpc83xx/serdes.c create mode 100644 include/asm-ppc/fsl_serdes.h diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 7ad7e3e..fcb6a52 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -37,6 +37,7 @@ COBJS-y += interrupts.o COBJS-y += spd_sdram.o COBJS-y += ecc.o COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_FSL_SERDES) += serdes.o COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c new file mode 100644 index 0000000..020c4c8 --- /dev/null +++ b/cpu/mpc83xx/serdes.c @@ -0,0 +1,145 @@ +/* + * Freescale SerDes initialization routine + * + * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved. + * + * Author: Li Yang <leoli(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> + +/* SerDes registers */ +#define FSL_SRDSCR0_OFFS 0x0 +#define FSL_SRDSCR0_DPP_1V2 0x00008800 +#define FSL_SRDSCR1_OFFS 0x4 +#define FSL_SRDSCR1_PLLBW 0x00000040 +#define FSL_SRDSCR2_OFFS 0x8 +#define FSL_SRDSCR2_VDD_1V2 0x00800000 +#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c +#define FSL_SRDSCR2_SEIC_SATA 0x00001414 +#define FSL_SRDSCR2_SEIC_PEX 0x00001010 +#define FSL_SRDSCR2_SEIC_SGMII 0x00000101 +#define FSL_SRDSCR3_OFFS 0xc +#define FSL_SRDSCR3_KFR_SATA 0x10100000 +#define FSL_SRDSCR3_KPH_SATA 0x04040000 +#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 +#define FSL_SRDSCR3_SDTXL_SATA 0x00000505 +#define FSL_SRDSCR4_OFFS 0x10 +#define FSL_SRDSCR4_PROT_SATA 0x00000808 +#define FSL_SRDSCR4_PROT_PEX 0x00000101 +#define FSL_SRDSCR4_PROT_SGMII 0x00000505 +#define FSL_SRDSCR4_PLANE_X2 0x01000000 +#define FSL_SRDSRSTCTL_OFFS 0x20 +#define FSL_SRDSRSTCTL_RST 0x80000000 +#define FSL_SRDSRSTCTL_SATA_RESET 0xf + +void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) +{ + void *regs = (void *)CFG_IMMR + offset; + u32 tmp; + + /* 1.0V corevdd */ + if (vdd) { + /* DPPE/DPPA = 0 */ + tmp = in_be32(regs + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_DPP_1V2; + out_be32(regs + FSL_SRDSCR0_OFFS, tmp); + + /* VDD = 0 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_VDD_1V2; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + } + + /* protocol specific configuration */ + switch (proto) { + case FSL_SERDES_PROTO_SATA: + /* Set and clear reset bits */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + udelay(1000); + tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SATA; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | + FSL_SRDSCR3_SDFM_SATA_PEX | + FSL_SRDSCR3_SDTXL_SATA; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SATA; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_PEX: + case FSL_SERDES_PROTO_PEX_X2: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp |= FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_PEX; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_SDFM_SATA_PEX; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_PEX; + if (proto == FSL_SERDES_PROTO_PEX_X2) + tmp |= FSL_SRDSCR4_PLANE_X2; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_SGMII: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SGMII; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + out_be32(regs + FSL_SRDSCR3_OFFS, 0); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + default: + return; + } + + /* Do a software reset */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_RST; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); +} diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h new file mode 100644 index 0000000..733f919 --- /dev/null +++ b/include/asm-ppc/fsl_serdes.h @@ -0,0 +1,21 @@ +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include <config.h> + +#define FSL_SERDES_CLK_100 0 +#define FSL_SERDES_CLK_125 1 +#define FSL_SERDES_CLK_150 3 +#define FSL_SERDES_PROTO_SATA 0 +#define FSL_SERDES_PROTO_PEX 1 +#define FSL_SERDES_PROTO_PEX_X2 2 +#define FSL_SERDES_PROTO_SGMII 3 +#define FSL_SERDES_VDD_1V 1 + +#ifdef CONFIG_FSL_SERDES +extern void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd); +#else +static void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) {} +#endif /* CONFIG_FSL_SERDES */ + +#endif /* __FSL_SERDES_H */ -- 1.5.2.2

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[U-Boot-Users] [PATCH 2/5] 83xx: split COBJS onto separate lines
by Anton Vorontsov 24 Mar '08

24 Mar '08

..plus get rid of some #ifdefs in the .c files. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- Rebased on top of today's u-boot-mpc83xx. cpu/mpc83xx/Makefile | 14 ++++++++++++-- cpu/mpc83xx/fdt.c | 4 ---- cpu/mpc83xx/pci.c | 2 -- cpu/mpc83xx/qe_io.c | 3 --- 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 94a3cb8..7ad7e3e 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -28,9 +28,19 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o ecc.o qe_io.o pci.o fdt.o +COBJS-y += traps.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += speed.o +COBJS-y += interrupts.o +COBJS-y += spd_sdram.o +COBJS-y += ecc.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + +COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 6f55932..d3fd78e 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -24,9 +24,6 @@ */ #include <common.h> - -#if defined(CONFIG_OF_LIBFDT) - #include <libfdt.h> #include <fdt_support.h> @@ -68,4 +65,3 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 18558db..adabf7a 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -33,7 +33,6 @@ #include <asm/mpc8349_pci.h> -#ifdef CONFIG_83XX_GENERIC_PCI #define MAX_BUSES 2 DECLARE_GLOBAL_DATA_PTR; @@ -209,4 +208,3 @@ void ft_pci_setup(void *blob, bd_t *bd) } } #endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_83XX_GENERIC_PCI */ diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index 8b3937a..ce91a07 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -25,7 +25,6 @@ #include "asm/io.h" #include "asm/immap_83xx.h" -#if defined(CONFIG_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { @@ -81,5 +80,3 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); } } - -#endif /* CONFIG_QE */ -- 1.5.2.2

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