March 2008 - U-Boot

[U-Boot-Users] Identify an U-boot compilation
by Luigi 'Comio' Mantellini 24 Mar '08

24 Mar '08

Hi All, Is there a symbol (like __U_BOO_T__) that is defined during U-Boot compilation and that I can test into my .c/.h source files? I have a self-made library that is shared between the bootloader and the linux kernel. Obviously the source paths and includes are different in the two environment and I need to choose the correct code on the basis of the target enviroment. In the linux kernel I can use symbol like "__LINUX__" to understand that the actual compilation is referred to the Linux Kernel... but I don't find an similar symbol define in U-Boot. I would write code like: ... #if defined(__U_BOOT__) /* U-boot specific code */ ... #elsif defined(__LINUX__) /*Kernel specific code */ #endif ... Is there a similar mechanism in U-BOOT building infrastructure? (anyway, can we insert a -D__U_BOOT__ in the compiler invocation?) Thanks a lot, luigi -- ______ Luigi Mantellini .'______'. R&D - Software (.' '.) Industrie Dial Face S.p.A. ( :=----=: ) Via Canzo, 4 ('.______.') 20068 Peschiera Borromeo (MI), Italy '.______.' Tel.: +39 02 5167 2813 Fax: +39 02 5167 2459 Ind. Dial Face Email: luigi.mantellini(a)idf-hit.com www.idf-hit.com GPG fingerprint: 3DD1 7B71 FBDF 6376 1B4A B003 175F E979 907E 1650

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[U-Boot-Users] [PATCH] sh: Add support Renesas Solutions R2D plus board
by Nobuhiro Iwamatsu 24 Mar '08

24 Mar '08

R2D plus is SH reference board used with SH7751R. This board has 266Mhz CPU, 64MB SDRAM, Cardbus, CF interface, one PCI bus, VGA, and two Ethernet controller. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 5 ++ board/r2dplus/Makefile | 43 +++++++++++ board/r2dplus/config.mk | 23 ++++++ board/r2dplus/lowlevel_init.S | 154 +++++++++++++++++++++++++++++++++++++++++ board/r2dplus/r2dplus.c | 76 ++++++++++++++++++++ board/r2dplus/u-boot.lds | 105 ++++++++++++++++++++++++++++ include/configs/r2dplus.h | 151 ++++++++++++++++++++++++++++++++++++++++ 9 files changed, 559 insertions(+), 0 deletions(-) create mode 100644 board/r2dplus/Makefile create mode 100644 board/r2dplus/config.mk create mode 100644 board/r2dplus/lowlevel_init.S create mode 100644 board/r2dplus/r2dplus.c create mode 100644 board/r2dplus/u-boot.lds create mode 100644 include/configs/r2dplus.h diff --git a/MAINTAINERS b/MAINTAINERS index 5add085..4e4c358 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -696,6 +696,7 @@ Nobuhiro Iwmaatsu <iwamatsu(a)nigauri.org> MS7750SE SH7750 MS7722SE SH7722 + R2DPlus SH7751R Mark Jonas <mark.jonas(a)de.bosch.com> diff --git a/MAKEALL b/MAKEALL index 7668aee..97f91cb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -698,6 +698,7 @@ LIST_sh4=" \ ms7722se \ Migo-R \ r7780mp \ + r2dplus \ " LIST_sh3=" \ diff --git a/Makefile b/Makefile index 62b5d2e..1cc6c84 100644 --- a/Makefile +++ b/Makefile @@ -2850,6 +2850,11 @@ r7780mp_config: unconfig @echo "#define CONFIG_R7780MP 1" >> include/config.h @./mkconfig -a $(@:_config=) sh sh4 r7780mp +r2dplus_config : unconfig + @ >include/config.h + @echo "#define CONFIG_R2DPLUS 1" >> include/config.h + @./mkconfig -a $(@:_config=) sh sh4 r2dplus + ######################################################################### ######################################################################### ######################################################################### diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile new file mode 100644 index 0000000..ed609ea --- /dev/null +++ b/board/r2dplus/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := r2dplus.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +################################################################# + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +################################################################# diff --git a/board/r2dplus/config.mk b/board/r2dplus/config.mk new file mode 100644 index 0000000..1ec7dcc --- /dev/null +++ b/board/r2dplus/config.mk @@ -0,0 +1,23 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +TEXT_BASE = 0x0FFC0000 diff --git a/board/r2dplus/lowlevel_init.S b/board/r2dplus/lowlevel_init.S new file mode 100644 index 0000000..5755de8 --- /dev/null +++ b/board/r2dplus/lowlevel_init.S @@ -0,0 +1,154 @@ +/* + * modified from SH-IPL+g (init-r0p751rlc0011rl.S) + * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) + * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> +*/ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> + + .global lowlevel_init + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 + mov.l CCR_D_D, r0 + mov.l r0,@r1 + + mov.l MMUCR_A,r1 + mov.l MMUCR_D,r0 + mov.w r0,@r1 + + mov.l BCR1_A,r1 + mov.l BCR1_D,r0 + mov.l r0,@r1 + + mov.l BCR2_A,r1 + mov.l BCR2_D,r0 + mov.w r0,@r1 + + mov.l BCR3_A,r1 + mov.l BCR3_D,r0 + mov.w r0,@r1 + + mov.l BCR4_A,r1 + mov.l BCR4_D,r0 + mov.l r0,@r1 + + mov.l WCR1_A,r1 + mov.l WCR1_D,r0 + mov.l r0,@r1 + + mov.l WCR2_A,r1 + mov.l WCR2_D,r0 + mov.l r0,@r1 + + mov.l WCR3_A,r1 + mov.l WCR3_D,r0 + mov.l r0,@r1 + + mov.l PCR_A,r1 + mov.l PCR_D,r0 + mov.w r0,@r1 + + mov.l LED_A,r1 + mov #0xff,r0 + mov.w r0,@r1 + + mov.l MCR_A,r1 + mov.l MCR_D1,r0 + mov.l r0,@r1 + + mov.l RTCNT_A,r1 + mov.l RTCNT_D,r0 + mov.w r0,@r1 + + mov.l RTCOR_A,r1 + mov.l RTCOR_D,r0 + mov.w r0,@r1 + + mov.l RFCR_A,r1 + mov.l RFCR_D,r0 + mov.w r0,@r1 + + mov.l RTCSR_A,r1 + mov.l RTCSR_D,r0 + mov.w r0,@r1 + + mov.l SDMR3_A,r1 + mov #0x55,r0 + mov.b r0,@r1 + + /* Wait DRAM refresh 30 times */ + mov.l RFCR_A,r1 + mov #30,r3 +1: + mov.w @r1,r0 + extu.w r0,r2 + cmp/hi r3,r2 + bf 1b + + mov.l MCR_A,r1 + mov.l MCR_D2,r0 + mov.l r0,@r1 + + mov.l SDMR3_A,r1 + mov #0,r0 + mov.b r0,@r1 + + mov.l IRLMASK_A,r1 + mov.l IRLMASK_D,r0 + mov.l r0,@r1 + + mov.l CCR_A, r1 + mov.l CCR_D_E, r0 + mov.l r0, @r1 + + rts + nop + + .align 2 +CCR_A: .long CCR /* Cache Control Register */ +CCR_D_D: .long 0x0808 /* Flush the cache, disable */ +CCR_D_E: .long 0x8000090B + +FRQCR_A: .long FRQCR /* FRQCR Address */ +FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ +BCR1_A: .long BCR1 /* BCR1 Address */ +BCR1_D: .long 0x00180008 +BCR2_A: .long BCR2 /* BCR2 Address */ +BCR2_D: .long 0xabe8 +BCR3_A: .long BCR3 /* BCR3 Address */ +BCR3_D: .long 0x0000 +BCR4_A: .long BCR4 /* BCR4 Address */ +BCR4_D: .long 0x00000010 +WCR1_A: .long WCR1 /* WCR1 Address */ +WCR1_D: .long 0x33343333 +WCR2_A: .long WCR2 /* WCR2 Address */ +WCR2_D: .long 0xcff86fbf +WCR3_A: .long WCR3 /* WCR3 Address */ +WCR3_D: .long 0x07777707 +LED_A: .long 0x04000036 /* LED Address */ +RTCNT_A: .long RTCNT /* RTCNT Address */ +RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCOR_A: .long RTCOR /* RTCOR Address */ +RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCSR_A: .long RTCSR /* RTCSR Address */ +RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ +SDMR3_D: .long 0x55 +MCR_A: .long MCR /* MCR Address */ +MCR_D1: .long 0x081901F4 /* MRSET:'0' */ +MCR_D2: .long 0x481901F4 /* MRSET:'1' */ +RFCR_A: .long RFCR /* RFCR Address */ +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +PCR_A: .long PCR /* PCR Address */ +PCR_D: .long 0x0000 +MMUCR_A: .long MMUCR /* MMUCCR Address */ +MMUCR_D: .long 0x00000000 /* MMUCCR Data */ +IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ +IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c new file mode 100644 index 0000000..2ee3ea2 --- /dev/null +++ b/board/r2dplus/r2dplus.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ide.h> +#include <asm/processor.h> +#include <asm/pci.h> + +int checkboard(void) +{ + puts("BOARD: Renesas Solutions R2D Plus\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +#define FPGA_BASE 0xA4000000 +#define FPGA_CFCTL (FPGA_BASE + 0x04) +#define FPGA_CFPOW (FPGA_BASE + 0x06) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) + +void ide_set_reset (int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset){ + (*(vu_short *)FPGA_CFCTL) = 0x432; + (*(vu_short *)FPGA_CFPOW) |= 0x02; + (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + } +} + +#if defined(CONFIG_PCI) +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7751_init( &hose ); +} +#endif /* CONFIG_PCI */ diff --git a/board/r2dplus/u-boot.lds b/board/r2dplus/u-boot.lds new file mode 100644 index 0000000..96d8d81 --- /dev/null +++ b/board/r2dplus/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x0C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h new file mode 100644 index 0000000..6107685 --- /dev/null +++ b/include/configs/r2dplus.h @@ -0,0 +1,151 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7751 1 +#define CONFIG_CPU_SH_TYPE_R 1 +#define CONFIG_R2DPLUS 1 +/* OLD type R2D plus support*/ +/* #define CONFIG_R2DPLUS_OLD 1 */ +#define __LITTLE_ENDIAN__ 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DFL +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_SCIF1 1 +#define BOARD_LATE_INIT 1 + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_ENV_OVERWRITE 1 + +/* Network setting */ +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_IPADDR 10.0.192.51 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_GATEWAYIP 10.0.0.1 + +/* SDRAM */ +#define CFG_SDRAM_BASE (0x8C000000) +#define CFG_SDRAM_SIZE (0x04000000) + +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } + +#define CFG_MEMTEST_START (CFG_SDRAM_BASE) +#define CFG_MEMTEST_END (TEXT_BASE - 0x100000) + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) +/* Address of u-boot image in Flash */ +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ + +#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* + * NOR Flash + */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER + +#if defined(CONFIG_R2DPLUS_OLD) +#define CFG_FLASH_BASE (0xA0000000) +#define CFG_MAX_FLASH_BANKS (1) /* Max number of + * Flash memory banks + */ +#define CFG_MAX_FLASH_SECT 142 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#else /* CONFIG_R2DPLUS_OLD */ + +#define CFG_FLASH_BASE (0xA0000000) +#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */ +#define CFG_MAX_FLASH_BANKS (2) +#define CFG_MAX_FLASH_SECT 270 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ + CFG_FLASH_BASE + 0x100000,\ + CFG_FLASH_BASE + 0x400000,\ + CFG_FLASH_BASE + 0x700000, } +#endif /* CONFIG_R2DPLUS_OLD */ + +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +/* + * SuperH Clock setting + */ +#define CONFIG_SYS_CLK_FREQ 60000000 +#define TMU_CLK_DIVIDER 4 +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) +#define CFG_PLL_SETTLING_TIME 100 /* in us */ + +/* + * IDE support + */ +#define CONFIG_IDE_RESET 1 +#define CFG_PIO_MODE 1 +#define CFG_IDE_MAXBUS 1 /* IDE bus */ +#define CFG_IDE_MAXDEVICE 1 +#define CFG_ATA_BASE_ADDR 0xb4000000 +#define CFG_ATA_STRIDE 2 /* 1bit shift */ +#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */ + +/* + * SuperH PCI Bridge Configration + */ +#define CONFIG_PCI +#define CONFIG_SH4_PCI +#define CONFIG_SH7751_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW 1 +#define __io +#define __mem_pci + +#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ +#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ + +/* + * Network device (RTL8139) support + */ +#define CONFIG_NET_MULTI +#define CONFIG_RTL8139 +#define _IO_BASE 0x00000000 +#define KSEG1ADDR(x) (x) + +#endif /* __CONFIG_H */ -- 1.5.4.3

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[U-Boot-Users] [RFC][MIPS] Remove mips_cache_lock
by Shinya Kuribayashi 24 Mar '08

24 Mar '08

I don't know the background why this lock added. So if I miss something, please let me know. Or I'll push this before merge window close(). ========> I don't see any reason why we have to lock cache line here. Maybe some targets require this locking, but that's completely target specific re- quirement and we should not have such things in global start codes. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/cache.S | 26 -------------------------- cpu/mips/start.S | 5 ----- 2 files changed, 0 insertions(+), 31 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 443240e..9d793bf 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -237,29 +237,3 @@ dcache_disable: j ra .end dcache_disable - -/******************************************************************************* -* -* mips_cache_lock - lock RAM area pointed to by a0 in cache. -* -* RETURNS: N/A -* -*/ -#if defined(CONFIG_PURPLE) -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2) -#else -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE) -#endif - .globl mips_cache_lock - .ent mips_cache_lock -mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE - addu a0, a1 - li a2, CACHE_LOCK_SIZE - li a3, CFG_CACHELINE_SIZE - move a1, a2 - icacheop(a0,a1,a2,a3,0x1d) - - j ra - - .end mips_cache_lock diff --git a/cpu/mips/start.S b/cpu/mips/start.S index c92b162..fd44da0 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -267,11 +267,6 @@ reset: /* Set up temporary stack. */ - li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalr t9 - nop - li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET la sp, 0(t0)

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[U-Boot-Users] NAND bad blocks scan unacceptable slow
by Nikita V. Youshchenko 23 Mar '08

23 Mar '08

Hello. I'm working on a board that has a 256-megabyte NAND chip connected to cpu GPIO interface. I wrote some code that provide hardware access methods for struct nand_chip, and then u-boot recognized the NAND chip, and read/write/erase worked. However, on-boot scan for bad blocks takes up to 20 seconds, which is unacceptable slow. Linux kernel scans for bad blocks on the same board, using almost same code to access hardware, almost immediately. I was able to fix this using a patch included below. However, this all looks ugly. Look in nand_read_raw() in drivers/mtd/nand/nand_base.c: int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen) { ... int pagesize = mtd->oobblock + mtd->oobsize; ... len += ooblen; while (len) { ... len -= pagesize; ... } } So, if len is not mtd->oobblock or ooblen is not mtd->oobsize, the loop most likely won't terminate. And of course all usages of nand_read_raw use exactly these parameters. How to deal with this? Nikita P.S. The patch I used against slow bad block scan: commit 9f09001529526e07ebb6e65a33baa4995198851c Author: Nikita Youshchenko <yoush(a)cs.msu.su> Date: Fri Mar 21 21:08:06 2008 +0000 nand: when scanning for bad blocks, read only oob area of nand flash This patch adds one more parameter to nand_read_raw(), which, when non-zero, causes it to read oob area only. It also renames nand_read_raw() to nand_read_raw_ext(), and provides a wrapper nand_read_raw() that calls nand_read_raw_ext() with extra parameter set to zero. It also makes bad block scan routine to call nand_read_raw_ext(), if it is going to check oob area only. This makes scanning for bad blocks 100 times faster. Signed-off-by: Nikita Youshchenko <yoush(a)cs.msu.su> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 151f535..ed93a20 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1468,7 +1468,7 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * * Read raw data including oob into buffer */ -int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen) +int nand_read_raw_ext (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen, int oob_only) { struct nand_chip *this = mtd->priv; int page = (int) (from >> this->page_shift); @@ -1477,6 +1477,7 @@ int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, int cnt = 0; int pagesize = mtd->oobblock + mtd->oobsize; int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + int column; /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { @@ -1493,11 +1494,19 @@ int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, len += ooblen; while (len) { + if (oob_only) + column = mtd->oobblock; + else + column = 0; + if (sndcmd) - this->cmdfunc (mtd, NAND_CMD_READ0, 0, page & this->pagemask); + this->cmdfunc (mtd, NAND_CMD_READ0, column, page & this->pagemask); sndcmd = 0; - this->read_buf (mtd, &buf[cnt], pagesize); + if (oob_only) + this->read_buf (mtd, &buf[cnt + mtd->oobblock], ooblen); + else + this->read_buf (mtd, &buf[cnt], pagesize); len -= pagesize; cnt += pagesize; @@ -1518,6 +1527,10 @@ int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, return 0; } +int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen) +{ + return nand_read_raw_ext(mtd, buf, from, len, ooblen, 0); +} /** * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 19a9bc2..fcac13f 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -292,7 +292,10 @@ static void create_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc } for (i = startblock; i < numblocks;) { - nand_read_raw (mtd, buf, from, readlen, ooblen); + if (bd->options & NAND_BBT_SCANEMPTY) + nand_read_raw (mtd, buf, from, readlen, ooblen); + else + nand_read_raw_ext (mtd, buf, from, readlen, ooblen, 1); for (j = 0; j < len; j++) { if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) { this->bbt[i >> 3] |= 0x03 << (i & 0x6); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4cc4a7d..fe7fd9a 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -63,6 +63,7 @@ extern void nand_release (struct mtd_info *mtd); /* Read raw data from the device without ECC */ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); +extern int nand_read_raw_ext (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen, int oob_only); /* This constant declares the max. oobsize / page, which

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[U-Boot-Users] (no subject)
by 钟文辉 23 Mar '08

23 Mar '08

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[U-Boot-Users] Doctors Recommend This
by df Ken 23 Mar '08

23 Mar '08

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[U-Boot-Users] [PATCH] sh: Remove a warning when compiling drivers/serial/serial_sh.c
by Mark Jonas 23 Mar '08

23 Mar '08

Hello, The attached patch removes a warning when compiling drivers/serial/serial_sh.c. Regards, Mark Jonas CHANGELOG: ---------- sh: Removed warning when compiling drivers/serial/serial_sh.c. Signed-off-by: Mark Jonas <mark.jonas(a)de.bosch.com>

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[U-Boot-Users] [PATCH v2] sh: Add support PCI host driver for SH7751/SH7751R
by Nobuhiro Iwamatsu 23 Mar '08

23 Mar '08

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/pci/Makefile | 1 + drivers/pci/pci_sh7751.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++ include/asm-sh/pci.h | 7 +- 3 files changed, 204 insertions(+), 3 deletions(-) create mode 100644 drivers/pci/pci_sh7751.c diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index ef7781f..ad1b7dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -32,6 +32,7 @@ COBJS-y += pci_indirect.o COBJS-y += tsi108_pci.o COBJS-y += w83c553f.o COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o +COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o COBJS := $(COBJS-y) diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c new file mode 100644 index 0000000..13b2193 --- /dev/null +++ b/drivers/pci/pci_sh7751.c @@ -0,0 +1,199 @@ +/* + * SH7751 PCI Controller (PCIC) for U-Boot. + * (C) Dustin McIntire (dustin(a)sensoria.com) + * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <pci.h> + +/* Register addresses and such */ +#define SH7751_BCR (vu_long *)0xFF800000 +#define SH7751_BCR2 (vu_short*)0xFF800004 +#define SH7751_WCR1 (vu_long *)0xFF800008 +#define SH7751_WCR2 (vu_long *)0xFF80000C +#define SH7751_WCR3 (vu_long *)0xFF800010 +#define SH7751_MCR (vu_long *)0xFF800014 +#define SH7751_BCR3 (vu_short*)0xFF800050 +#define SH7751_PCICONF0 (vu_long *)0xFE200000 +#define SH7751_PCICONF1 (vu_long *)0xFE200004 +#define SH7751_PCICONF2 (vu_long *)0xFE200008 +#define SH7751_PCICONF3 (vu_long *)0xFE20000C +#define SH7751_PCICONF4 (vu_long *)0xFE200010 +#define SH7751_PCICONF5 (vu_long *)0xFE200014 +#define SH7751_PCICONF6 (vu_long *)0xFE200018 +#define SH7751_PCICR (vu_long *)0xFE200100 +#define SH7751_PCILSR0 (vu_long *)0xFE200104 +#define SH7751_PCILSR1 (vu_long *)0xFE200108 +#define SH7751_PCILAR0 (vu_long *)0xFE20010C +#define SH7751_PCILAR1 (vu_long *)0xFE200110 +#define SH7751_PCIMBR (vu_long *)0xFE2001C4 +#define SH7751_PCIIOBR (vu_long *)0xFE2001C8 +#define SH7751_PCIPINT (vu_long *)0xFE2001CC +#define SH7751_PCIPINTM (vu_long *)0xFE2001D0 +#define SH7751_PCICLKR (vu_long *)0xFE2001D4 +#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0 +#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4 +#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8 +#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC +#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0 +#define SH7751_PCIMCR (vu_long *)0xFE2001F4 +#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8 + +#define BCR1_BREQEN 0x00080000 +#define PCI_SH7751_ID 0x35051054 +#define PCI_SH7751R_ID 0x350E1054 +#define SH7751_PCICONF1_WCC 0x00000080 +#define SH7751_PCICONF1_PER 0x00000040 +#define SH7751_PCICONF1_BUM 0x00000004 +#define SH7751_PCICONF1_MES 0x00000002 +#define SH7751_PCICONF1_CMDS 0x000000C6 +#define SH7751_PCI_HOST_BRIDGE 0x6 +#define SH7751_PCICR_PREFIX 0xa5000000 +#define SH7751_PCICR_PRST 0x00000002 +#define SH7751_PCICR_CFIN 0x00000001 +#define SH7751_PCIPINT_D3 0x00000002 +#define SH7751_PCIPINT_D0 0x00000001 +#define SH7751_PCICLKR_PREFIX 0xa5000000 + +#define SH7751_PCI_MEM_BASE 0xFD000000 +#define SH7751_PCI_MEM_SIZE 0x01000000 +#define SH7751_PCI_IO_BASE 0xFE240000 +#define SH7751_PCI_IO_SIZE 0x00040000 + +#define SH7751_CS3_BASE_ADDR 0x0C000000 +#define SH7751_P2CS3_BASE_ADDR 0xAC000000 + +#define SH7751_PCIPAR (vu_long *)0xFE2001C0 +#define SH7751_PCIPDR (vu_long *)0xFE200220 + +#define p4_in(addr) *(addr) +#define p4_out(data,addr) *(addr) = (data) + +/* Double word */ +int pci_sh4_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + u32 par_data = 0x80000000 | dev; + + p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR); + *value = p4_in(SH7751_PCIPDR); + + return 0; +} + +int pci_sh4_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + u32 par_data = 0x80000000 | dev; + + p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR); + p4_out(value, SH7751_PCIPDR); + + return 0; +} + +int pci_sh7751_init(struct pci_controller *hose) +{ + /* Double-check that we're a 7751 or 7751R chip */ + if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID + && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) { + printf("PCI: Unknown PCI host bridge.\n"); + return 1; + } + printf("PCI: SH7751 PCI host bridge found.\n"); + + /* Double-check some BSC config settings */ + /* (Area 3 non-MPX 32-bit, PCI bus pins) */ + if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) { + printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1)); + return 2; + } + if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) { + printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2)); + return 3; + } + if (p4_in(SH7751_BCR2) & 0x01) { + printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2)); + return 4; + } + + /* Force BREQEN in BCR1 to allow PCIC access */ + p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1); + + /* Toggle PCI reset pin */ + p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR); + udelay(32); + p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR); + + /* Set cmd bits: WCC, PER, BUM, MES */ + /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */ + p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */ + + /* Define this host as the host bridge */ + p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2); + + /* Force PCI clock(s) on */ + p4_out(0, SH7751_PCICLKR); + p4_out(0x03, SH7751_PCICLKR); + + /* Clear powerdown IRQs, also mask them (unused) */ + p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT); + p4_out(0, SH7751_PCIPINTM); + + p4_out(0xab000001, SH7751_PCICONF4); + + /* Set up target memory mappings (for external DMA access) */ + /* Map both P0 and P2 range to Area 3 RAM for ease of use */ + p4_out((64 - 1) << 20, SH7751_PCILSR0); + p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0); + p4_out(0, SH7751_PCILSR1); + p4_out(0, SH7751_PCILAR1); + p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5); + p4_out(0xd0000000, SH7751_PCICONF6); + + /* Map memory window to same address on PCI bus */ + p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR); + + /* Map IO window to same address on PCI bus */ + p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR); + + /* set BREQEN */ + p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1); + + /* Copy BSC registers into PCI BSC */ + p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1); + p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2); + p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3); + p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1); + p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2); + p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3); + p4_out(inl(SH7751_MCR), SH7751_PCIMCR); + + /* Finally, set central function init complete */ + p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR); + + pci_sh4_init(hose); + + return 0; +} diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h index 821961f..bc59491 100644 --- a/include/asm-sh/pci.h +++ b/include/asm-sh/pci.h @@ -1,7 +1,7 @@ /* * SH4 PCI Controller (PCIC) for U-Boot. * (C) Dustin McIntire (dustin(a)sensoria.com) - * (C) 2007 Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> + * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> * (C) 2008 Yusuke Goda <goda.yusuke(a)renesas.com> * * u-boot/include/asm-sh/pci.h @@ -28,8 +28,9 @@ #define _ASM_PCI_H_ #include <pci.h> - -#if defined(CONFIG_CPU_SH7780) +#if defined(CONFIG_SH7751_PCI) +int pci_sh7751_init(struct pci_controller *hose); +#elif defined(CONFIG_SH7780_PCI) int pci_sh7780_init(struct pci_controller *hose); #else #error "Not support PCI." -- 1.5.4.3

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[U-Boot-Users] [PATCH] sh: Remove disable_ctrlc function from R7780MP
by Nobuhiro Iwamatsu 23 Mar '08

23 Mar '08

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- board/r7780mp/r7780mp.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c index 1e0f536..1a37711 100644 --- a/board/r7780mp/r7780mp.c +++ b/board/r7780mp/r7780mp.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> * Copyright (C) 2008 Yusuke Goda <goda.yusuke(a)renesas.com> * * This program is free software; you can redistribute it and/or @@ -40,9 +40,6 @@ int board_init(void) /* SCIF Enable */ *(vu_short*)PHCR = 0x0000; - /* Disable Control-C */ - disable_ctrlc(1); - return 0; } -- 1.5.4.3

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[U-Boot-Users] [PATCH] sh: Add maintainer of R7780MP to MAINTAINER file
by Nobuhiro Iwamatsu 23 Mar '08

23 Mar '08

Update MAINTAINER entry for R7780MP. And fix maintainer's name. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- MAINTAINERS | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4e4c358..3084872 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -692,10 +692,11 @@ Haavard Skinnemoen <hskinnemoen(a)atmel.com> # Board CPU # ######################################################################### -Nobuhiro Iwmaatsu <iwamatsu(a)nigauri.org> +Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> MS7750SE SH7750 MS7722SE SH7722 + R7780MP SH7780 R2DPlus SH7751R Mark Jonas <mark.jonas(a)de.bosch.com> -- 1.5.4.3

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