October 2008 - U-Boot

[U-Boot] [PATCH] Add IC Ident. Module (IIM) support for ADS5121
by Martha Marx 08 Oct '08

08 Oct '08

IIM (IC Identification Module) is the fusebox for the mpc5121. Use #define CONFIG_IIM to turn on the clock for this module, use #define CONFIG_CMD_FUSE to add fusebox commands. Fusebox commands include the ability to read the status, read the register cache, override the register cache, program the fuses and sense them. Signed-off-by: Martha Marx <mmarx(a)silicontkx.com> --- board/ads5121/Makefile | 1 + board/ads5121/ads5121.c | 3 + board/ads5121/ads5121_iim.c | 367 ++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_512x.h | 20 +++- include/configs/ads5121.h | 6 + include/mpc512x.h | 25 +++ 6 files changed, 421 insertions(+), 1 deletions(-) create mode 100644 board/ads5121/ads5121_iim.c diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index 52d0d3c..125ac60 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -32,6 +32,7 @@ COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_IIM) += ads5121_iim.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index deaa292..4198826 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -101,6 +101,9 @@ int board_early_init_f (void) */ im->clk.sccr[0] = SCCR1_CLOCKS_EN; im->clk.sccr[1] = SCCR2_CLOCKS_EN; +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) + im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN; +#endif return 0; } diff --git a/board/ads5121/ads5121_iim.c b/board/ads5121/ads5121_iim.c new file mode 100644 index 0000000..2dd2493 --- /dev/null +++ b/board/ads5121/ads5121_iim.c @@ -0,0 +1,367 @@ +/* + * Copyright 2008 Silicon Turnkey Express, Inc. + * Martha Marx <mmarx(a)silicontkx.com> + * + * ADS5121 IIM (Fusebox) Interface + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#ifdef CONFIG_CMD_FUSE + +DECLARE_GLOBAL_DATA_PTR; + +static char cur_bank = '1'; + +char *iim_err_msg(u32 err) +{ + static char *IIM_errs[] = { + "Parity Error in cache", + "Explicit Sense Cycle Error", + "Write to Locked Register Error", + "Read Protect Error", + "Override Protect Error", + "Write Protect Error"}; + + int i; + + if (!err) + return ""; + for (i = 1; i < 8; i++) + if (err & (1 << i)) + printf("IIM - %s\n", IIM_errs[i-1]); + return ""; +} + +int ads5121_fuse_read(int bank, int fstart, int num) +{ + volatile iim512x_t *iim = &((immap_t *) CFG_IMMR)->iim; + u32 *iim_fb, dummy; + int f, ctr; + + if (bank == 0) + iim_fb = (u32 *)&(iim->fbac0); + else + iim_fb = (u32 *)&(iim->fbac1); +/* try a read to see if Read Protect is set */ + dummy = iim_fb[0]; + if (iim->err & IIM_ERR_RPE) { + printf("\tRead protect fuse is set\n"); + iim->err = 0; + return 0; + } + printf("Reading Bank %d cache\n", bank); + for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) { + if (ctr % 4 == 0) + printf("F%2d:", f); + printf("\t%#04x", (u8)(iim_fb[f])); + if (ctr % 4 == 3) + printf("\n"); + } + if (ctr % 4 != 0) + printf("\n"); +} + +int ads5121_fuse_override(int bank, int f, u8 val) +{ + volatile iim512x_t *iim = &((immap_t *) CFG_IMMR)->iim; + u32 *iim_fb; + u32 iim_stat; + int i; + + if (bank == 0) + iim_fb = (u32 *)&(iim->fbac0); + else + iim_fb = (u32 *)&(iim->fbac1); +/* try a read to see if Read Protect is set */ + iim_stat = iim_fb[0]; + if (iim->err & IIM_ERR_RPE) { + printf("Read protect fuse is set on bank %d;" + "Override protect may also be set\n", bank); + printf("An attempt will be made to override\n"); + iim->err = 0; + } + if (iim_stat & IIM_FBAC_FBOP) { + printf("Override protect fuse is set on bank %d\n", bank); + return 1; + } + if (f > IIM_FMAX) /* reset the entire bank */ + for (i = 0; i < IIM_FMAX + 1; i++) + iim_fb[i] = 0; + else + iim_fb[f] = val; + + return 0; +} + +int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno) +{ + volatile iim512x_t *iim = &((immap_t *) CFG_IMMR)->iim; + int f, i; + int bitno; + + f = simple_strtoul(fuseno_bitno, NULL, 10); + if (f > IIM_FMAX) { + printf("Fuse row number ranges from 0-%d\n", IIM_FMAX); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + bitno = -1; + for (i = 0; i < 8; i++) { + if (fuseno_bitno[i] == '_') { + bitno = simple_strtoul(&(fuseno_bitno[i+1]), NULL, 10); + break; + } else if (fuseno_bitno[i] == '\0') + break; + } + if (bitno > 8) { + printf("Bit number ranges from 0-7\n"); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + iim->prg_p = IIM_PRG_P_SET; + iim->ua = IIM_SET_UA(bank, f); + iim->la = IIM_SET_LA(f, bitno); +#ifdef DEBUG + printf("Programming disabled with DEBUG defined \n"); + printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la); +#else + iim->fctl = IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG; + do + udelay(10); + while (iim->stat & IIM_STAT_BUSY); + if (iim->stat & IIM_STAT_PRGD) { + if (!(iim->err & (IIM_ERR_WPE | IIM_ERR_WPE))) { + printf("Fuse is successfully set "); + if (iim->err) + printf("- however there are other errors"); + printf("\n"); + } + iim->stat = 0; + } + if (iim->err) { + iim_err_msg(iim->err); + iim->err = 0; + } +#endif +} + +int ads5121_fuse_sense(int bank, int fstart, int num) +{ + volatile iim512x_t *iim = &((immap_t *) CFG_IMMR)->iim; + u32 iim_fbac; + u32 err_hold; + int f, ctr; + + if (bank == 0) + iim_fbac = iim->fbac0; + else + iim_fbac = iim->fbac1; + + if (iim_fbac & (IIM_FBAC_FBESP | IIM_FBAC_FBSP)) { + printf("Protection Fuses Bank %d = %#04x:\n", bank, (u8)iim_fbac); + printf("\tSense Protect is set\n"); + return 1; + } + if (iim->err & IIM_ERR_RPE) { + printf("\tRead protect fuse is set; " + "Sense Protect may be set but will be attempted\n"); + iim->err = 0; + } + printf("Sensing fuse(s) on Bank %d\n", bank); + for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) { + iim->ua = IIM_SET_UA(bank, f); + iim->la = IIM_SET_LA(f, 0); + iim->fctl = IIM_FCTL_ESNS_N; + do + udelay(100); + while (iim->stat & IIM_STAT_BUSY); + if (iim->err & IIM_ERR_SNSE) { + iim_err_msg(iim->err); + iim->err = 0; + return 1; + } + if (iim->stat & IIM_STAT_SNSD) { + iim->stat = 0; + if (ctr % 4 == 0) + printf("F%2d:", f); + printf("\t%#04x", (u8)(iim->sdat)); + if (ctr % 4 == 3) + printf("\n"); + } + if (iim->err) { + err_hold |= iim->err; + iim->err = 0; + } + } + if (ctr % 4 != 0) + printf("\n"); + if (err_hold) + iim_err_msg(err_hold); + + return 0; +} + +int ads5121_fuse_stat(int bank) +{ + volatile iim512x_t *iim = &((immap_t *) CFG_IMMR)->iim; + u32 iim_fbac; + + if (bank == 0) + iim_fbac = iim->fbac0; + else + iim_fbac = iim->fbac1; + if (iim->err) + iim_err_msg(iim->err); + if (iim_fbac & IIM_PROTECTION) + printf("Protection Fuses on Bank %d = %#04x:\n", bank, iim_fbac); + else if (!(iim->err & IIM_ERR_RPE)) + printf("No Protection fuses set\n"); + if (iim_fbac & IIM_FBAC_FBWP) + printf("\tWrite Protect is set\n"); + if (iim_fbac & IIM_FBAC_FBOP) + printf("\tOverride Protect is set\n"); + if (iim->err & IIM_ERR_RPE || iim_fbac & IIM_FBAC_FBRP) { + printf("\tRead protect fuse is set\n"); + if (iim_fbac == 0) + printf(" Settings can't be read - try sensing fuse 0;\n"); + } + if (iim_fbac & IIM_FBAC_FBESP || iim_fbac & IIM_FBAC_FBSP) + printf("\tSense Protect is set\n"); + iim->err = 0; + + return 0; +} + +int do_ads5121_fuse(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + int frow, n, v, bank; + + if (cur_bank == '0') + bank = 0; + else + bank = 1; + + switch (argc) { + case 0: + case 1: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1], "stat", 4) == 0) { + ads5121_fuse_stat(bank); + return 0; + } else if (strncmp(argv[1], "read", 4) == 0) { + ads5121_fuse_read(bank, 0, IIM_FMAX + 1); + return 0; + } else if (strncmp(argv[1], "sense", 5) == 0) { + ads5121_fuse_sense(bank, 0, IIM_FMAX + 1); + return 0; + } else if (strncmp(argv[1], "ovride", 6) == 0) { + ads5121_fuse_override(bank, IIM_FMAX + 1, 0); + return 0; + } else if (strncmp(argv[1], "bank", 4) == 0) { + printf("Active Fuse Bank is %c\n", cur_bank); + return 0; + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strncmp(argv[1], "bank", 4) == 0) { + if (argv[2][0] == '0') + cur_bank = '0'; + else if (argv[2][0] == '1') + cur_bank = '1'; + else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + printf("Setting Active Fuse Bank to %c\n", cur_bank); + return 0; + } else if (strncmp(argv[1], "read", 4) == 0) { + frow = (int)simple_strtoul(argv[2], NULL, 10); + if (frow > IIM_FMAX || frow < 0) { + printf("<frow> is the fuse row, 0-31 decimal\n\n"); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return ads5121_fuse_read(bank, frow, 1); + } else if (strncmp(argv[1], "ovride", 6) == 0) { + frow = (int)simple_strtoul(argv[2], NULL, 10); + return ads5121_fuse_override(bank, frow, 0); + } else if (strncmp(argv[1], "sense", 5) == 0) { + frow = (int)simple_strtoul(argv[2], NULL, 10); + return ads5121_fuse_sense(bank, frow, 1); + } else if (strncmp(argv[1], "prog", 4) == 0) { + return ads5121_fuse_prog(cmdtp, bank, argv[2]); + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 4: + if (strncmp(argv[1], "read", 4) == 0) { + frow = (int)simple_strtoul(argv[2], NULL, 10); + if (frow > IIM_FMAX || frow < 0) { + printf("<frow> is the fuse row, a decimal number 0-31\n\n"); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + n = (int)simple_strtoul(argv[3], NULL, 10); + if (frow + n > IIM_FMAX + 1) { + printf("There are %d fuses per bank\n\n", IIM_FMAX); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return ads5121_fuse_read(bank, frow, n); + } else if (strncmp(argv[1], "ovride", 6) == 0) { + frow = (int)simple_strtoul(argv[2], NULL, 10); + if (frow > IIM_FMAX || frow < 0) { + printf("<frow> is the fuse row, 0-31 decimal\n\n"); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + v = (int)simple_strtoul(argv[3], NULL, 10); + return ads5121_fuse_override(bank, frow, v); + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + default: /* at least 5 args */ + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + fuse, CFG_MAXARGS, 0, do_ads5121_fuse, + " - Read, Sense, Override or Program Fuses\n", + "bank <n> - Set the active Fuse Bank n (0 or 1) Default is 1\n" + "fuse stat - print active fuse bank's status\n" + "fuse read [<frow> [<num>]] - print <num> fuse rows starting at <frow>\n" + " - no args to print entire bank's fuses\n" + "fuse ovride [<frow> [<val>]] - override fuses at <frow> with <val> (default=0)\n" + " - no args resets entire bank\n" + "fuse sense [<frow>] - senses current fuse at <frow>, no args for entire bank\n" + "fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n" + " - <frow> ranges from 0-31, <bit> ranges from 0-7\n" + ); +#endif /* CONFIG_CMD_FUSE */ diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index cd90945..222d713 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -415,7 +415,25 @@ typedef struct ioctrl512x { * IIM */ typedef struct iim512x { - u8 fixme[0x1000]; + u32 stat; /* IIM status register */ + u32 statm; /* IIM status IRQ mask */ + u32 err; /* IIM errors register */ + u32 emask; /* IIM error IRQ mask */ + u32 fctl; /* IIM fuse control register */ + u32 ua; /* IIM upper address register */ + u32 la; /* IIM lower address register */ + u32 sdat; /* IIM explicit sense data */ + u8 res0[0x08]; + u32 prg_p; /* IIM program protection register */ + u8 res1[0x10]; + u32 divide; /* IIM divide factor register */ + u8 res2[0x7c0]; + u32 fbac0; /* IIM fuse bank 0 protection (for Freescale use) */ + u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ + u8 res3[0x380]; + u32 fbac1; /* IIM fuse bank 1 protection */ + u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ + u8 res4[0x380]; } iim512x_t; /* diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index d6f7e02..1955fba 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -294,6 +294,11 @@ #endif /* + * IIM - IC Identification Module + */ +#define CONFIG_IIM + +/* * EEPROM configuration */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ @@ -348,6 +353,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE +#define CONFIG_CMD_FUSE #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/mpc512x.h b/include/mpc512x.h index cb418d1..49f5cd2 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -574,6 +574,31 @@ void iopin_initialize(iopin_t *,int); /* Register Offset Base */ #define MPC512X_FEC (CFG_IMMR + 0x02800) +/* IIM control */ +#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5)) +#define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit) +#define IIM_STAT_BUSY 0x00000080 +#define IIM_STAT_PRGD 0x00000002 +#define IIM_STAT_SNSD 0x00000001 +#define IIM_ERR_WPE 0x00000040 +#define IIM_ERR_OPE 0x00000020 +#define IIM_ERR_RPE 0x00000010 +#define IIM_ERR_WLRE 0x00000008 +#define IIM_ERR_SNSE 0x00000004 +#define IIM_ERR_PARITYE 0x00000002 +#define IIM_PRG_P_SET 0x000000aa +#define IIM_PRG_P_UNSET 0 +#define IIM_FCTL_PROG_PULSE 0x00000020 +#define IIM_FCTL_PROG 0x00000001 +#define IIM_FCTL_ESNS_N 0x00000008 +#define IIM_FBAC_FBWP 0x00000080 +#define IIM_FBAC_FBOP 0x00000040 +#define IIM_FBAC_FBRP 0x00000020 +#define IIM_FBAC_FBSP 0x00000010 +#define IIM_FBAC_FBESP 0x00000008 +#define IIM_PROTECTION 0x000000f8 +#define IIM_FMAX 31 + /* Number of I2C buses */ #define I2C_BUS_CNT 3 -- 1.5.2.4

2 1

[U-Boot] make clean problem
by Eugene O'Brien 08 Oct '08

08 Oct '08

Hello, I just stumbled on a problem with the make clean command in U-Boot. When executing make clean I noticed that some programmes that should have been deleted were not deleted. These were the programmes to be deleted with instructions such as: @rm -f $(obj)tools/env/{fw_printenv,fw_setenv} The reason is (after scratching my head for a few hours) that on my platform BASH is not the default shell. I am using Ubuntu and /bin/sh is linked to dash (see https://wiki.ubuntu.com/DashAsBinSh for details). As I am not an expert on shells, my guess is that the above construct is a "bashism" and not compliant to /bin/sh. There are two trivial solutions to this problem: (a) Add a line SHELL=/bin/bash somewhere in top level Makefile (b) Write out each individual file's path name separately in the @rm command line. What is best course of action? Choosing (a) means that we are specifying BASH as a requirement for the U-Boot HOST environment. If this is already the case then solution (a) is perhaps the best and limits U-Boot regression testing to one shell type. Otherwise if we want to be compatible with /bin/sh then I believe solution (b) is preferable. Regards, Eugene O'Brien

3 3

[U-Boot] [PATCH 2/3] iMX31: Add support to copy NAND Flash code to RAM
by Alan Carvalho de Assis 08 Oct '08

08 Oct '08

>From 473120de8390abd78014cac9fe0925cb49f57fbe Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis <alan.assis(a)freescale.com> Date: Sun, 5 Oct 2008 19:59:47 -0300 Subject: [PATCH] iMX31: Add support to copy NAND Flash code to RAM This code is executed from internal 2KB NAND Flash Controller RAM buffer and will copy the remaining U-Boot code from NAND Flash verifying its bad blocks (case it exists). Signed-off-by: Alan Carvalho de Assis <alan.assis(a)freescale.com> --- cpu/arm1136/mx31/Makefile | 2 + cpu/arm1136/mx31/nand_copy.S | 263 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 69 +++++++++ 3 files changed, 334 insertions(+), 0 deletions(-) create mode 100644 cpu/arm1136/mx31/nand_copy.S diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index b648ffd..0490706 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a COBJS = interrupts.o serial.o generic.o +SOBJS-$(CONFIG_BOOT_FROM_NAND) = nand_copy.o +SOBJS := $(SOBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/nand_copy.S b/cpu/arm1136/mx31/nand_copy.S new file mode 100644 index 0000000..591720a --- /dev/null +++ b/cpu/arm1136/mx31/nand_copy.S @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * + * Alan Carvalho de Assis <alan.assis(a)freescale.com> + * based on iMX31PDK RedBoot_200814 code. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx31-regs.h> + +.macro do_addr_input + and r3, r3, #0xFF + strh r3, [r12, #NFC_FLASH_ADDR_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done +.endm /* do_addr_input */ + +do_wait_op_done: +1: ldrh r3, [r12, #NFC_CONFIG2_OFF] + ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE + beq 1b + bx lr + +nfc_data_output: + mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN) + strh r3, [r12, #NFC_CONFIG1_OFF] + strh r8, [r12, #NFC_BUF_ADDR_OFF] + mov r3, #FDO_PAGE_SPARE_VAL + strh r3, [r12, #NFC_CONFIG2_OFF] + bx lr + +.globl nand_copy +nand_copy: + /* Copy image from flash to SDRAM first */ + mov r0, #NFC_BASE_ADDR + add r2, r0, #0x800 /* 2K window */ + ldr r1, MXC_UBOOT_ROM_START + +1: ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + blo 1b + /* Jump to SDRAM */ + ldr r1, =0x0FFF + and r0, pc, r1 /* offset of pc */ + ldr r1, MXC_UBOOT_ROM_START + add r1, r1, #0x10 + add pc, r0, r1 + nop + nop + nop + nop + +nand_copy_main: + /* Check if x16/2kb page */ + ldr r7, =CCM_BASE + ldr r7, [r7, #0xC] + ands r7, r7, #(1 << 30) + + mov r0, #NAND_FLASH_BOOT + ldr r1, =AVIC_VECTOR0 + str r0, [r1] + mov r0, #MXCFIS_NAND + ldr r1, =AVIC_VECTOR1 + str r0, [r1] + + mov r0, #NFC_BASE_ADDR /* r0: nfc base. Reloaded after each page copying */ + mov r1, #0x800 /* r1: starting flash addr to be copied. Updated constantly */ + add r2, r0, #0x800 /* r2: end of 3rd RAM buf. Doesn't change */ + addeq r2, r0, #0x200 /* r2: end of 1st RAM buf. Doesn't change (only set for small page NAND) */ + add r12, r0, #0xE00 /* r12: NFC register base. Doesn't change */ + ldr r11, MXC_UBOOT_ROM_START + add r13, r11, #0x40000 /* r13: end of SDRAM address for copying. Doesn't change */ + add r11, r11, r1 /* r11: starting SDRAM address for copying. Updated constantly */ + + /* unlock internal buffer */ + mov r3, #0x2 + strh r3, [r12, #0xA] + +nfc_read_page: + mov r3, #0x0 + strh r3, [r12, #NFC_FLASH_CMD_OFF] + mov r3, #NAND_FLASH_CONFIG2_FCMD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + + /* Check if x16/2kb page */ + ldr r7, =CCM_BASE + ldr r7, [r7, #0xC] + ands r7, r7, #(1 << 30) + bne nfc_addr_ops_2kb + + /* 1st addr cycle */ + mov r3, r1 + do_addr_input + /* 1st addr cycle */ + mov r3, r1, lsr #9 + do_addr_input + /* 1st addr cycle */ + mov r3, r1, lsr #17 + do_addr_input + /* 1st addr cycle */ + mov r3, r1, lsr #25 + do_addr_input + b end_of_nfc_addr_ops + +nfc_addr_ops_2kb: + /* 1st addr cycle */ + mov r3, #0 + and r3, r3, #0xFF + strh r3, [r12, #NFC_FLASH_ADDR_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + mov r3, #0 + /* 2nd addr cycle */ + and r3, r3, #0xFF + strh r3, [r12, #NFC_FLASH_ADDR_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + mov r3, r1, lsr #11 + /* 3rd addr cycle */ + and r3, r3, #0xFF + strh r3, [r12, #NFC_FLASH_ADDR_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + mov r3, r1, lsr #19 + /* 4th addr cycle */ + and r3, r3, #0xFF + strh r3, [r12, #NFC_FLASH_ADDR_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + mov r3, r1, lsr #27 + /* 5th addr cycle */ + and r3, r3, #0xFF + strh r3, [r12, #NFC_FLASH_ADDR_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + + mov r3, #0x30 + strh r3, [r12, #NFC_FLASH_CMD_OFF] + mov r3, #NAND_FLASH_CONFIG2_FCMD_EN + strh r3, [r12, #NFC_CONFIG2_OFF] + bl do_wait_op_done + +end_of_nfc_addr_ops: + mov r8, #0 + bl nfc_data_output + bl do_wait_op_done + + /* Check if x16/2kb page */ + ldr r7, =CCM_BASE + ldr r7, [r7, #0xC] + ands r7, r7, #(1 << 30) + beq nfc_addr_data_output_done_512 + + /* For 2K page - 2nd 512 */ + mov r8, #1 + bl nfc_data_output + bl do_wait_op_done + + /* 3rd 512 */ + mov r8, #2 + bl nfc_data_output + bl do_wait_op_done + + /* 4th 512 */ + mov r8, #3 + bl nfc_data_output + bl do_wait_op_done + + /* check for bad block */ + mov r3, r1, lsl #(32-17) /* get rid of block number */ + cmp r3, #(0x800 << (32-17)) /* check if not page 0 or 1 */ + b nfc_addr_data_output_done + +nfc_addr_data_output_done_512: + /* check for bad block */ + mov r3, r1, lsl #(32-5-9) /* get rid of block number */ + cmp r3, #(512 << (32-5-9)) /* check if not page 0 or 1 */ + +nfc_addr_data_output_done: + bhi copy_good_blk + add r4, r0, #0x800 /* r3 -> spare area buf 0 */ + ldrh r4, [r4, #0x4] + and r4, r4, #0xFF00 + cmp r4, #0xFF00 + beq copy_good_blk + /* really sucks. Bad block!!!! */ + cmp r3, #0x0 + beq skip_bad_block + + /* even suckier since we already read the first page! */ + /* Check if x16/2kb page */ + ldr r7, =CCM_BASE + ldr r7, [r7, #0xC] + ands r7, r7, #(1 << 30) + + subeq r11, r11, #512 /* rewind 1 page for the sdram pointer */ + subeq r1, r1, #512 /* rewind 1 page for the flash pointer */ + + /* for 2k page */ + subne r11, r11, #0x800 /* rewind 1 page for the sdram pointer */ + subne r1, r1, #0x800 /* rewind 1 page for the flash pointer */ + +skip_bad_block: + /* Check if x16/2kb page */ + ldr r7, =CCM_BASE + ldr r7, [r7, #0xC] + ands r7, r7, #(1 << 30) + + addeq r1, r1, #(32*512) + addne r1, r1, #(64*2048) + b nfc_read_page + +copy_good_blk: + /* copying page */ +1: ldmia r0!, {r3-r10} + stmia r11!, {r3-r10} + cmp r0, r2 + blo 1b + cmp r11, r13 + bge nand_copy_main_done + /* Check if x16/2kb page */ + ldr r7, =CCM_BASE + ldr r7, [r7, #0xC] + ands r7, r7, #(1 << 30) + + addeq r1, r1, #0x200 + addne r1, r1, #0x800 + mov r0, #NFC_BASE_ADDR + b nfc_read_page + +nand_copy_main_done: + /* Restore stack pointer since sp has been re-used in this file */ + ldr sp, =CFG_INTERNAL_SRAM_STACK + /* Restore return address and return to caller */ + ldr lr, [sp] + bx lr + +MXC_UBOOT_ROM_START: .word 0x87F00000 +UBOOT_IMAGE_SIZE: .word 0x40000 + diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index b04a718..1c5c121 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -84,8 +84,14 @@ #define IPU_CONF_IC_EN (1<<1) #define IPU_CONF_SCI_EN (1<<0) +#define ARM_PPMRR 0x40000015 + #define WDOG_BASE 0x53FDC000 +#define AVIC_BASE 0x68000000 +#define AVIC_VECTOR0 (AVIC_BASE + 0x100) +#define AVIC_VECTOR1 (AVIC_BASE + 0x104) + /* * Signal Multiplexing (IOMUX) */ @@ -168,4 +174,67 @@ #define CS5_BASE 0xB6000000 #define PCMCIA_MEM_BASE 0xC0000000 +/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB8000000 +#define NFC_REGS (NFC_BASE_ADDR + 0xE00) + +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE_OFF 0 +#define NFC_BUF_SIZE (*((volatile u16 *)(NFC_REGS + NFC_BUF_SIZE_OFF))) +#define NFC_BUF_ADDR_OFF 0x04 +#define NFC_BUF_ADDR (*((volatile u16 *)(NFC_REGS + NFC_BUF_ADDR_OFF))) +#define NFC_FLASH_ADDR_OFF 0x06 +#define NFC_FLASH_ADDR (*((volatile u16 *)(NFC_REGS + NFC_FLASH_ADDR_OFF))) +#define NFC_FLASH_CMD_OFF 0x08 +#define NFC_FLASH_CMD (*((volatile u16 *)(NFC_REGS + NFC_FLASH_CMD_OFF))) +#define NFC_CONFIG_OFF 0x0A +#define NFC_CONFIG (*((volatile u16 *)(NFC_REGS + NFC_CONFIG_OFF))) +#define NFC_ECC_RSLT_OFF 0x0C +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)(NFC_REGS + NFC_ECC_RSLT_OFF))) +#define NFC_RSLTMAIN_AREA_OFF 0x0E +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)(NFC_REGS + NFC_RSLTMAIN_AREA_OFF))) +#define NFC_RSLTSPARE_AREA_OFF 0x10 +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)(NFC_REGS + NFC_RSLTSPARE_AREA_OFF))) +#define NFC_WRPROT_OFF 0x12 +#define NFC_WRPROT (*((volatile u16 *)(NFC_REGS + NFC_WRPROT_OFF))) +#define NFC_UNLCKSTART_BLK_OFF 0x14 +#define NFC_UNLCKSTART_BLKADDR (*((volatile u16 *)(NFC_REGS + NFC_UNLOCKSTART_BLK_OFF))) +#define NFC_UNLCKEND_BLK_OFF 0x16 +#define NFC_UNLCKEND_BLKADDR (*((volatile u16 *)(NFC_REGS + NFC_UNLOCKEND_BLK_OFF))) +#define NFC_NF_WRPRST_OFF 0x18 +#define NFC_NF_WRPRST (*((volatile u16 *)(NFC_REGS + NFC_NF_WRPRST_OFF))) +#define NFC_CONFIG1_OFF 0x1A +#define NFC_CONFIG1 (*((volatile u16 *)(NFC_REGS + NFC_CONFIG1_OFF))) +#define NFC_CONFIG2_OFF 0x1C +#define NFC_CONFIG2 (*((volatile u16 *)(NFC_REGS + NFC_CONFIG2_OFF))) + +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 +#define NAND_FLASH_BOOT 0x10000000 +#define MXCFIS_NAND 0x10000000 + #endif /* __ASM_ARCH_MX31_REGS_H */ -- 1.5.4.3

2 2

[U-Boot] [PATCH 3/3 v5] ppc4xx: Add routine to retrieve CPU number
by Adam Graham 08 Oct '08

08 Oct '08

Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham(a)amcc.com> Signed-off-by: Victor Gallardo <vgallardo(a)amcc.com> --- v2: - Correct return code of the generic get_cpu_num routine and make the return code a defined value. v3: - Correct tab/spaces in ppc4xx.h v4: - Fix commit text (line to long) - Remove starting underscores from NA_OR_UNKNOWN_CPU v5: - Fix commit text (line to long) again. cpu/ppc4xx/cpu.c | 19 ++++++++++++++++++- include/ppc4xx.h | 3 +++ 2 files changed, 21 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index bc9335a..67f88f8 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -41,6 +41,18 @@ DECLARE_GLOBAL_DATA_PTR; void board_reset(void); +/* + * To provide an interface to detect CPU number for boards that support + * more then one CPU, we implement the "weak" default functions here. + * + * Returns CPU number + */ +int __get_cpu_num(void) +{ + return NA_OR_UNKNOWN_CPU; +} +int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num"))); + #if defined(CONFIG_405GP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -274,8 +286,13 @@ int checkcpu (void) #if !defined(CONFIG_IOP480) char addstr[64] = ""; sys_info_t sys_info; + int cpu_num; - puts ("CPU: "); + cpu_num = get_cpu_num(); + if (cpu_num >= 0) + printf("CPU%d: ", cpu_num); + else + puts("CPU: "); get_sys_info(&sys_info); diff --git a/include/ppc4xx.h b/include/ppc4xx.h index e216663..61209a7 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -218,4 +218,7 @@ static inline void set_mcsr(u32 val) #endif /* __ASSEMBLY__ */ +/* for multi-cpu support */ +#define NA_OR_UNKNOWN_CPU -1 + #endif /* __PPC4XX_H__ */ -- 1.5.5

1 0

[U-Boot] [PATCH 2/3 v5] ppc4xx: Add static support for 44x IBM SDRAM Controller
by Adam Graham 08 Oct '08

08 Oct '08

This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham(a)amcc.com> Signed-off-by: Victor Gallardo <vgallardo(a)amcc.com> --- v2: - No changes. v3: - No changes. v4: - Fix commit text (line to long) - Fix typo (it's to its) v5: - No changes. cpu/ppc4xx/44x_spd_ddr2.c | 71 +++++++++++++++++++++++++++++++++----------- 1 files changed, 53 insertions(+), 18 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f1d7684..735d476 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -60,6 +60,26 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) +#if defined(CONFIG_440) +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 + * memory region. Right now the cache should still be disabled in U-Boot + * because of the EMAC driver, that need its buffer descriptor to be located + * in non cached memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CONFIG_4xx_DCACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CONFIG_4xx_DCACHE +/* enable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE 0 +#else +/* disable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE +#endif /* CONFIG_4xx_DCACHE */ +#endif /* CONFIG_440 */ + #if defined(CONFIG_SPD_EEPROM) /*-----------------------------------------------------------------------------+ @@ -131,22 +151,6 @@ #define NUMLOOPS 64 /* memory test loops */ /* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory - * region. Right now the cache should still be disabled in U-Boot because of the - * EMAC driver, that need it's buffer descriptor to be located in non cached - * memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#ifdef CONFIG_4xx_DCACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -#endif - -/* * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. * To support such configurations, we "only" map the first 2GB via the TLB's. We * need some free virtual address space for the remaining peripherals like, SoC @@ -2956,9 +2960,10 @@ static void test(void) /*----------------------------------------------------------------------------- * Function: initdram - * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory - * banks. The configuration is performed using static, compile- + * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. + * The configuration is performed using static, compile- * time parameters. + * Configures the PPC405EX(r) and PPC460EX/GT *---------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { @@ -2974,6 +2979,18 @@ phys_size_t initdram(int board_type) #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) unsigned long val; +#if defined(CONFIG_440) + mtdcr(SDRAM_R0BAS, CFG_SDRAM_R0BAS); + mtdcr(SDRAM_R1BAS, CFG_SDRAM_R1BAS); + mtdcr(SDRAM_R2BAS, CFG_SDRAM_R2BAS); + mtdcr(SDRAM_R3BAS, CFG_SDRAM_R3BAS); + mtdcr(SDRAM_PLBADDULL, CFG_SDRAM_PLBADDULL); /* MQ0_BAUL */ + mtdcr(SDRAM_PLBADDUHB, CFG_SDRAM_PLBADDUHB); /* MQ0_BAUH */ + mtdcr(SDRAM_CONF1LL, CFG_SDRAM_CONF1LL); + mtdcr(SDRAM_CONF1HB, CFG_SDRAM_CONF1HB); + mtdcr(SDRAM_CONFPATHB, CFG_SDRAM_CONFPATHB); +#endif + /* Set Memory Bank Configuration Registers */ mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); @@ -3067,6 +3084,14 @@ phys_size_t initdram(int board_type) mfsdram(SDRAM_MCOPT2, val); mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); +#if defined(CONFIG_440) + /* + * Program TLB entries with caches enabled, for best performace + * while auto-calibrating and ECC generation + */ + program_tlb(0, 0, (CFG_MBYTES_SDRAM << 20), 0); +#endif + #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /*------------------------------------------------------------------ @@ -3080,6 +3105,16 @@ phys_size_t initdram(int board_type) ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ +#if defined(CONFIG_440) + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(0, (CFG_MBYTES_SDRAM << 20)); + program_tlb(0, 0, (CFG_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE); +#endif + ppc4xx_ibm_ddr2_register_dump(); #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -- 1.5.5

1 0

[U-Boot] [PATCH 2/3 v5] ppc4xx: Add static support for 44x IBM SDRAM Controller
by Adam Graham 08 Oct '08

08 Oct '08

This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham(a)amcc.com> Signed-off-by: Victor Gallardo <vgallardo(a)amcc.com> --- v2: - No changes. v3: - No changes. v4: - Fix commit text (line to long) - Fix typo (it's to its) v5: - No changes. cpu/ppc4xx/44x_spd_ddr2.c | 71 +++++++++++++++++++++++++++++++++----------- 1 files changed, 53 insertions(+), 18 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f1d7684..735d476 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -60,6 +60,26 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) +#if defined(CONFIG_440) +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 + * memory region. Right now the cache should still be disabled in U-Boot + * because of the EMAC driver, that need its buffer descriptor to be located + * in non cached memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CONFIG_4xx_DCACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CONFIG_4xx_DCACHE +/* enable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE 0 +#else +/* disable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE +#endif /* CONFIG_4xx_DCACHE */ +#endif /* CONFIG_440 */ + #if defined(CONFIG_SPD_EEPROM) /*-----------------------------------------------------------------------------+ @@ -131,22 +151,6 @@ #define NUMLOOPS 64 /* memory test loops */ /* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory - * region. Right now the cache should still be disabled in U-Boot because of the - * EMAC driver, that need it's buffer descriptor to be located in non cached - * memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#ifdef CONFIG_4xx_DCACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -#endif - -/* * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. * To support such configurations, we "only" map the first 2GB via the TLB's. We * need some free virtual address space for the remaining peripherals like, SoC @@ -2956,9 +2960,10 @@ static void test(void) /*----------------------------------------------------------------------------- * Function: initdram - * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory - * banks. The configuration is performed using static, compile- + * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. + * The configuration is performed using static, compile- * time parameters. + * Configures the PPC405EX(r) and PPC460EX/GT *---------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { @@ -2974,6 +2979,18 @@ phys_size_t initdram(int board_type) #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) unsigned long val; +#if defined(CONFIG_440) + mtdcr(SDRAM_R0BAS, CFG_SDRAM_R0BAS); + mtdcr(SDRAM_R1BAS, CFG_SDRAM_R1BAS); + mtdcr(SDRAM_R2BAS, CFG_SDRAM_R2BAS); + mtdcr(SDRAM_R3BAS, CFG_SDRAM_R3BAS); + mtdcr(SDRAM_PLBADDULL, CFG_SDRAM_PLBADDULL); /* MQ0_BAUL */ + mtdcr(SDRAM_PLBADDUHB, CFG_SDRAM_PLBADDUHB); /* MQ0_BAUH */ + mtdcr(SDRAM_CONF1LL, CFG_SDRAM_CONF1LL); + mtdcr(SDRAM_CONF1HB, CFG_SDRAM_CONF1HB); + mtdcr(SDRAM_CONFPATHB, CFG_SDRAM_CONFPATHB); +#endif + /* Set Memory Bank Configuration Registers */ mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); @@ -3067,6 +3084,14 @@ phys_size_t initdram(int board_type) mfsdram(SDRAM_MCOPT2, val); mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); +#if defined(CONFIG_440) + /* + * Program TLB entries with caches enabled, for best performace + * while auto-calibrating and ECC generation + */ + program_tlb(0, 0, (CFG_MBYTES_SDRAM << 20), 0); +#endif + #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /*------------------------------------------------------------------ @@ -3080,6 +3105,16 @@ phys_size_t initdram(int board_type) ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ +#if defined(CONFIG_440) + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(0, (CFG_MBYTES_SDRAM << 20)); + program_tlb(0, 0, (CFG_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE); +#endif + ppc4xx_ibm_ddr2_register_dump(); #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -- 1.5.5

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[U-Boot] [PATCH 1/3 v4] ppc4xx: Add AMCC Arches board support (dual 460GT)
by Adam Graham 08 Oct '08

08 Oct '08

The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham(a)amcc.com> Signed-off-by: Victor Gallardo <vgallardo(a)amcc.com> --- v2: - Added Arches (460GT) support to the existing Canyonlands (460) board files since the Canyonlands board files support all current AMCC PPC460EX/GT boards. v3: - Correct tab/spaces in canyonlands.h file. v4: - Fix commit text (line to long) - remove unneed timeout for ETH_PLL lock - remove CONFIG_EXTRA_ENV_SETTINGS from "USB connectivity" section - seperated CONFIG_CMD_xxx on a per board bases - Use ethprime to set Arches default ethernet port to 1 v5: - No changes. MAKEALL | 1 + Makefile | 3 +- board/amcc/canyonlands/canyonlands.c | 140 ++++++++++++++++++++++ board/amcc/canyonlands/init.S | 17 +++ include/configs/amcc-common.h | 17 +++- include/configs/canyonlands.h | 219 +++++++++++++++++++++++++++++++--- include/ppc440.h | 3 + 7 files changed, 383 insertions(+), 17 deletions(-) diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..847c1fa 100755 --- a/MAKEALL +++ b/MAKEALL @@ -161,6 +161,7 @@ LIST_4xx=" \ alpr \ AP1000 \ AR405 \ + arches \ ASH405 \ bamboo \ bamboo_nand \ diff --git a/Makefile b/Makefile index 7c13ce8..2af11c4 100644 --- a/Makefile +++ b/Makefile @@ -1206,7 +1206,8 @@ bubinga_config: unconfig CANBT_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd -# Canyonlands & Glacier use different U-Boot images +# Arches, Canyonlands & Glacier use different U-Boot images +arches_config \ canyonlands_config \ glacier_config: unconfig @mkdir -p $(obj)include diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index e9eba49..b6ee2ab 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -38,11 +38,52 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARD_CANYONLANDS_PCIE 1 #define BOARD_CANYONLANDS_SATA 2 #define BOARD_GLACIER 3 +#define BOARD_ARCHES 4 + +#if defined(CONFIG_ARCHES) +/* + * FPGA read/write helper macros + */ +static inline int board_fpga_read(int offset) +{ + int data; + + data = in_8((void *)(CFG_FPGA_BASE + offset)); + + return data; +} + +static inline void board_fpga_write(int offset, int data) +{ + out_8((void *)(CFG_FPGA_BASE + offset), data); +} + +/* + * CPLD read/write helper macros + */ +static inline int board_cpld_read(int offset) +{ + int data; + + out_8((void *)(CFG_CPLD_ADDR), offset); + data = in_8((void *)(CFG_CPLD_DATA)); + + return data; +} + +static inline void board_cpld_write(int offset, int data) +{ + out_8((void *)(CFG_CPLD_ADDR), offset); + out_8((void *)(CFG_CPLD_DATA), data); +} +#endif /* defined(CONFIG_ARCHES) */ int board_early_init_f(void) { +#if !defined(CONFIG_ARCHES) u32 sdr0_cust0; u32 pvr = get_pvr(); +#endif /* * Setup the interrupt controller polarities, triggers, etc. @@ -79,6 +120,7 @@ int board_early_init_f(void) mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic3sr, 0xffffffff); /* clear all */ +#if !defined(CONFIG_ARCHES) /* SDR Setting - enable NDFC */ mfsdr(SDR0_CUST0, sdr0_cust0); sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | @@ -88,6 +130,7 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_BAC_ENCODE(3) | (0x80000000 >> (28 + CFG_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); +#endif /* * Configure PFC (Pin Function Control) registers @@ -98,6 +141,7 @@ int board_early_init_f(void) /* Enable PCI host functionality in SDR0_PCI0 */ mtsdr(SDR0_PCI0, 0xe0000000); +#if !defined(CONFIG_ARCHES) /* Enable ethernet and take out of reset */ out_8((void *)CFG_BCSR_BASE + 6, 0); @@ -123,10 +167,12 @@ int board_early_init_f(void) gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); } +#endif return 0; } +#if !defined(CONFIG_ARCHES) static void canyonlands_sata_init(int board_type) { u32 reg; @@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type) SDR_WRITE(SDR0_SRST1, 0x00000000); } } +#endif /* !defined(CONFIG_ARCHES) */ + +int get_cpu_num(void) +{ + int cpu = NA_OR_UNKNOWN_CPU; + +#if defined(CONFIG_ARCHES) + int cpu_num; + + cpu_num = board_fpga_read(0x3); + + /* sanity check; assume cpu numbering starts and increments from 0 */ + if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) + cpu = cpu_num; +#endif + + return cpu; +} +#if !defined(CONFIG_ARCHES) int checkboard(void) { char *s = getenv("serial#"); @@ -188,6 +253,39 @@ int checkboard(void) return (0); } +#else /* defined(CONFIG_ARCHES) */ + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); + printf(" Revision %02x.%02x ", + board_fpga_read(0x0), board_fpga_read(0x1)); + + gd->board_type = BOARD_ARCHES; + + /* Only CPU0 has access to CPLD registers */ + if (get_cpu_num() == 0) { + u8 cfg_sw = board_cpld_read(0x1); + printf("(FPGA=%02x, CPLD=%02x)\n", + board_fpga_read(0x2), board_cpld_read(0x0)); + printf(" Configuration Switch %d%d%d%d\n", + ((cfg_sw >> 3) & 0x01), + ((cfg_sw >> 2) & 0x01), + ((cfg_sw >> 1) & 0x01), + ((cfg_sw >> 0) & 0x01)); + } else + printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); + + + if (s != NULL) + printf(" Serial# %s\n", s); + + return 0; +} +#endif /* !defined(CONFIG_ARCHES) */ + /* * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. @@ -389,6 +487,7 @@ int board_early_init_r (void) return 0; } +#if !defined(CONFIG_ARCHES) int misc_init_r(void) { u32 sdr0_srst1 = 0; @@ -434,6 +533,47 @@ int misc_init_r(void) return 0; } +#else /* defined(CONFIG_ARCHES) */ + +int misc_init_r(void) +{ + u32 eth_cfg = 0; + u32 eth_pll; + u32 reg; + + /* + * Set EMAC mode/configuration (GMII, SGMII, RGMII...). + * This is board specific, so let's do it here. + */ + + /* enable SGMII mode */ + eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | + SDR0_ETH_CFG_SGMII1_ENABLE | + SDR0_ETH_CFG_SGMII2_ENABLE); + + /* Set EMAC for MDIO */ + eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; + + /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ + eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + + mtsdr(SDR0_ETH_CFG, eth_cfg); + + /* reset all SGMII interfaces */ + mfsdr(SDR0_SRST1, reg); + reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); + mtsdr(SDR0_SRST1, reg); + mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); + mtsdr(SDR0_SRST1, 0x00000000); + + do { + mfsdr(SDR0_ETH_PLL, eth_pll); + } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK)); + + return 0; +} +#endif /* !defined(CONFIG_ARCHES) */ + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 258fb5d..12dead3 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -77,11 +77,16 @@ tlbtab: /* PCIe UTL register */ tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) +#if !defined(CONFIG_ARCHES) /* TLB-entry for NAND */ tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) /* TLB-entry for CPLD */ tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#else + /* TLB-entry for FPGA */ + tlbentry(CFG_FPGA_BASE, SZ_16M, CFG_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#endif /* TLB-entry for OCM */ tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) @@ -92,6 +97,18 @@ tlbtab: /* AHB: Internal USB Peripherals (USB, SATA) */ tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) +#if defined(CONFIG_RAPIDIO) + /* TLB-entries for RapidIO (SRIO) */ + tlbentry(CFG_SRGPL0_REG_BAR, SZ_16M, CFG_SRGPL0_REG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_SRGPL0_CFG_BAR, SZ_16M, CFG_SRGPL0_CFG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_SRGPL0_MNT_BAR, SZ_16M, CFG_SRGPL0_MNT_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_I2ODMA_BASE, SZ_1K, 0x00100000, + 0x4, AC_R|AC_W|SA_G|SA_I) +#endif + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 1f27d78..380b447 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -160,6 +160,13 @@ #endif /* + * Only very few boards have default netdev not set to eth0 (like Arches) + */ +#if !defined(CONFIG_USE_NETDEV) +#define CONFIG_USE_NETDEV eth0 +#endif + +/* * Only some 4xx PPC's are equipped with an FPU */ #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ @@ -184,7 +191,7 @@ * General common environment variables shared on all AMCC eval boards */ #define CONFIG_AMCC_DEF_ENV \ - "netdev=eth0\0" \ + "netdev=" xstr(CONFIG_USE_NETDEV) "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -197,8 +204,10 @@ "initrd_high=30000000\0" \ "kernel_addr_r=400000\0" \ "fdt_addr_r=800000\0" \ + "ramdisk_addr_r=C00000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ CONFIG_AMCC_DEF_ENV_ROOTPATH /* @@ -214,6 +223,12 @@ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdt_file};" \ + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ + "net_self=run net_self_load;" \ + "run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" /* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 2f162e1..5ab678a 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -27,14 +27,24 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */ -#ifndef CONFIG_CANYONLANDS +/* + * This config file is used for Canyonlands (460EX) Glacier (460GT) + * and Arches dual (460GT) + */ +#ifdef CONFIG_CANYONLANDS +#define CONFIG_460EX 1 /* Specific PPC460EX */ +#define CONFIG_HOSTNAME canyonlands +#else #define CONFIG_460GT 1 /* Specific PPC460GT */ +#ifdef CONFIG_GLACIER #define CONFIG_HOSTNAME glacier #else -#define CONFIG_460EX 1 /* Specific PPC460EX */ -#define CONFIG_HOSTNAME canyonlands +#define CONFIG_HOSTNAME arches +#define CONFIG_USE_NETDEV eth1 +#define CONFIG_BD_NUM_CPUS 2 #endif +#endif + #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ @@ -73,15 +83,24 @@ #define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */ /* EBC stuff */ -#define CFG_NAND_ADDR 0xE0000000 +#if !defined(CONFIG_ARCHES) #define CFG_BCSR_BASE 0xE1000000 -#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */ -#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */ +#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */ +#define CFG_FLASH_SIZE (64 << 20) +#else +#define CFG_FPGA_BASE 0xE1000000 +#define CFG_CPLD_ADDR (CFG_FPGA_BASE + 0x00080000) +#define CFG_CPLD_DATA (CFG_FPGA_BASE + 0x00080002) +#define CFG_FLASH_BASE 0xFE000000 /* later mapped to this addr */ +#define CFG_FLASH_SIZE (32 << 20) +#endif + +#define CFG_NAND_ADDR 0xE0000000 +#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */ #define CFG_FLASH_BASE_PHYS_H 0x4 #define CFG_FLASH_BASE_PHYS_L 0xCC000000 #define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \ (u64)CFG_FLASH_BASE_PHYS_L) -#define CFG_FLASH_SIZE (64 << 20) #define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */ #define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */ @@ -223,6 +242,7 @@ * DDR SDRAM *----------------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) +#if !defined(CONFIG_ARCHES) /* * NAND booting U-Boot version uses a fixed initialization, since the whole * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot @@ -232,7 +252,70 @@ #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ -#endif + +#else /* defined(CONFIG_ARCHES) */ + +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ + +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A + +/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CFG_SDRAM_R0BAS 0x0000f000 +#define CFG_SDRAM_R1BAS 0x00000000 +#define CFG_SDRAM_R2BAS 0x00000000 +#define CFG_SDRAM_R3BAS 0x00000000 +#define CFG_SDRAM_PLBADDULL 0x00000000 +#define CFG_SDRAM_PLBADDUHB 0x00000008 +#define CFG_SDRAM_CONF1LL 0x00001080 +#define CFG_SDRAM_CONF1HB 0x00001080 +#define CFG_SDRAM_CONFPATHB 0x10a68000 + +/* SDRAM Controller */ +#define CFG_SDRAM0_MB0CF 0x00000701 +#define CFG_SDRAM0_MB1CF 0x00000000 +#define CFG_SDRAM0_MB2CF 0x00000000 +#define CFG_SDRAM0_MB3CF 0x00000000 +#define CFG_SDRAM0_MCOPT1 0x05322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01000000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_MODT2 0x00000000 +#define CFG_SDRAM0_MODT3 0x00000000 +#define CFG_SDRAM0_CODT 0x00800021 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xb5380000 +#define CFG_SDRAM0_INITPLR1 0x82100400 +#define CFG_SDRAM0_INITPLR2 0x80820000 +#define CFG_SDRAM0_INITPLR3 0x80830000 +#define CFG_SDRAM0_INITPLR4 0x80810040 +#define CFG_SDRAM0_INITPLR5 0x80800532 +#define CFG_SDRAM0_INITPLR6 0x82100400 +#define CFG_SDRAM0_INITPLR7 0x8a080000 +#define CFG_SDRAM0_INITPLR8 0x8a080000 +#define CFG_SDRAM0_INITPLR9 0x8a080000 +#define CFG_SDRAM0_INITPLR10 0x8a080000 +#define CFG_SDRAM0_INITPLR11 0x80000432 +#define CFG_SDRAM0_INITPLR12 0x808103c0 +#define CFG_SDRAM0_INITPLR13 0x80810040 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000257 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x03000091 +#define CFG_SDRAM0_CLKTR 0x40000000 +#define CFG_SDRAM0_WRDTR 0x82000823 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x42204243 +#define CFG_SDRAM0_SDTR3 0x090c0d1a +#define CFG_SDRAM0_MMODE 0x00000432 +#define CFG_SDRAM0_MEMODE 0x00000004 +#endif /* !defined(CONFIG_ARCHES) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) */ + #define CFG_MBYTES_SDRAM 512 /* 512MB */ /*----------------------------------------------------------------------- @@ -255,18 +338,27 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 +#if defined(CONFIG_ARCHES) +#define CFG_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */ +#endif + +#if !defined(CONFIG_ARCHES) /* RTC configuration */ #define CONFIG_RTC_M41T62 1 #define CFG_I2C_RTC_ADDR 0x68 +#endif /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 1 + #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 + +#if !defined(CONFIG_ARCHES) +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 /* Only Glacier (460GT) has 4 EMAC interfaces */ #ifdef CONFIG_460GT #define CONFIG_PHY2_ADDR 2 @@ -275,6 +367,30 @@ #define CONFIG_HAS_ETH3 #endif +#else /* defined(CONFIG_ARCHES) */ + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY +#define CONFIG_PHY1_ADDR 0 +#define CONFIG_PHY2_ADDR 1 +#define CONFIG_HAS_ETH2 + +#define CFG_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CFG_FIXED_PHY_PORTS \ + CFG_FIXED_PHY_PORT(0, 1000, FULL) + +#define CONFIG_M88E1112_PHY + +/* + * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not + * used by CONFIG_PHYx_ADDR + */ +#define CONFIG_GPCS_PHY_ADDR 0xA +#define CONFIG_GPCS_PHY1_ADDR 0xB +#define CONFIG_GPCS_PHY2_ADDR 0xC +#endif /* !defined(CONFIG_ARCHES) */ + #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_DYNAMIC_ANEG 1 @@ -297,7 +413,8 @@ /* * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#if !defined(CONFIG_ARCHES) +#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ @@ -308,20 +425,46 @@ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" +#else /* defined(CONFIG_ARCHES) */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fe000000\0" \ + "fdt_addr=fe1e0000\0" \ + "ramdisk_addr=fe200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "ethprime=ppc_4xx_eth1\0" \ + "" +#endif /* !defined(CONFIG_ARCHES) */ /* * Commands additional to the ones defined in amcc-common.h */ +#if defined(CONFIG_ARCHES) +#define CONFIG_CMD_DTT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#elif defined(CONFIG_CANYONLANDS) #define CONFIG_CMD_DATE #define CONFIG_CMD_DTT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP -#ifdef CONFIG_460EX -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_USB +#elif defined(CONFIG_GLACIER) +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP +#else +#error "board type not defined" #endif /* Partitions */ @@ -345,6 +488,36 @@ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#ifdef CONFIG_460GT +#if defined(CONFIG_ARCHES) +/*----------------------------------------------------------------------- + * RapidIO I/O and Registers + *----------------------------------------------------------------------*/ +#define CONFIG_RAPIDIO +#define CFG_460GT_SRIO_ERRATA_1 + +#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */ +#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */ +#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */ +#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */ +#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */ + +#define CFG_SRGPL0_REG_BAR 0xAA000000 /* 16MB */ +#define CFG_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */ +#define CFG_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */ +#define CFG_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */ + +#define CFG_I2ODMA_BASE 0xCF000000 +#define CFG_I2ODMA_PHYS_ADDR 0x0000000400100000ull + +#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE +#undef CONFIG_PPC4XX_RAPIDIO_DEBUG +#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM +#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB +#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK +#endif /* CONFIG_ARCHES */ +#endif /* CONFIG_460GT */ + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -357,6 +530,11 @@ * EBC address which accepts bigger regions: * * 0xfc00.0000 -> 4.cc00.0000 + * + * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be + * remapped to: + * + * 0xfe00.0000 -> 4.ce00.0000 */ #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) @@ -372,15 +550,26 @@ #define CFG_EBC_PB0AP 0x10055e00 #define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000) +#if !defined(CONFIG_ARCHES) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ #endif +#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ +#if !defined(CONFIG_ARCHES) /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x00804240 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */ +#else /* defined(CONFIG_ARCHES) */ + +/* Memory Bank 1 (FPGA) initialization */ +#define CFG_EBC_PB1AP 0x7f8ffe80 +#define CFG_EBC_PB1CR (CFG_FPGA_BASE | 0x3a000) +/* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/ +#endif /* !defined(CONFIG_ARCHES) */ + #define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */ /* diff --git a/include/ppc440.h b/include/ppc440.h index be8d3ff..7ffc640 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1349,6 +1349,9 @@ #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10 #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 +/* Ethernet Status Register */ +#define SDR0_ETH_STS 0x4104 + /* Miscealleneaous Function Reg. (SDR0_MFR) */ #define SDR0_MFR 0x4300 #define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */ -- 1.5.5

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Re: [U-Boot] Run hello world with Uboot !
by Wolfgang Denk 08 Oct '08

08 Oct '08

Dear "Mathieu Dube", please keep the ML on Cc: ! In message <c5ee099c0810070917s7bd8d0dey9908f41419c3c03d(a)mail.gmail.com> you wrote: > > > Did you read the FAQ??? > > this entry?: > > http://www.denx.de/wiki/view/DULG/MyStandaloneProgramDoesNotWork Yes, this entry. > if I nm(with the correct toolchain) the executable > > it gives me 0c100000 T hello_world > > so I go 0x8c100000 > > still crashes. HM. I'm not really surprised. For me, 0x8c100000 is not the same as 0x0c100000. For me, that makes a difference of 2 GB. > is there another way to find the exact entry point? "nm" is a good way. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Q: Do you know what the death rate around here is? A: One per person.

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Re: [U-Boot] [PATCH 1/1 v2] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
by Victor Gallardo 08 Oct '08

08 Oct '08

OK. Thanks Stefan. > > We will take a look. > > Thanks. > > > Yes, we ran the test as you mentioned (bootcmd=reset) on both versions of > > the Kilauea board and let it run for 24 hours without any problems. > > Hopefully we can reproduce the problem you are seeing. > > I suggest that you use some means to cool down the board and heat it up a > little bit, to see if it fails in some temperature ranges. > > It happend here with a "cold" board. I powered it on again: ... > > I suggest that you use the same object I used. Please find it attached.

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[U-Boot] PATCH: IXP465 support and some IXP4xx rework, Sidewinder board support
by h.sattler＠erhardt-leimer.com 08 Oct '08

08 Oct '08

Hi, on the matter of getting u-boot work with the ADI Sidewinder Reference Platform, I found the previously posted patches and used them as starting point for my own patch set. The Sidewinder board works with this patch, including ECC (optional). There is a minimum set of ifdefs in cpu/ixp/start.S and no board-specific low-level.S and thus no endless code-duplication. The SDRAM parameters are handled by configuration definitions. The ixp425.h and ixp465.h header files should be merged but that can follow in a different patch, possibly renaming the defines and fixing all board specific code. The new initialisation routine was also tested on an IXP425, it really works on both. The npe_less_fw.patch allows to have NPE-C firmware and still use NPE-B. There is no need to load firmware to NPE-C if you are not going to use it. This work was done for Erhardt+Leimer GmbH. Note: I hope this can be merged, however, your description at http://www.denx.de/wiki/U-Boot/Patches makes me worry. I can only use Lotus Notes and that's a bit limited. No, I cannot use another MUA from here, really! If you can accept them at attachments (patches with description header, diff index and Signed-off-by line, I use quilt locallly). Sincerly, Hendrik Sattler PS: please CC on answers as I am not subscribed.

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