October 2008 - U-Boot

[U-Boot] [PATCH 07/12 v2] ARM: OMAP3: Add memory and syslib common files, add NAND support
by dirk.behme＠googlemail.com 07 Oct '08

07 Oct '08

Subject: [PATCH 07/12 v2] ARM: OMAP3: Add memory and syslib common files, add NAND support From: Dirk Behme <dirk.behme(a)gmail.com> Add memory and syslib common files, add NAND support Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v2: - Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang. common/cmd_nand.c | 29 ++ cpu/arm_cortexa8/omap3/Makefile | 2 cpu/arm_cortexa8/omap3/mem.c | 301 ++++++++++++++++++++++++++++++ cpu/arm_cortexa8/omap3/nand.c | 399 ++++++++++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/omap3/syslib.c | 72 +++++++ drivers/mtd/nand/nand_base.c | 145 ++++++++++++++ examples/Makefile | 6 7 files changed, 951 insertions(+), 3 deletions(-) Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c =================================================================== --- /dev/null +++ u-boot-arm/cpu/arm_cortexa8/omap3/mem.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Manikandan Pillai <mani.pillai(a)ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <command.h> + +/* Only One NAND allowed on board at a time. + * The GPMC CS Base for the same + */ +unsigned int boot_flash_base; +unsigned int boot_flash_off; +unsigned int boot_flash_sec; +unsigned int boot_flash_type; +volatile unsigned int boot_flash_env_addr; + +/* help common/env_flash.c */ +#ifdef ENV_IS_VARIABLE + +uchar(*boot_env_get_char_spec) (int index); +int (*boot_env_init) (void); +int (*boot_saveenv) (void); +void (*boot_env_relocate_spec) (void); + +/* 16 bit NAND */ +uchar env_get_char_spec(int index); +int env_init(void); +int saveenv(void); +void env_relocate_spec(void); +extern char *env_name_spec; + +#if defined(CONFIG_CMD_NAND) +u8 is_nand; +#endif + +#if defined(CONFIG_CMD_ONENAND) +u8 is_onenand; +#endif + +#endif /* ENV_IS_VARIABLE */ + +#if defined(CONFIG_CMD_NAND) +static u32 gpmc_m_nand[GPMC_MAX_REG] = { + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0 +}; +unsigned int nand_cs_base; +#endif + +#if defined(CONFIG_CMD_ONENAND) +static u32 gpmc_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, 0 +}; +unsigned int onenand_cs_base; + +#endif + +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0; + + __raw_writel(0x0, addr + 0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = __raw_readl(addr + 0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed */ + return 0; + else + return 1; +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ + /* only init up first bank here */ + do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); +} + +/************************************************************************* + * do_sdrc_init(): initialize the SDRAM for use. + * -code sets up SDRAM basic SDRC timings for CS0 + * -optimal settings can be placed here, or redone after i2c + * inspection of board info + * + * - code called ones in C-Stack only context for CS0 and a possible 2nd + * time depending on memory configuration from stack+global context + **************************************************************************/ + +void do_sdrc_init(u32 offset, u32 early) +{ + + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + /* SDRC_MCFG0 register */ + (*(unsigned int *) 0x6D000080) = 0x02584099; /* from Micron */ + + /* SDRC_RFR_CTRL0 register */ + (*(unsigned int *) 0x6D0000a4) = 0x54601; /* for 166M */ + + /* SDRC_ACTIM_CTRLA0 register */ + (*(unsigned int *) 0x6D00009c) = 0xa29db4c6; /* for 166M */ + + /* SDRC_ACTIM_CTRLB0 register */ + (*(unsigned int *) 0x6D0000a0) = 0x12214; /* for 166M */ + + /* Disble Power Down of CKE cuz of 1 CKE on combo part */ + (*(unsigned int *) 0x6D000070) = 0x00000081; + + /* SDRC_Manual command register */ + (*(unsigned int *) 0x6D0000a8) = 0x00000000; /* NOP command */ + (*(unsigned int *) 0x6D0000a8) = 0x00000001; /* Precharge command */ + (*(unsigned int *) 0x6D0000a8) = 0x00000002; /* Auto-refresh command */ + (*(unsigned int *) 0x6D0000a8) = 0x00000002; /* Auto-refresh command */ + + /* SDRC MR0 register */ + (*(int *) 0x6D000084) = 0x00000032; /* Burst length = 4 */ + /* CAS latency = 3, Write Burst = Read Burst Serial Mode */ + + /* SDRC DLLA control register */ + (*(unsigned int *) 0x6D000060) = 0x0000A; + sdelay(0x20000); +} + +void enable_gpmc_config(u32 *gpmc_config, u32 gpmc_base, u32 base, u32 size) +{ + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + sdelay(2000); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + /* putting a blanket check on GPMC based on ZeBu for now */ + u32 mux = 0, mwidth; + u32 *gpmc_config = NULL; + u32 gpmc_base = 0; + u32 base = 0; + u32 size = 0; + u32 f_off = CONFIG_SYS_MONITOR_LEN; + u32 f_sec = 0; + u32 config = 0; + + mux = BIT9; + mwidth = get_gpmc0_width(); + + /* global settings */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ + + config = __raw_readl(GPMC_CONFIG); + config &= (~0xf00); + __raw_writel(config, GPMC_CONFIG); + + /* Disable the GPMC0 config set by ROM code + * It conflicts with our MPDB (both at 0x08000000) + */ + __raw_writel(0, GPMC_CONFIG7 + GPMC_CONFIG_CS0); + sdelay(1000); + +#if defined(CONFIG_CMD_NAND) /* CS 0 */ + gpmc_config = gpmc_m_nand; +#if defined(CONFIG_ENV_IS_IN_NAND) + gpmc_base = GPMC_CONFIG_CS0 + (0 * GPMC_CONFIG_WIDTH); +#else + gpmc_base = GPMC_CONFIG_CS0 + (1 * GPMC_CONFIG_WIDTH); +#endif + base = PISMO1_NAND_BASE; + size = PISMO1_NAND_SIZE; + enable_gpmc_config(gpmc_config, gpmc_base, base, size); + is_nand = 1; + nand_cs_base = gpmc_base; +#if defined(CONFIG_ENV_IS_IN_NAND) + f_off = SMNAND_ENV_OFFSET; + f_sec = SZ_128K; + /* env setup */ + boot_flash_base = base; + boot_flash_off = f_off; + boot_flash_sec = f_sec; + boot_flash_env_addr = f_off; +#endif +#endif + +#if defined(CONFIG_CMD_ONENAND) + gpmc_config = gpmc_onenand; +#if defined(CONFIG_ENV_IS_IN_ONENAND) + gpmc_base = GPMC_CONFIG_CS0 + (0 * GPMC_CONFIG_WIDTH); +#else + gpmc_base = GPMC_CONFIG_CS0 + (1 * GPMC_CONFIG_WIDTH); +#endif + base = PISMO1_ONEN_BASE; + size = PISMO1_ONEN_SIZE; + enable_gpmc_config(gpmc_config, gpmc_base, base, size); + is_onenand = 1; + onenand_cs_base = gpmc_base; +#if defined(CONFIG_ENV_IS_IN_ONENAND) + f_off = ONENAND_ENV_OFFSET; + f_sec = SZ_128K; + /* env setup */ + boot_flash_base = base; + boot_flash_off = f_off; + boot_flash_sec = f_sec; + boot_flash_env_addr = f_off; +#endif +#endif + +#ifdef ENV_IS_VARIABLE + boot_env_get_char_spec = env_get_char_spec; + boot_env_init = env_init; + boot_saveenv = saveenv; + boot_env_relocate_spec = env_relocate_spec; +#endif +} Index: u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c =================================================================== --- /dev/null +++ u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} Index: u-boot-arm/cpu/arm_cortexa8/omap3/nand.c =================================================================== --- /dev/null +++ u-boot-arm/cpu/arm_cortexa8/omap3/nand.c @@ -0,0 +1,399 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> + * Rohit Choraria <rohitkc(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <linux/mtd/nand_ecc.h> + +#if defined(CONFIG_CMD_NAND) + +#include <nand.h> + +unsigned char cs; +volatile unsigned long gpmc_cs_base_add; + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +#define ECC_P1_128_E(val) ((val) & 0x000000FF) /* Bit 0 to 7 */ +#define ECC_P512_2048_E(val) (((val) & 0x00000F00)>>8) /* Bit 8 to 11 */ +#define ECC_P1_128_O(val) (((val) & 0x00FF0000)>>16) /* Bit 16 to Bit 23 */ +#define ECC_P512_2048_O(val) (((val) & 0x0F000000)>>24) /* Bit 24 to Bit 27 */ + +/* + * omap_nand_hwcontrol - Set the address pointers corretly for the + * following address/data/command operation + */ +static void omap_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + register struct nand_chip *this = mtd->priv; + + /* Point the IO_ADDR to DATA and ADDRESS registers instead + of chip address */ + switch (ctrl) { + case NAND_CTRL_CHANGE | NAND_CTRL_CLE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTRL_CHANGE | NAND_CTRL_ALE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTRL_CHANGE | NAND_NCE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +/* + * omap_nand_wait - called primarily after a program/erase operation + * so that we access NAND again only after the device + * is ready again. + * @mtd: MTD device structure + * @chip: nand_chip structure + */ +static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + register struct nand_chip *this = mtd->priv; + int status = 0; + + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + /* Send the status command and loop until the device is free */ + while (!(status & 0x40)) { + __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); + status = __raw_readb(this->IO_ADDR_R); + } + return status; +} + +#ifdef CONFIG_SYS_NAND_WIDTH_16 +/* + * omap_nand_write_buf16 - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 16bit buswith + */ +static void omap_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i = 0; i < len; i++) { + writew(p[i], this->IO_ADDR_W); + while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL)) ; + } +} + +/* + * nand_read_buf16 - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 16bit buswith + */ +static void omap_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i = 0; i < len; i++) + p[i] = readw(this->IO_ADDR_R); +} + +#else +/* + * omap_nand_write_buf - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + */ +static void omap_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + int i; + int j = 0; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) { + writeb(buf[i], chip->IO_ADDR_W); + for (j = 0; j < 10; j++) ; + } + +} + +/* + * omap_nand_read_buf - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + */ +static void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + int j = 0; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) { + buf[i] = readb(chip->IO_ADDR_R); + while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL)); + } +} +#endif /* CONFIG_SYS_NAND_WIDTH_16 */ + +/* + * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in + * GPMC controller + * @mtd: MTD device structure + * + */ +static void omap_hwecc_init(struct nand_chip *chip) +{ + unsigned long val = 0x0; + + /* Init ECC Control Register */ + /* Clear all ECC | Enable Reg1 */ + val = ((0x00000001 << 8) | 0x00000001); + __raw_writel(val, GPMC_BASE + GPMC_ECC_CONTROL); + __raw_writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG); +} + +/* + * omap_correct_data - Compares the ecc read from nand spare area with + * ECC registers values + * and corrects one bit error if it has occured + * @mtd: MTD device structure + * @dat: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from ECC registers + */ +static int omap_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + return 0; +} + +/* + * omap_calculate_ecc - Generate non-inverted ECC bytes. + * + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer + */ +static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + unsigned long val = 0x0; + unsigned long reg; + + /* Start Reading from HW ECC1_Result = 0x200 */ + reg = (unsigned long) (GPMC_BASE + GPMC_ECC1_RESULT); + val = __raw_readl(reg); + + *ecc_code++ = ECC_P1_128_E(val); + *ecc_code++ = ECC_P1_128_O(val); + *ecc_code++ = ECC_P512_2048_E(val) | ECC_P512_2048_O(val) << 4; + + return 0; +} + +/* + * omap_enable_ecc - This function enables the hardware ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void omap_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *chip = mtd->priv; + unsigned int val = __raw_readl(GPMC_BASE + GPMC_ECC_CONFIG); + unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + + switch (mode) { + case NAND_ECC_READ: + __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width | CS | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1); + break; + case NAND_ECC_READSYN: + __raw_writel(0x100, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width | CS | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1); + break; + case NAND_ECC_WRITE: + __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width | CS | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1); + break; + default: + printf("Error: Unrecognized Mode[%d]!\n", mode); + break; + } + + __raw_writel(val, GPMC_BASE + GPMC_ECC_CONFIG); +} + +static struct nand_ecclayout hw_nand_oob_64 = { + .eccbytes = 12, + .eccpos = { + 2, 3, 4, 5, + 6, 7, 8, 9, + 10, 11, 12, 13}, + .oobfree = { {20, 50} } /* don't care */ +}; + +static struct nand_ecclayout sw_nand_oob_64 = { + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { {2, 38} } +}; + +void omap_nand_switch_ecc(struct mtd_info *mtd, int hardware) +{ + struct nand_chip *nand = mtd->priv; + + if (!hardware) { + nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = &sw_nand_oob_64; + nand->ecc.size = 256; /* set default eccsize */ + nand->ecc.bytes = 3; + nand->ecc.steps = 8; + nand->ecc.hwctl = 0; + nand->ecc.calculate = nand_calculate_ecc; + nand->ecc.correct = nand_correct_data; + } else { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_nand_oob_64; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = 4; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + omap_hwecc_init(nand); + } + nand_switch_ecc(mtd); + + if (nand->options & NAND_BUSWIDTH_16) { + mtd->oobavail = mtd->oobsize - (nand->ecc.layout->eccbytes + 2); + if (nand->ecc.layout->eccbytes & 0x01) + mtd->oobavail--; + } else + mtd->oobavail = mtd->oobsize - (nand->ecc.layout->eccbytes + 1); +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +int board_nand_init(struct nand_chip *nand) +{ + int gpmc_config = 0; + cs = 0; + while (cs <= GPMC_MAX_CS) { + /* Each GPMC set for a single CS is at offset 0x30 */ + /* already remapped for us */ + gpmc_cs_base_add = (GPMC_CONFIG_CS0 + (cs * 0x30)); + /* xloader/Uboot would have written the NAND type for us + * NOTE: This is a temporary measure and cannot handle ONENAND. + * The proper way of doing this is to pass the setup of + * u-boot up to kernel using kernel params - something on + * the lines of machineID + */ + /* Check if NAND type is set */ + if ((__raw_readl(gpmc_cs_base_add + GPMC_CONFIG1) & 0xC00) == + 0x800) { + /* Found it!! */ + break; + } + cs++; + } + if (cs > GPMC_MAX_CS) { + printf("NAND: Unable to find NAND settings in " \ + "GPMC Configuration - quitting\n"); + } + + gpmc_config = __raw_readl(GPMC_CONFIG); + /* Disable Write protect */ + gpmc_config |= 0x10; + __raw_writel(gpmc_config, GPMC_CONFIG); + + nand->IO_ADDR_R = (int *) gpmc_cs_base_add + GPMC_NAND_DAT; + nand->IO_ADDR_W = (int *) gpmc_cs_base_add + GPMC_NAND_CMD; + + nand->cmd_ctrl = omap_nand_hwcontrol; + nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR | + NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR; + nand->read_buf = omap_nand_read_buf; + nand->write_buf = omap_nand_write_buf; + nand->ecc.mode = NAND_ECC_SOFT; + /* if RDY/BSY line is connected to OMAP then use the omap ready + * function and the generic nand_wait function which reads the + * status register after monitoring the RDY/BSY line. Otherwise + * use a standard chip delay which is slightly more than tR + * (AC Timing) of the NAND device and read the status register + * until you get a failure or success + */ + nand->waitfunc = omap_nand_wait; + nand->chip_delay = 50; + + return 0; +} +#endif /* CONFIG_CMD_NAND */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/Makefile +++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(SOC).a SOBJS := lowlevel_init.o -OBJS := sys_info.o board.o clock.o interrupts.o +OBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o nand.o all: .depend $(LIB) Index: u-boot-arm/examples/Makefile =================================================================== --- u-boot-arm.orig/examples/Makefile +++ u-boot-arm/examples/Makefile @@ -30,10 +30,12 @@ LOAD_ADDR = 0x40000 endif ifeq ($(ARCH),arm) +LOAD_ADDR = 0xc100000 ifeq ($(BOARD),omap2420h4) LOAD_ADDR = 0x80300000 -else -LOAD_ADDR = 0xc100000 +endif +ifeq ($(CPU),omap3) +LOAD_ADDR = 0x80300000 endif endif Index: u-boot-arm/common/cmd_nand.c =================================================================== --- u-boot-arm.orig/common/cmd_nand.c +++ u-boot-arm/common/cmd_nand.c @@ -38,6 +38,11 @@ int find_dev_and_part(const char *id, st u8 *part_num, struct part_info **part); #endif +#if defined(CONFIG_OMAP) && (defined(CONFIG_OMAP3_BEAGLE)\ + || defined(CONFIG_OMAP3_EVM) || defined(CONFIG_OVERO)) +extern void omap_nand_switch_ecc(nand_info_t *nand, int hardware); +#endif + static int nand_dump(nand_info_t *nand, ulong off, int only_oob) { int i; @@ -234,6 +239,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && strcmp(cmd, "biterr") != 0 && +#if defined(CONFIG_OMAP) && (defined(CONFIG_OMAP3_BEAGLE)\ + || defined(CONFIG_OMAP3_EVM) || defined(CONFIG_OVERO)) + strncmp(cmd, "ecc", 3) != 0 && +#endif strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) goto usage; @@ -318,6 +327,22 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, } +#if defined(CONFIG_OMAP) && (defined(CONFIG_OMAP3_BEAGLE) \ + || defined(CONFIG_OMAP3_EVM) || defined(CONFIG_OVERO)) + if (strncmp(cmd, "ecc", 3) == 0) { + if (argc < 2) + goto usage; + if (strncmp(argv[2], "hw", 2) == 0) + omap_nand_switch_ecc(nand, 1); + else if (strncmp(argv[2], "sw", 2) == 0) + omap_nand_switch_ecc(nand, 0); + else + goto usage; + + return 0; + } +#endif + if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { int read; @@ -483,6 +508,10 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" +#if defined(CONFIG_OMAP) && (defined(CONFIG_OMAP3_BEAGLE) \ + || defined(CONFIG_OMAP3_EVM) || defined(CONFIG_OVERO)) + "nand ecc [hw/sw] - switch the ecc calculation algorithm \n" +#endif "nand lock [tight] [status]\n" " bring nand to lock state or display locked pages\n" "nand unlock [offset] [size] - unlock section\n"); Index: u-boot-arm/drivers/mtd/nand/nand_base.c =================================================================== --- u-boot-arm.orig/drivers/mtd/nand/nand_base.c +++ u-boot-arm/drivers/mtd/nand/nand_base.c @@ -2730,6 +2730,151 @@ int nand_scan_tail(struct mtd_info *mtd) return 0; } +#if defined(CONFIG_OMAP) && (defined(CONFIG_OMAP3_BEAGLE) \ + || defined(CONFIG_OMAP3_EVM) || defined(CONFIG_OVERO)) +void nand_switch_ecc(struct mtd_info *mtd) +{ + int i; + struct nand_chip *chip = mtd->priv; + + if (!chip->buffers) + return; + + switch (chip->ecc.mode) { + case NAND_ECC_HW: + /* Use standard hwecc read page function ? */ + chip->ecc.read_page = nand_read_page_hwecc; + chip->ecc.write_page = nand_write_page_hwecc; + chip->ecc.read_oob = nand_read_oob_std; + chip->ecc.write_oob = nand_write_oob_std; + break; + case NAND_ECC_HW_SYNDROME: + if ((!chip->ecc.calculate || !chip->ecc.correct || + !chip->ecc.hwctl) && + (!chip->ecc.read_page || + chip->ecc.read_page == nand_read_page_hwecc || + !chip->ecc.write_page || + chip->ecc.write_page == nand_write_page_hwecc)) { + printk(KERN_WARNING "No ECC functions supplied, " + "Hardware ECC not possible\n"); + BUG(); + } + /* Use standard syndrome read/write page function ? */ + chip->ecc.read_page = nand_read_page_syndrome; + chip->ecc.write_page = nand_write_page_syndrome; + chip->ecc.read_oob = nand_read_oob_syndrome; + chip->ecc.write_oob = nand_write_oob_syndrome; + + if (mtd->writesize >= chip->ecc.size) + break; + printk(KERN_WARNING "%d byte HW ECC not possible on " + "%d byte page size, fallback to SW ECC\n", + chip->ecc.size, mtd->writesize); + chip->ecc.mode = NAND_ECC_SOFT; + break; + case NAND_ECC_SOFT: + chip->ecc.calculate = nand_calculate_ecc; + chip->ecc.correct = nand_correct_data; + chip->ecc.read_page = nand_read_page_swecc; + chip->ecc.write_page = nand_write_page_swecc; + chip->ecc.read_oob = nand_read_oob_std; + chip->ecc.write_oob = nand_write_oob_std; + chip->ecc.size = 256; + chip->ecc.bytes = 3; + break; + + case NAND_ECC_NONE: + printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " + "This is not recommended !!\n"); + chip->ecc.read_page = nand_read_page_raw; + chip->ecc.write_page = nand_write_page_raw; + chip->ecc.read_oob = nand_read_oob_std; + chip->ecc.write_oob = nand_write_oob_std; + chip->ecc.size = mtd->writesize; + chip->ecc.bytes = 0; + break; + + default: + printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", + chip->ecc.mode); + BUG(); + } + /* + * The number of bytes available for a client to place data into + * the out of band area + */ + chip->ecc.layout->oobavail = 0; + for (i = 0; chip->ecc.layout->oobfree[i].length; i++) + chip->ecc.layout->oobavail += + chip->ecc.layout->oobfree[i].length; + mtd->oobavail = chip->ecc.layout->oobavail; + + /* + * Set the number of read / write steps for one page depending on ECC + * mode + */ + chip->ecc.steps = mtd->writesize / chip->ecc.size; + if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { + printk(KERN_WARNING "Invalid ecc parameters\n"); + BUG(); + } + chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; + + /* + * Allow subpage writes up to ecc.steps. Not possible for MLC + * FLASH. + */ + if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && + !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { + switch (chip->ecc.steps) { + case 2: + mtd->subpage_sft = 1; + break; + case 4: + case 8: + mtd->subpage_sft = 2; + break; + } + } + chip->subpagesize = mtd->writesize >> mtd->subpage_sft; + + /* Initialize state */ + chip->state = FL_READY; + + /* De-select the device */ + chip->select_chip(mtd, -1); + + /* Invalidate the pagebuffer reference */ + chip->pagebuf = -1; + + /* Fill in remaining MTD driver data */ + mtd->type = MTD_NANDFLASH; + mtd->flags = MTD_CAP_NANDFLASH; + mtd->erase = nand_erase; + mtd->point = NULL; + mtd->unpoint = NULL; + mtd->read = nand_read; + mtd->write = nand_write; + mtd->read_oob = nand_read_oob; + mtd->write_oob = nand_write_oob; + mtd->sync = nand_sync; + mtd->lock = NULL; + mtd->unlock = NULL; + mtd->suspend = nand_suspend; + mtd->resume = nand_resume; + mtd->block_isbad = nand_block_isbad; + mtd->block_markbad = nand_block_markbad; + + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = chip->ecc.layout; + + /* Check, if we should skip the bad block table scan */ + if (chip->options & NAND_SKIP_BBTSCAN) + chip->options |= NAND_BBT_SCANNED; + +} +#endif + /* module_text_address() isn't exported, and it's mostly a pointless test if this is a module _anyway_ -- they'd have to try _really_ hard to call us from in-kernel code if the core NAND support is modular. */

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[U-Boot] [PATCH 0/3] iMX31: Add iMX31 support to boots from NAND
by Alan Carvalho de Assis 07 Oct '08

07 Oct '08

This serie of patches adds support to iMX31PDK board to boot directly from NAND. Notice these patches don't add support to MTD NAND Flash support to U-Boot (like reading and saving environment parameters in Flash because MTD NAND Flash driver still needs further revision). For people willing to test it follow these simple steps: Create a local copy of u-boot-arm/testing: $ git clone git://git.denx.de/u-boot-arm-next.git u-boot-arm $ cd u-boot-arm $ git checkout -b local_test origin/testing Apply patches: $ patch -p1 < ../0001-iMX31-Reducing-start.S-size-to-let-boot-from-NAND.patch $ patch -p1 < ../0002-iMX31-Add-support-to-copy-NAND-Flash-code-to-RAM.patch $ patch -p1 < ../0003-iMX31-Add-support-to-iMX31PDK-board-and-let-it-boot.patch Set up your cross-compile (we are using one from LTIB): $ export PATH="$PATH:/opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/" $ export CROSS_COMPILE=arm-none-linux-gnueabi- Compile U-Boot to iMX31PDK board: $ make mx31pdk_config $ make Flash u-boot.bin to NAND flash (we are using ATK to do that)es doesn't add U-Boot support to erase/write on NAND. These patches will be applied against u-boot-arm/testing, against Magnus Lilja patches. Thanks to Kenneth Johansson about the idea to reduce start.S size. Thanks very much to Magnus Lilja and Fabio Estevam for all the help testing these patches.

1 0

Re: [U-Boot] how can i change u-boot load address?
by Gururaja Hebbar K R 07 Oct '08

07 Oct '08

Hi, >I seem to understand that remapping, being a CPU specific and >depending on a way U-Boot starts (either from ROM or RAM), is taken >away in 'lowlevel_init' function, defined either in in >$(uboot)/cpu/arm/$(soc)/lowlevel_init.S (for example, >$(uboot)/cpu/arm920t/ks8695/) or in >$(uboot)/board/board_name/lowlevel_init.S, but what confuses me is >that I couldn't find remap functions on every ARM platform, running >from ROM at reset. U wouldnt see mapping the vector on (most) ARM Platforms because they use u-boot as secondary bootloader Initial Arm Bootmonitor would run & that would re-locate the U-boot to ram & then give control to u-boot I said "most" because ARM Integrator Board doesnt use Arm Bootmonitor & hence its code has remapping functionality. Kindly look at $(uboot)/board/integratorcp/lowlevel_init.S & $(uboot)/board/integratorcp/integratorcp.c. It needs CONFIG_CM_REMAP setting to be defined For the board that i am using, i had to make use of this. Hope this helps Regards Gururaja

2 2

[U-Boot] [PATCH 1/3 v2] ppc4xx: Add AMCC Arches board support (dual 460GT)
by Adam Graham 07 Oct '08

07 Oct '08

The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham(a)amcc.com> Signed-off-by: Victor Gallardo <vgallardo(a)amcc.com> --- v2: - Added Arches (460GT) support to the existing Canyonlands (460) board files since the Canyonlands board files support all current AMCC PPC460EX/GT boards. MAKEALL | 1 + Makefile | 3 +- board/amcc/canyonlands/canyonlands.c | 143 ++++++++++++++++++++ board/amcc/canyonlands/init.S | 17 +++ include/configs/amcc-common.h | 19 +++- include/configs/canyonlands.h | 242 +++++++++++++++++++++++++++++++--- include/ppc440.h | 3 + 7 files changed, 410 insertions(+), 18 deletions(-) diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..847c1fa 100755 --- a/MAKEALL +++ b/MAKEALL @@ -161,6 +161,7 @@ LIST_4xx=" \ alpr \ AP1000 \ AR405 \ + arches \ ASH405 \ bamboo \ bamboo_nand \ diff --git a/Makefile b/Makefile index 7c13ce8..2af11c4 100644 --- a/Makefile +++ b/Makefile @@ -1206,7 +1206,8 @@ bubinga_config: unconfig CANBT_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd -# Canyonlands & Glacier use different U-Boot images +# Arches, Canyonlands & Glacier use different U-Boot images +arches_config \ canyonlands_config \ glacier_config: unconfig @mkdir -p $(obj)include diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index e9eba49..3d39cbc 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -38,11 +38,52 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARD_CANYONLANDS_PCIE 1 #define BOARD_CANYONLANDS_SATA 2 #define BOARD_GLACIER 3 +#define BOARD_ARCHES 4 + +#if defined(CONFIG_ARCHES) +/* + * FPGA read/write helper macros + */ +static inline int board_fpga_read(int offset) +{ + int data; + + data = in_8((void *)(CFG_FPGA_BASE + offset)); + + return data; +} + +static inline void board_fpga_write(int offset, int data) +{ + out_8((void *)(CFG_FPGA_BASE + offset), data); +} + +/* + * CPLD read/write helper macros + */ +static inline int board_cpld_read(int offset) +{ + int data; + + out_8((void *)(CFG_CPLD_ADDR), offset); + data = in_8((void *)(CFG_CPLD_DATA)); + + return data; +} + +static inline void board_cpld_write(int offset, int data) +{ + out_8((void *)(CFG_CPLD_ADDR), offset); + out_8((void *)(CFG_CPLD_DATA), data); +} +#endif /* defined(CONFIG_ARCHES) */ int board_early_init_f(void) { +#if !defined(CONFIG_ARCHES) u32 sdr0_cust0; u32 pvr = get_pvr(); +#endif /* * Setup the interrupt controller polarities, triggers, etc. @@ -79,6 +120,7 @@ int board_early_init_f(void) mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic3sr, 0xffffffff); /* clear all */ +#if !defined(CONFIG_ARCHES) /* SDR Setting - enable NDFC */ mfsdr(SDR0_CUST0, sdr0_cust0); sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | @@ -88,6 +130,7 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_BAC_ENCODE(3) | (0x80000000 >> (28 + CFG_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); +#endif /* * Configure PFC (Pin Function Control) registers @@ -98,6 +141,7 @@ int board_early_init_f(void) /* Enable PCI host functionality in SDR0_PCI0 */ mtsdr(SDR0_PCI0, 0xe0000000); +#if !defined(CONFIG_ARCHES) /* Enable ethernet and take out of reset */ out_8((void *)CFG_BCSR_BASE + 6, 0); @@ -123,10 +167,12 @@ int board_early_init_f(void) gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); } +#endif return 0; } +#if !defined(CONFIG_ARCHES) static void canyonlands_sata_init(int board_type) { u32 reg; @@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type) SDR_WRITE(SDR0_SRST1, 0x00000000); } } +#endif /* !defined(CONFIG_ARCHES) */ + +int get_cpu_num(void) +{ + int cpu = __NA_OR_UNKNOWN_CPU; + +#if defined(CONFIG_ARCHES) + int cpu_num; + + cpu_num = board_fpga_read(0x3); + + /* sanity check; assume cpu numbering starts and increments from 0 */ + if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) + cpu = cpu_num; +#endif + + return cpu; +} +#if !defined(CONFIG_ARCHES) int checkboard(void) { char *s = getenv("serial#"); @@ -188,6 +253,35 @@ int checkboard(void) return (0); } +#else /* defined(CONFIG_ARCHES) */ + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); + printf(" Revision %02x.%02x ", + board_fpga_read(0x0), board_fpga_read(0x1)); + + gd->board_type = BOARD_ARCHES; + + /* Only CPU0 has access to CPLD registers */ + if (get_cpu_num() == 0) { + printf("(FPGA=%02x, CPLD=%02x)\n", + board_fpga_read(0x2), board_cpld_read(0x0)); + printf(" Configuration Switch 0x%02x\n", + board_cpld_read(0x1)); + } else + printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); + + + if (s != NULL) + printf(" Serial# %s\n", s); + + return 0; +} +#endif /* !defined(CONFIG_ARCHES) */ + /* * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. @@ -389,6 +483,7 @@ int board_early_init_r (void) return 0; } +#if !defined(CONFIG_ARCHES) int misc_init_r(void) { u32 sdr0_srst1 = 0; @@ -434,6 +529,54 @@ int misc_init_r(void) return 0; } +#else /* defined(CONFIG_ARCHES) */ + +int misc_init_r(void) +{ + u32 eth_cfg = 0; + u32 eth_pll; + u32 reg; + int timeout; + + /* + * Set EMAC mode/configuration (GMII, SGMII, RGMII...). + * This is board specific, so let's do it here. + */ + + /* enable SGMII mode */ + eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | + SDR0_ETH_CFG_SGMII1_ENABLE | + SDR0_ETH_CFG_SGMII2_ENABLE); + + /* Set EMAC for MDIO */ + eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; + + /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ + eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + + mtsdr(SDR0_ETH_CFG, eth_cfg); + + /* reset all SGMII interfaces */ + mfsdr(SDR0_SRST1, reg); + reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); + mtsdr(SDR0_SRST1, reg); + mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); + mtsdr(SDR0_SRST1, 0x00000000); + + for (timeout = 60; timeout > 0; timeout--) { + udelay(1000); + mfsdr(SDR0_ETH_PLL, eth_pll); + if ((eth_pll & SDR0_ETH_PLL_PLLLOCK) != 0) + break; + } + + if (timeout == 0) + printf("timeout: while waiting for SGMII PLL lock\n"); + + return 0; +} +#endif /* !defined(CONFIG_ARCHES) */ + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 258fb5d..12dead3 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -77,11 +77,16 @@ tlbtab: /* PCIe UTL register */ tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) +#if !defined(CONFIG_ARCHES) /* TLB-entry for NAND */ tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) /* TLB-entry for CPLD */ tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#else + /* TLB-entry for FPGA */ + tlbentry(CFG_FPGA_BASE, SZ_16M, CFG_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#endif /* TLB-entry for OCM */ tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) @@ -92,6 +97,18 @@ tlbtab: /* AHB: Internal USB Peripherals (USB, SATA) */ tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) +#if defined(CONFIG_RAPIDIO) + /* TLB-entries for RapidIO (SRIO) */ + tlbentry(CFG_SRGPL0_REG_BAR, SZ_16M, CFG_SRGPL0_REG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_SRGPL0_CFG_BAR, SZ_16M, CFG_SRGPL0_CFG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_SRGPL0_MNT_BAR, SZ_16M, CFG_SRGPL0_MNT_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_I2ODMA_BASE, SZ_1K, 0x00100000, + 0x4, AC_R|AC_W|SA_G|SA_I) +#endif + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 1f27d78..ee053fb 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -55,6 +55,13 @@ #endif /* + * Only very few boards have default netdev not set to eth0 (like Arches) + */ +#if !defined(CONFIG_NETDEV) +#define CONFIG_NETDEV eth0 +#endif + +/* * Commands */ #include <config_cmd_default.h> @@ -147,9 +154,11 @@ /* * Booting and default environment */ +#if !defined(CONFIG_PREBOOT) #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" +#endif #define CONFIG_BOOTCOMMAND "run flash_self" /* @@ -184,7 +193,7 @@ * General common environment variables shared on all AMCC eval boards */ #define CONFIG_AMCC_DEF_ENV \ - "netdev=eth0\0" \ + "netdev=" xstr(CONFIG_NETDEV) "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -197,8 +206,10 @@ "initrd_high=30000000\0" \ "kernel_addr_r=400000\0" \ "fdt_addr_r=800000\0" \ + "ramdisk_addr_r=C00000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ CONFIG_AMCC_DEF_ENV_ROOTPATH /* @@ -214,6 +225,12 @@ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdt_file};" \ + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ + "net_self=run net_self_load;" \ + "run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" /* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 2f162e1..acad9b3 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -27,17 +27,53 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */ -#ifndef CONFIG_CANYONLANDS -#define CONFIG_460GT 1 /* Specific PPC460GT */ -#define CONFIG_HOSTNAME glacier +/* + * This config file is used for Canyonlands (460EX) Glacier (460GT) + * and Arches dual (460GT) + */ +#ifdef CONFIG_CANYONLANDS +#define CONFIG_460EX 1 /* Specific PPC460EX */ +#define CONFIG_HOSTNAME canyonlands +#else +#define CONFIG_460GT 1 /* Specific PPC460GT */ +#ifdef CONFIG_GLACIER +#define CONFIG_HOSTNAME glacier #else -#define CONFIG_460EX 1 /* Specific PPC460EX */ -#define CONFIG_HOSTNAME canyonlands +#define CONFIG_HOSTNAME arches +#define CONFIG_BD_NUM_CPUS 2 #endif +#endif + #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ +#if defined(CONFIG_ARCHES) +/* defined before amcc-common.h */ +/* + * On the Arches board, there are 3 configured EMAC interfaces. + * Both PPC460GT's are wired exactly the same, except that SGMII 0 Rx on + * PPC460GT 0 to SGMII 0 Tx on PPC460GT 1. + * + * EMAC0 ppc_4xx_eth0 PPC460-0_SGMII 0 PPC460-1_SGMII 0 + * EMAC1 ppc_4xx_eth1 SGMII 1 Ethernet PHY addr 0000 + * EMAC2 ppc_4xx_eth2 SGMII 2 Ethernet PHY addr 0001 + * + * Need to set the default Ethernet interface to "ppc_4xx_eth1", for EMAC1. + * Default U-Boot environment Ethernet interface will use EMAC1. + */ +#define CONFIG_NETDEV eth1 + +/* + * Update default PREBOOT environment variables + * defined in amcc-common.h + */ +#define CONFIG_PREBOOT \ + "setenv ethact ppc_4xx_eth1;" \ + "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo;" +#endif + /* * Include common defines/options for all AMCC eval boards */ @@ -73,15 +109,24 @@ #define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */ /* EBC stuff */ -#define CFG_NAND_ADDR 0xE0000000 +#if !defined(CONFIG_ARCHES) #define CFG_BCSR_BASE 0xE1000000 -#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */ -#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */ +#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */ +#define CFG_FLASH_SIZE (64 << 20) +#else +#define CFG_FPGA_BASE 0xE1000000 +#define CFG_CPLD_ADDR (CFG_FPGA_BASE + 0x00080000) +#define CFG_CPLD_DATA (CFG_FPGA_BASE + 0x00080002) +#define CFG_FLASH_BASE 0xFE000000 /* later mapped to this addr */ +#define CFG_FLASH_SIZE (32 << 20) +#endif + +#define CFG_NAND_ADDR 0xE0000000 +#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */ #define CFG_FLASH_BASE_PHYS_H 0x4 #define CFG_FLASH_BASE_PHYS_L 0xCC000000 #define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \ (u64)CFG_FLASH_BASE_PHYS_L) -#define CFG_FLASH_SIZE (64 << 20) #define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */ #define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */ @@ -89,7 +134,7 @@ #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ -#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */ +#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in OCM) @@ -223,6 +268,7 @@ * DDR SDRAM *----------------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) +#if !defined(CONFIG_ARCHES) /* * NAND booting U-Boot version uses a fixed initialization, since the whole * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot @@ -232,7 +278,70 @@ #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ -#endif + +#else /* defined(CONFIG_ARCHES) */ + +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ + +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A + +/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CFG_SDRAM_R0BAS 0x0000f000 +#define CFG_SDRAM_R1BAS 0x00000000 +#define CFG_SDRAM_R2BAS 0x00000000 +#define CFG_SDRAM_R3BAS 0x00000000 +#define CFG_SDRAM_PLBADDULL 0x00000000 +#define CFG_SDRAM_PLBADDUHB 0x00000008 +#define CFG_SDRAM_CONF1LL 0x00001080 +#define CFG_SDRAM_CONF1HB 0x00001080 +#define CFG_SDRAM_CONFPATHB 0x10a68000 + +/* SDRAM Controller */ +#define CFG_SDRAM0_MB0CF 0x00000701 +#define CFG_SDRAM0_MB1CF 0x00000000 +#define CFG_SDRAM0_MB2CF 0x00000000 +#define CFG_SDRAM0_MB3CF 0x00000000 +#define CFG_SDRAM0_MCOPT1 0x05322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01000000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_MODT2 0x00000000 +#define CFG_SDRAM0_MODT3 0x00000000 +#define CFG_SDRAM0_CODT 0x00800021 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xb5380000 +#define CFG_SDRAM0_INITPLR1 0x82100400 +#define CFG_SDRAM0_INITPLR2 0x80820000 +#define CFG_SDRAM0_INITPLR3 0x80830000 +#define CFG_SDRAM0_INITPLR4 0x80810040 +#define CFG_SDRAM0_INITPLR5 0x80800532 +#define CFG_SDRAM0_INITPLR6 0x82100400 +#define CFG_SDRAM0_INITPLR7 0x8a080000 +#define CFG_SDRAM0_INITPLR8 0x8a080000 +#define CFG_SDRAM0_INITPLR9 0x8a080000 +#define CFG_SDRAM0_INITPLR10 0x8a080000 +#define CFG_SDRAM0_INITPLR11 0x80000432 +#define CFG_SDRAM0_INITPLR12 0x808103c0 +#define CFG_SDRAM0_INITPLR13 0x80810040 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000257 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x03000091 +#define CFG_SDRAM0_CLKTR 0x40000000 +#define CFG_SDRAM0_WRDTR 0x82000823 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x42204243 +#define CFG_SDRAM0_SDTR3 0x090c0d1a +#define CFG_SDRAM0_MMODE 0x00000432 +#define CFG_SDRAM0_MEMODE 0x00000004 +#endif /* !defined(CONFIG_ARCHES) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) */ + #define CFG_MBYTES_SDRAM 512 /* 512MB */ /*----------------------------------------------------------------------- @@ -255,18 +364,27 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 +#if defined(CONFIG_ARCHES) +#define CFG_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */ +#endif + +#if !defined(CONFIG_ARCHES) /* RTC configuration */ #define CONFIG_RTC_M41T62 1 #define CFG_I2C_RTC_ADDR 0x68 +#endif /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 1 + #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 + +#if !defined(CONFIG_ARCHES) +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 /* Only Glacier (460GT) has 4 EMAC interfaces */ #ifdef CONFIG_460GT #define CONFIG_PHY2_ADDR 2 @@ -275,6 +393,30 @@ #define CONFIG_HAS_ETH3 #endif +#else /* defined(CONFIG_ARCHES) */ + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY +#define CONFIG_PHY1_ADDR 0 +#define CONFIG_PHY2_ADDR 1 +#define CONFIG_HAS_ETH2 + +#define CFG_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CFG_FIXED_PHY_PORTS \ + CFG_FIXED_PHY_PORT(0, 1000, FULL) + +#define CONFIG_M88E1112_PHY + +/* + * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not + * used by CONFIG_PHYx_ADDR + */ +#define CONFIG_GPCS_PHY_ADDR 0xA +#define CONFIG_GPCS_PHY1_ADDR 0xB +#define CONFIG_GPCS_PHY2_ADDR 0xC +#endif /* !defined(CONFIG_ARCHES) */ + #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_DYNAMIC_ANEG 1 @@ -282,6 +424,7 @@ /*----------------------------------------------------------------------- * USB-OHCI *----------------------------------------------------------------------*/ +#if !defined(CONFIG_ARCHES) /* Only Canyonlands (460EX) has USB */ #ifdef CONFIG_460EX #define CONFIG_USB_OHCI_NEW @@ -309,15 +452,36 @@ "pcie_mode=RP:RP\0" \ "" +#else /* defined(CONFIG_ARCHES) */ + +/* Arches board does not have USB connectivity */ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fe000000\0" \ + "fdt_addr=fe1e0000\0" \ + "ramdisk_addr=fe200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" +#endif /* !defined(CONFIG_ARCHES) */ + /* * Commands additional to the ones defined in amcc-common.h */ +#if !defined(CONFIG_ARCHES) #define CONFIG_CMD_DATE -#define CONFIG_CMD_DTT #define CONFIG_CMD_NAND +#define CONFIG_CMD_SNTP +#endif +#define CONFIG_CMD_DTT #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP #ifdef CONFIG_460EX #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT @@ -345,6 +509,36 @@ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#ifdef CONFIG_460GT +#if defined(CONFIG_ARCHES) +/*----------------------------------------------------------------------- + * RapidIO I/O and Registers + *----------------------------------------------------------------------*/ +#define CONFIG_RAPIDIO +#define CFG_460GT_SRIO_ERRATA_1 + +#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */ +#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */ +#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */ +#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */ +#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */ + +#define CFG_SRGPL0_REG_BAR 0xAA000000 /* 16MB */ +#define CFG_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */ +#define CFG_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */ +#define CFG_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */ + +#define CFG_I2ODMA_BASE 0xCF000000 +#define CFG_I2ODMA_PHYS_ADDR 0x0000000400100000ull + +#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE +#undef CONFIG_PPC4XX_RAPIDIO_DEBUG +#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM +#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB +#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK +#endif /* CONFIG_ARCHES */ +#endif /* CONFIG_460GT */ + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -358,6 +552,11 @@ * * 0xfc00.0000 -> 4.cc00.0000 */ +/* + * Arches has 32MBytes of NOR FLASH (Spansion 29GL256) so remap FLASH to + * EBC address which accepts bigger regions: + * 0xfe00.0000 -> 4.ce00.0000 + */ #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) /* Memory Bank 3 (NOR-FLASH) initialization */ @@ -372,15 +571,26 @@ #define CFG_EBC_PB0AP 0x10055e00 #define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000) +#if !defined(CONFIG_ARCHES) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ #endif +#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ +#if !defined(CONFIG_ARCHES) /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x00804240 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */ +#else /* defined(CONFIG_ARCHES) */ + +/* Memory Bank 1 (FPGA) initialization */ +#define CFG_EBC_PB1AP 0x7f8ffe80 +#define CFG_EBC_PB1CR (CFG_FPGA_BASE | 0x3a000) +/* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/ +#endif /* !defined(CONFIG_ARCHES) */ + #define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */ /* diff --git a/include/ppc440.h b/include/ppc440.h index be8d3ff..7ffc640 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1349,6 +1349,9 @@ #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10 #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 +/* Ethernet Status Register */ +#define SDR0_ETH_STS 0x4104 + /* Miscealleneaous Function Reg. (SDR0_MFR) */ #define SDR0_MFR 0x4300 #define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */ -- 1.5.5

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[U-Boot] JFFS2-Summary support for u-boot
by Michael Lawnick 07 Oct '08

07 Oct '08

Hi *, please feel free to correct me if I tell sh**: As far as I was told, bad JFFS2 boot performance of u-boot is result of not supporting summary. (Because there is no JFFS2 but only JFFS support?) So my question: Has anybody done or is planning in next time (~weeks) to add summary support for u-boot JFFS2? We need a file system on 32MB NOR flash with wear leveling and acceptable boot time. Ubi is currently not supported for NOR, JFFS2 slow, ... :-( TIA Kind Regards, M.Lawnick

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[U-Boot] ext2ls - size limit
by mRon 07 Oct '08

07 Oct '08

Hello, Could you tell me what is the maximum size limit for partition to be able to be listed via ext2ls command? I have uBoot 1.1.1 Pozdrawiam, mRon

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[U-Boot] [PATCH] Align end of bss by 4 bytes,
by Selvamuthukumar 07 Oct '08

07 Oct '08

bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. --- cpu/mpc83xx/u-boot.lds | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds index 99ad675..0d26937 100644 --- a/cpu/mpc83xx/u-boot.lds +++ b/cpu/mpc83xx/u-boot.lds @@ -117,6 +117,7 @@ SECTIONS *(.bss) *(COMMON) } + . = ALIGN(4); _end = . ; PROVIDE (end = .); } -- 1.5.5

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[U-Boot] [PATCH] ARM DaVinci: Add maintainer informations for SFFSDR board.
by Hugo Villeneuve 06 Oct '08

06 Oct '08

ARM DaVinci: Add maintainer informations for SFFSDR board. Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> --- MAINTAINERS | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 750e374..fc55a0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -526,6 +526,10 @@ Sergey Kubushyn <ksi(a)koi8.net> SONATA ARM926EJS SCHMOOGIE ARM926EJS +Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> + + SFFSDR ARM926EJS + Prakash Kumar <prakash(a)embedx.com> cerf250 xscale

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[U-Boot] /chosen node not overwritten by bootm
by Stefan Roese 06 Oct '08

06 Oct '08

Hi Jerry, Again I (and Wolfgang) stumbled about the problem, that the /chosen node is not overwritten by the bootm command when it already exists. This is really annoying, since we either: a) Have to remove the chosen node from the dts files (which is not so easy if we try to stay in sync with the kernel.org version) or b) Have to manually use the U-Boot "fdt" commands to overwrite the chosen node I can't remember why this current behavior is implemented this way. Jerry, can't we just overwrite this node even if it already exists? What would we loose by doing this? Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] Arm Pull request
by Jean-Christophe PLAGNIOL-VILLARD 06 Oct '08

06 Oct '08

Hi Wolfgang, Please pull The following changes since commit 8fd4166c467a46773f80208bda1ec3b4757747bc: Stefan Roese (1): ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixup are available in the git repository at: git://git.denx.de/u-boot-arm.git Master Guennadi Liakhovetski (1): i.MX31: switch to CFG_HZ=1000 Jean-Christophe PLAGNIOL-VILLARD (4): Revert "ARM: set GD_FLG_RELOC for boards skipping relocation to RAM" ARM: set GD_FLG_RELOC at board init move README.imx31 to doc/ and merge with README.mx31 update uImage FIT multi documentation README.imx31 | 13 ------ cpu/arm1136/mx31/interrupts.c | 79 ++++++++++++++++++++++++-------------- doc/README.imx31 | 29 ++++++++++++++ doc/README.mx31 | 17 -------- doc/uImage.FIT/multi.its | 2 + include/configs/imx31_litekit.h | 4 +- include/configs/imx31_phycore.h | 2 +- include/configs/mx31ads.h | 4 +- lib_arm/board.c | 19 +-------- 9 files changed, 86 insertions(+), 83 deletions(-) delete mode 100644 README.imx31 create mode 100644 doc/README.imx31 delete mode 100644 doc/README.mx31 Best Regards, J.

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