October 2008 - U-Boot

[U-Boot] [PATCH] Introduce CONFIG_4xx_HAS_OPB
by Josh Boyer 10 Oct '08

10 Oct '08

The lib_ppc/board.c file will fill in the bi_opbfreq variable in the bd_t structure for PowerPC 4xx platforms. However, it currently seems to be coupled together with the bi_pci_busfreq variable under a series of ifdefs for particular CPU types. As a result, it is rather easy to miss getting bi_opbfreq populated on boards when doing a board port. This is the case for CONFIG_405EZ for example. This patch introduces a CONFIG_4xx_HAS_OPB option that is set to indicate that the platform uses that variable in the bd_t structure. It decouples this from the PCI bus setting and sets is properly for CPUs that have this defined. Signed-off-by: Josh Boyer <jwboyer(a)linux.vnet.ibm.com> diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 54ac01d..6673cd4 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -112,12 +112,14 @@ typedef struct bd_info { unsigned char bi_enet3addr[6]; #endif +#if defined(CONFIG_4xx_HAS_OPB) + unsigned int bi_opbfreq; /* OPB clock in Hz */ +#endif #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) - unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif #if defined(CONFIG_NX823) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index e216663..be6696d 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -46,6 +46,15 @@ #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif +/* Configure the OPB variable */ +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CONFIG_4xx_HAS_OPB +#endif + /* PLB4 CrossBar Arbiter Core supported across PPC4xx families */ #if defined(CONFIG_405EX) || \ defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c02ac62..977fc19 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -611,10 +611,12 @@ void board_init_f (ulong bootflag) defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) bd->bi_pci_busfreq = get_PCI_freq (); - bd->bi_opbfreq = get_OPB_freq (); #elif defined(CONFIG_XILINX_405) bd->bi_pci_busfreq = get_PCI_freq (); #endif +#if defined(CONFIG_4xx_HAS_OPB) + bd->bi_opbfreq = get_OPB_freq (); +#endif #endif debug ("New Stack Pointer is: %08lx\n", addr_sp);

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[U-Boot] Standalone application after powerup
by Nagesh.ML 10 Oct '08

10 Oct '08

Hi, I am trying to run the hello_world standalone application on my powerpc board(ppc 82xx). I get it worked right, when the u-boot prompt comes up by copying the hello_world.bin from flash to the RAM space(0x40000) and then using the "go 0x40004" command. Everyting works fine in this case. The next case I tried was using the run_command() function and passing the "cp" and "go" command with appropriate flash and RAM addresses with that as the arguments, After powerup and executing some of the cpu and memory controller initializations..I call the run_command() functions. My board resets giving program check exception. What could be the possible solution to include the standalone application in my board powerup sequence? --Nagesh -- View this message in context: http://www.nabble.com/Standalone-application-after-powerup-tp19914708p19914… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] [patch 0/2] Some more USB-OHCI bugfixes
by Remy Bohmer 10 Oct '08

10 Oct '08

The USB OHCI init procedure sets the maximum message length the wrong way. A max of 64 bits should not be done by writing '64' in maxpacketsize, but '3'. While fixing this problem it turned out that there is more wrong here in this code it turned out that the wrong bits were checked to determine if the pipe was of type PIPE_INTERRUPT. This series fixes those errors also. I made it 2 seperate patches. The 1st of this series is fully tested and correct on at least the AT91SAM9261 cores. I hope it fixes the known problems on AT91SAM9263 (and other) cores also, maybe Stelian can verify this. If it does not help on sam9263, it should not make it worse either... The 2nd patch, however, is created by search-for-the-same-errors-and-replace. I am not able to test that patch, I do not have the boards, so that needs to be done by others or by review. It is clear that code there is buggy in the first place. These patches require my previous series called 'Improve stability USB memory sticks for the common OHCI USB layer.' to be applied before this series. So they should apply on the u-boot-usb git tree. --> git://git.denx.de/u-boot-usb.git I want to mention also, that everytime I look deeper into this code, I find new bugs. It appears that several parts of this code is written with interrupt handling in mind, while we have no interrupt handling at all. Assumptions are done that a interrupt handler does things asynchronous, causing long loops that have no real use at all... So, no guarantees that _all_ problems are solved by now... Kind Regards, Remy --

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[U-Boot] [PATCH 1/4] ppc4xx: Update DU440 config
by matthias.fuchs＠esd-electronics.com 10 Oct '08

10 Oct '08

From: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- include/configs/DU440.h | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 9f8c423..fd0c046 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -85,8 +85,7 @@ /* * Serial Port */ -/* TODO: external clock oscillator will be removed */ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#undef CFG_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE @@ -432,4 +431,7 @@ int du440_phy_addr(int devnum); #define CONFIG_AUTOSCRIPT 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + #endif /* __CONFIG_H */ -- 1.5.3

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Re: [U-Boot] Special memory test Question
by Wolfgang Denk 10 Oct '08

10 Oct '08

Dear Martin, please keep the ML on Cc:. In message <001201c92a17$ee1381c0$4201a8c0@amil> you wrote: > > > Is there by chance any watchdog on your system that mith have such a > > timeout / reset period? ... > Thank you for your quick reply. U-Boot appears to work properly apart from > the "loop" command. I have not run Linux, but different versions of my > application will normally fail in a similar way to what happens when using > the loop command (but after different periods of time i.e 0 to 30 seconds). > > If I type > loop .b <SDRAM address> > or > loop .b <internal SRAM address> > U-boot, after about 20 seconds, produces the dump copied below. > > However if I type > loop .b <Flash memory address> > e.g. loop . 40000 > the code appears to go into an infinate loop. > > Would a dump be produced if the loop command was terminated by a watchdog? No, not as you describe. I think there are two likely reasons for your problem remaining: (1) incorrect initialization of your RAM (see FAQ # 1), and (2) a hardware problem. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Don't hit a man when he's down - kick him; it's easier.

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[U-Boot] [PATCH 1/2] Make mpc8572ds, mpc8544ds, mpc8536ds relocatable
by Ed Swarthout 10 Oct '08

10 Oct '08

Fixes boot crash from bad string pointers in get_table_entry_name when flash is erased or differs from current u-boot image. Remove .fixup from .text section since __fixup_entries is only calculated from .reloc section. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> --- tested with freescale-powerpc-linux-gnu-4.2-171.i686.rpm Patch #2 is needed only if x86 emulation is used for video bios. Compiling the x86 bios emulator with -mrelocatable removes the need to force the function pointer tables into got2. see patch #2 board/freescale/mpc8536ds/config.mk | 1 + board/freescale/mpc8536ds/u-boot.lds | 1 - board/freescale/mpc8544ds/config.mk | 1 + board/freescale/mpc8544ds/u-boot.lds | 1 - board/freescale/mpc8572ds/config.mk | 1 + board/freescale/mpc8572ds/u-boot.lds | 1 - 6 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index 9775ff4..b293583 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -30,3 +30,4 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8536=1 +PLATFORM_CPPFLAGS += -mrelocatable -DCONFIG_RELOC_FIXUP_WORKS diff --git a/board/freescale/mpc8536ds/u-boot.lds b/board/freescale/mpc8536ds/u-boot.lds index 901f633..54f9fbc 100644 --- a/board/freescale/mpc8536ds/u-boot.lds +++ b/board/freescale/mpc8536ds/u-boot.lds @@ -58,7 +58,6 @@ SECTIONS .text : { *(.text) - *(.fixup) *(.got1) } :text _etext = .; diff --git a/board/freescale/mpc8544ds/config.mk b/board/freescale/mpc8544ds/config.mk index 85663ef..b5071f2 100644 --- a/board/freescale/mpc8544ds/config.mk +++ b/board/freescale/mpc8544ds/config.mk @@ -30,3 +30,4 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8544=1 +PLATFORM_CPPFLAGS += -mrelocatable -DCONFIG_RELOC_FIXUP_WORKS diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index a05ece5..6477c69 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -58,7 +58,6 @@ SECTIONS .text : { *(.text) - *(.fixup) *(.got1) } :text _etext = .; diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk index 5b32186..8b3651b 100644 --- a/board/freescale/mpc8572ds/config.mk +++ b/board/freescale/mpc8572ds/config.mk @@ -30,3 +30,4 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 +PLATFORM_CPPFLAGS += -mrelocatable -DCONFIG_RELOC_FIXUP_WORKS diff --git a/board/freescale/mpc8572ds/u-boot.lds b/board/freescale/mpc8572ds/u-boot.lds index a05ece5..6477c69 100644 --- a/board/freescale/mpc8572ds/u-boot.lds +++ b/board/freescale/mpc8572ds/u-boot.lds @@ -58,7 +58,6 @@ SECTIONS .text : { *(.text) - *(.fixup) *(.got1) } :text _etext = .; -- 1.5.6.5

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[U-Boot] [OFF TOPIC] Linux Physmap drivers
by Alemao 09 Oct '08

09 Oct '08

Hi all, Im trying to use a physmap driver for NOR and NAND flash devices. With NOR, everything ok. It uses CFI driver. The problem is with NAND, cause it is connected at Freescale LocalBus UPM, and at a first look, the UPM driver is loading after the physmap (lines 14-15 in kernel output) Here some outputs from the board: Bootloader (U-Boot 1.2.0): CPU: e300c1, MPC8360E, Rev: 21 at 499.999 MHz, CSB: 333 MHz Board: MPC8360KTX I2C: ready DDR RAM: 128 MB FLASH: 16 MB NAND: 64 MiB In: serial Out: serial Err: serial Kernel (linux-2.6.17): 1 physmap nor flash device: 1000000 at ff000000 2 NOR flash: Found 1 x16 devices at 0x0 in 16-bit bank 3 Amd/Fujitsu Extended Query Table at 0x0040 4 number of CFI chips: 1 5 Using physmap partition definition 6 Creating 6 MTD partitions on "NOR flash": 7 0x00000000-0x00040000 : "u-boot" 8 0x00040000-0x00060000 : "env." 9 0x00060000-0x00080000 : "sys" 10 0x00080000-0x000c0000 : "logs" 11 0x000c0000-0x00860000 : "admin" 12 0x00860000-0x01000000 : "users" 13 14 physmap nand flash device: 4000000 at 60000000 15 UPM: User-Programmable Machine NAND driver Device Tree Source: localbus@e0005000 { compatible = "fsl,board-localbus"; #address-cells = <2>; #size-cells = <1>; reg = <e0005000 d8>; // BRx, ORx, etc ranges = <0 0 ff000000 1000000 // nor flash, 16 MB 1 0 60000000 4000000>; // nand flash, 64 MB flash@0,0 { compatible = "atmel,29LV256", "cfi-flash"; reg = <0 0 1000000>; bank-width = <2>; device-width = <1>; }; nand@1,0 { compatible = "stmicro,NAND512W3A", "fsl,upm-nand"; reg = <1 0 4000000>; //reg = <1 0 1>; width = <1>; upm = "A"; upm-addr-offset = <16>; upm-cmd-offset = <8>; gpios = <4 18>; gpio-parent = <&qe_pio>; wait-pattern; wait-write; }; }; The CFI driver is at linux/drivers/mtd/chips The UPM driver is at linux/drivers/mtd/nand So, how can I load the UPM driver before physmap? Thanks in advance, -- Alemao

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[U-Boot] [PATCH 13/13 v3] ARM: OMAP3: Add Overo board
by dirk.behme＠googlemail.com 09 Oct '08

09 Oct '08

Subject: [PATCH 13/13 v3] ARM: OMAP3: Add Overo board From: Dirk Behme <dirk.behme(a)gmail.com> Add Overo board Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v2: - Rebase against u-boot-arm.git next (CFG vs. CONFIG changes) Makefile | 3 board/omap3/overo/Makefile | 46 ++++++ board/omap3/overo/config.mk | 12 + board/omap3/overo/overo.c | 119 +++++++++++++++++ board/omap3/overo/u-boot.lds | 63 +++++++++ include/configs/omap3_overo.h | 283 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 526 insertions(+) Index: u-boot-arm/board/omap3/overo/Makefile =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/overo/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := overo.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### Index: u-boot-arm/board/omap3/overo/config.mk =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/overo/config.mk @@ -0,0 +1,12 @@ +# Overo uses OMAP3 (ARM-CortexA8) cpu +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + Index: u-boot-arm/board/omap3/overo/overo.c =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/overo/overo.c @@ -0,0 +1,119 @@ +/* + * Maintainer : Steve Sakoman <steve(a)sakoman.com> + * + * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> + +const omap3_sysinfo sysinfo = { + SDP_3430_V1, + SDP_3430_V2, + "3503", + "Gumstix Overo board", +}; + +/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OVERO; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/****************************************************************************** + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + *****************************************************************************/ +int misc_init_r(void) +{ + + unsigned char byte; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + /* set vaux2 to 2.8V */ + byte = 0x20; + i2c_write(0x4B, 0x76, 1, &byte, 1); + byte = 0x09; + i2c_write(0x4B, 0x79, 1, &byte, 1); + + /* set vaux3 to 2.8V */ + byte = 0x20; + i2c_write(0x4B, 0x7A, 1, &byte, 1); + byte = 0x03; + i2c_write(0x4B, 0x7D, 1, &byte, 1); + + /* set vpll2 to 1.8V */ + byte = 0xE0; + i2c_write(0x4B, 0x8E, 1, &byte, 1); + byte = 0x05; + i2c_write(0x4B, 0x91, 1, &byte, 1); + + /* set VDAC to 1.8V */ + byte = 0x20; + i2c_write(0x4B, 0x96, 1, &byte, 1); + byte = 0x03; + i2c_write(0x4B, 0x99, 1, &byte, 1); + + byte = 0x33; + i2c_write(0x4A, 0xEE, 1, &byte, 1); + + *((uint *) 0x49058034) = 0xFFFFFAF9; + *((uint *) 0x49056034) = 0x0F9F0FFF; + *((uint *) 0x49058094) = 0x00000506; + *((uint *) 0x49056094) = 0xF060F000; + + return 0; +} + +/****************************************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + *****************************************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_OVERO(); +} + Index: u-boot-arm/board/omap3/overo/u-boot.lds =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/overo/u-boot.lds @@ -0,0 +1,63 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: u-boot-arm/include/configs/omap3_overo.h =================================================================== --- /dev/null +++ u-boot-arm/include/configs/omap3_overo.h @@ -0,0 +1,283 @@ +/* + * Configuration settings for the Gumstix Overo board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OVERO 1 /* working with overo */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_MMC 1 +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#define CONFIG_CMD_AUTOSCRIPT /* autoscript support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* misc functions like sleep etc*/ +#define CONFIG_CMD_RUN /* run command in env variable */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP3 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTCOMMAND "mmcinit; fatload mmc 0 82000000 uImage; bootm 82000000" + +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootdelay=1" + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "Overo # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK)/(2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CONFIG_SYS_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CONFIG_SYS_FLASH_BANKS_LIST {0, 0} + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */ +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS+CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define ENV_IS_VARIABLE 1 + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr)\ + writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF()\ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON()\ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ Index: u-boot-arm/Makefile =================================================================== --- u-boot-arm.orig/Makefile +++ u-boot-arm/Makefile @@ -2722,6 +2722,9 @@ omap3_beagle_config : unconfig omap3_evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm omap3 omap3 +omap3_overo_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo omap3 omap3 + ######################################################################### ## XScale Systems #########################################################################

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[U-Boot] [PATCH 12/13 v3] ARM: OMAP3: Add EVM board
by dirk.behme＠googlemail.com 09 Oct '08

09 Oct '08

Subject: [PATCH 12/13 v3] ARM: OMAP3: Add EVM board From: Dirk Behme <dirk.behme(a)gmail.com> Add EVM board Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v2: - Rebase against u-boot-arm.git next (CFG vs. CONFIG changes) Makefile | 3 board/omap3/evm/Makefile | 46 ++++++ board/omap3/evm/config.mk | 17 ++ board/omap3/evm/evm.c | 199 ++++++++++++++++++++++++++ board/omap3/evm/u-boot.lds | 63 ++++++++ include/configs/omap3_evm.h | 327 ++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 655 insertions(+) Index: u-boot-arm/board/omap3/evm/Makefile =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/evm/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := evm.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### Index: u-boot-arm/board/omap3/evm/config.mk =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/evm/config.mk @@ -0,0 +1,17 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Begale Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + Index: u-boot-arm/board/omap3/evm/evm.c =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/evm/evm.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Manikandan Pillai <mani.pillai(a)ti.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> + +const omap3_sysinfo sysinfo = { + OMAP3EVM_V1, + OMAP3EVM_V2, + "35X-Family", + "OMAP3 EVM board", +}; + +static int setup_net_chip(void); + +/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/****************************************************************************** + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + *****************************************************************************/ +int misc_init_r(void) +{ + + unsigned char byte; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + + return 0; +} + +/****************************************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + *****************************************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); +} + +/****************************************************************************** + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. Pin Muxing for the SMC9118 is initialized + * here. + *****************************************************************************/ +static int setup_net_chip(void) +{ + int i = 0; + + /* Configure GPMC registers */ + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0150)) = 0x00001000; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0154)) = 0x001e1e01; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0158)) = 0x00080300; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x015C)) = 0x1c091c09; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0160)) = 0x04181f1f; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c; + + /* Configure PIN MUX registers */ + /* Enable GPMC Pin Mux Registers */ + /* Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000; + /* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) &= 0xFFFFFFF8; + /* Enable offmode for nwe in CONTROL_PADCONF_GPMC_NWE register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00000F00; + /* En off mode for noe and ale in CONTROL_PADCONF_GPMC_NADV_ALE reg */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC0)) |= 0x0E000E00; + /* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000; + + /* Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and + configuring the mux mode to 0 */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8; + /* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xAC)) |= 0x00000018; + /* Enable d14 - d13 in CONTROL_PADCONF_GPMC_D13 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA8)) |= 0x00180018; + /* Enable d12 - d11 in CONTROL_PADCONF_GPMC_D11 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA4)) |= 0x00180018; + /* Enable d10 - d9 in CONTROL_PADCONF_GPMC_D9 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA0)) |= 0x00180018; + /* Enable d8 - d7 in CONTROL_PADCONF_GPMC_D7 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x9C)) |= 0x00180018; + /* Enable d6 - d5 in CONTROL_PADCONF_GPMC_D5 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x98)) |= 0x00180018; + /* Enable d4 - d3 in CONTROL_PADCONF_GPMC_D3 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x94)) |= 0x00180018; + /* Enable d2 - d1 in CONTROL_PADCONF_GPMC_D1 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x90)) |= 0x00180018; + /* Enable d0 and a10 in CONTROL_PADCONF_GPMC_a10 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) &= 0xFFFFFFF8; + /* Enable a9 - a8 in CONTROL_PADCONF_GPMC_a8 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) &= 0xFFF8FFF8; + /* Enable a7 - a6 in CONTROL_PADCONF_GPMC_a6 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) &= 0xFFF8FFF8; + /* Enable a5 - a4 in CONTROL_PADCONF_GPMC_a4 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) &= 0xFFF8FFF8; + /* Enable a3 - a2 in CONTROL_PADCONF_GPMC_a2 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) &= 0xFFF8FFF8; + /* Enable a1 - a0 in CONTROL_PADCONF_GPMC_a0 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8; + +#if defined(CPU_3430_ES1) || defined(CPU_3430_ES2) + /* GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2 + register mux mode is 4. */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004; + + /* Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1 + register for ethernet ISR mux mode is 4 */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000; + + /* Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER + and CM_ICLKEN_PER registers */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800; + + /* Make GPIO 64 as output pin */ + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x34)) &= ~(0x00000001); + + /* Now send a pulse on the GPIO pin */ + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001; + for (i = 0; i < 99 ; i++); + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) &= ~(0x00000001); + for (i = 0; i < 99 ; i++); + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001; +#else + printf("Unknown revision... \n\n"); +#endif + return 0; +} + Index: u-boot-arm/board/omap3/evm/u-boot.lds =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/evm/u-boot.lds @@ -0,0 +1,63 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: u-boot-arm/include/configs/omap3_evm.h =================================================================== --- /dev/null +++ u-boot-arm/include/configs/omap3_evm.h @@ -0,0 +1,327 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + + * Author : + * Manikandan Pillai <mani.pillai(a)ti.com> + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * Manikandan Pillai <mani.pillai(a)ti.com> + * + * Configuration settings for the TI OMAP3 EVM board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_EVM 1 /* working with EVM */ +#define CONFIG_DOS_PARTITION 1 + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_MMC 1 +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_ONENAND /* ONENAND support */ + +#define CONFIG_CMD_AUTOSCRIPT /* autoscript support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* misc functions like sleep etc*/ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP3 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTCOMMAND "onenand read 80200000 280000 400000 ; \ + bootm 80200000" + +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd \ + root=/dev/mtdblock4 rw rootfstype=jffs2" + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3_EVM # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK)/(2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CONFIG_SYS_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CONFIG_SYS_FLASH_BANKS_LIST {0, 0} + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */ +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_ONENAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS+CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define ENV_IS_VARIABLE 1 + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr)\ + writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF()\ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON()\ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + * ---------------------------------------------------------------------------- + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_DRIVER_SMC911X +#define CONFIG_DRIVER_SMC911X_32_BIT +#define CONFIG_DRIVER_SMC911X_BASE (0x2C000000) + +#endif /* (CONFIG_CMD_NET) */ + +/* + * BOOTP fields + */ + + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 + +#endif /* __CONFIG_H */ Index: u-boot-arm/Makefile =================================================================== --- u-boot-arm.orig/Makefile +++ u-boot-arm/Makefile @@ -2719,6 +2719,9 @@ SMN42_config : unconfig omap3_beagle_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3 +omap3_evm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm omap3 omap3 + ######################################################################### ## XScale Systems #########################################################################

1 0

[U-Boot] [PATCH 11/13 v3] ARM: OMAP3: Add BeagleBoard
by dirk.behme＠googlemail.com 09 Oct '08

09 Oct '08

Subject: [PATCH 11/13 v3] ARM: OMAP3: Add BeagleBoard From: Dirk Behme <dirk.behme(a)gmail.com> Add BeagleBoard Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v2: - Rebase against u-boot-arm.git next (CFG vs. CONFIG changes) Makefile | 7 board/omap3/beagle/Makefile | 46 ++++++ board/omap3/beagle/beagle.c | 113 +++++++++++++++ board/omap3/beagle/config.mk | 17 ++ board/omap3/beagle/u-boot.lds | 63 ++++++++ include/configs/omap3_beagle.h | 292 +++++++++++++++++++++++++++++++++++++++++ 6 files changed, 538 insertions(+) Index: u-boot-arm/board/omap3/beagle/Makefile =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := beagle.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### Index: u-boot-arm/board/omap3/beagle/beagle.c =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/beagle.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> + +const omap3_sysinfo sysinfo = { + SDP_3430_V1, + SDP_3430_V2, + "3530", + "OMAP3 Beagle board", +}; + +/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/****************************************************************************** + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + *****************************************************************************/ +int misc_init_r(void) +{ + + unsigned char byte; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + /* set vaux3 to 2.8V */ + byte = 0x20; + i2c_write(0x4B, 0x7A, 1, &byte, 1); + byte = 0x03; + i2c_write(0x4B, 0x7D, 1, &byte, 1); + + /* set vpll2 to 1.8V */ + byte = 0xE0; + i2c_write(0x4B, 0x8E, 1, &byte, 1); + byte = 0x05; + i2c_write(0x4B, 0x91, 1, &byte, 1); + + /* set VDAC to 1.8V */ + byte = 0x20; + i2c_write(0x4B, 0x96, 1, &byte, 1); + byte = 0x03; + i2c_write(0x4B, 0x99, 1, &byte, 1); + + byte = 0x33; + i2c_write(0x4A, 0xEE, 1, &byte, 1); + + *((uint *) 0x49058034) = 0xFFFFFAF9; + *((uint *) 0x49056034) = 0x0F9F0FFF; + *((uint *) 0x49058094) = 0x00000506; + *((uint *) 0x49056094) = 0xF060F000; + + return 0; +} + +/****************************************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + *****************************************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); +} Index: u-boot-arm/board/omap3/beagle/config.mk =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/config.mk @@ -0,0 +1,17 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Begale Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + Index: u-boot-arm/board/omap3/beagle/u-boot.lds =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/u-boot.lds @@ -0,0 +1,63 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: u-boot-arm/include/configs/omap3_beagle.h =================================================================== --- /dev/null +++ u-boot-arm/include/configs/omap3_beagle.h @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * Configuration settings for the TI OMAP3530 Beagle board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ +#define CONFIG_DOS_PARTITION 1 + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_MMC 1 +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#define CONFIG_CMD_AUTOSCRIPT /* autoscript support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* misc functions like sleep etc*/ +#define CONFIG_CMD_RUN /* run command in env variable */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP3 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTCOMMAND "nand read 80200000 280000 400000 ; bootm 80200000" + +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd root=/dev/mtdblock4 rw rootfstype=jffs2" + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3 beagleboard.org # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK)/(2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CONFIG_SYS_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CONFIG_SYS_FLASH_BANKS_LIST {0, 0} + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */ +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS+CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define ENV_IS_VARIABLE 1 + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr)\ + writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF()\ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON()\ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ Index: u-boot-arm/Makefile =================================================================== --- u-boot-arm.orig/Makefile +++ u-boot-arm/Makefile @@ -2713,6 +2713,13 @@ SMN42_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292 ######################################################################### +## ARM CORTEX Systems +######################################################################### + +omap3_beagle_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3 + +######################################################################### ## XScale Systems #########################################################################

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