October 2008 - U-Boot

[U-Boot] [PATCH 3/3] iMX31: Add support to iMX31PDK board boots from NAND Flash
by Alan Carvalho de Assis 23 Oct '08

23 Oct '08

>From ae5af322e53d00d021f6d4aa39c6916e1d3e12b7 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis <alan.assis(a)freescale.com> Date: Sun, 5 Oct 2008 20:00:59 -0300 Subject: [PATCH] iMX31: Add support to iMX31PDK board boots from NAND Flash This patch adds support to iMX31PDK board to boot directly from NAND Flash. In order to it works the previous patches (which reduces start.S size and copy NAND code to RAM) need be applied first. Signed-off-by: Alan Carvalho de Assis <alan.assis(a)freescale.com> --- board/freescale/mx31pdk/lowlevel_init.S | 95 +++++++++++++++++++++++++++++- board/freescale/mx31pdk/u-boot.lds | 3 + include/configs/mx31pdk.h | 16 ++++-- 3 files changed, 105 insertions(+), 9 deletions(-) diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S index a94ea7f..71ab612 100644 --- a/board/freescale/mx31pdk/lowlevel_init.S +++ b/board/freescale/mx31pdk/lowlevel_init.S @@ -20,11 +20,98 @@ * MA 02111-1307 USA */ -/* - * This is just to keep the linker happy. - */ +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm .globl lowlevel_init lowlevel_init: - mov pc, lr + /* Store return address on the stack since lr is re-used in this file */ + /* and all other registers are re-used as well */ + str lr, [sp] + + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + REG IPU_CONF, IPU_CONF_DI_EN + REG CCM_CCMR, 0x074B0BF5 + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS + + /* Set up clock to 532MHz */ + REG CCM_PDR0, 0xFF871D58 + REG CCM_MPCTL, 0x0033280C + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* Set up CPLD on CS5 */ + REG CSCR_U(5), 0x0000D843 + REG CSCR_L(5), 0x22252521 + REG CSCR_A(5), 0x22220A00 + + /* Set up MX31 DDR Memory Controller */ + REG 0x43FAC26C, 0 /* SDCLK */ + REG 0x43FAC270, 0 /* CAS */ + REG 0x43FAC274, 0 /* RAS */ + REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */ + REG 0x43FAC284, 0 /* DQM3 */ + REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */ + REG 0x43FAC28C, 0 + REG 0x43FAC290, 0 + REG 0x43FAC294, 0 + REG 0x43FAC298, 0 + REG 0x43FAC29C, 0 + REG 0x43FAC2A0, 0 + REG 0x43FAC2A4, 0 + REG 0x43FAC2A8, 0 + REG 0x43FAC2AC, 0 + REG 0x43FAC2B0, 0 + REG 0x43FAC2B4, 0 + REG 0x43FAC2B8, 0 + REG 0x43FAC2BC, 0 + REG 0x43FAC2C0, 0 + REG 0x43FAC2C4, 0 + REG 0x43FAC2C8, 0 + REG 0x43FAC2CC, 0 + REG 0x43FAC2D0, 0 + REG 0x43FAC2D4, 0 + REG 0x43FAC2D8, 0 + REG 0x43FAC2DC, 0 + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x006ac73a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + /* Copy from NAND to RAM */ + b nand_copy diff --git a/board/freescale/mx31pdk/u-boot.lds b/board/freescale/mx31pdk/u-boot.lds index 1460adc..8602f3e 100644 --- a/board/freescale/mx31pdk/u-boot.lds +++ b/board/freescale/mx31pdk/u-boot.lds @@ -35,6 +35,9 @@ SECTIONS .text : { cpu/arm1136/start.o (.text) + board/freescale/mx31pdk/lowlevel_init.o (.text) + cpu/arm1136/mx31/nand_copy.o (.text) + . = 2K; /* lowlevel NAND needs to fit in 2KB of NFC buffer */ *(.text) } diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 6df1a00..d4362e3 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -38,6 +38,9 @@ #define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32768 +/* We are booting from NAND. Used to shrink start.S */ +#define CONFIG_BOOT_FROM_NAND 1 + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -45,11 +48,6 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other - * program to initialize the SDRAM. - */ -#define CONFIG_SKIP_LOWLEVEL_INIT - /* * Size of malloc() pool */ @@ -132,6 +130,13 @@ #define CONFIG_CMDLINE_EDITING 1 /*----------------------------------------------------------------------- + * Early stack pointer + * + * Use internal SRAM memory as SP when booting from NAND (ie. to iMX NFC) + */ +#define CFG_INTERNAL_SRAM_STACK 0x1FFFFFF0 + +/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below @@ -151,6 +156,7 @@ /* No NOR flash present */ #define CFG_NO_FLASH 1 +/* We can't save to Flash. Then place Environment nowhere */ #define CFG_ENV_IS_NOWHERE 1 #define CFG_ENV_SIZE (128 * 1024) -- 1.5.4.3

6 9

[U-Boot] [PATCH 01/19] ColdFire: Remove linker file
by James Kimble 23 Oct '08

23 Oct '08

I'm confused. Are you saying I need to apply these 19 patches to address the problem I'm having?

1 0

Re: [U-Boot] i2c_reg_read() on 8xx
by Wolfgang Denk 22 Oct '08

22 Oct '08

Dear Timur, In message <48FF7F40.1010205(a)freescale.com> you wrote: > Wolfgang, > > Mike Frysinger helped me resolve the problem with i2c_reg_read() on Blackfin, so > I'll be posting a new patch soon. However, I noticed that 8xx has a problem, too: > > uchar > i2c_reg_read(uchar i2c_addr, uchar reg) > { > uchar buf; > > i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); > > i2c_read(i2c_addr, reg, 1, &buf, 1); > > return (buf); > } > > Is the call to i2c_init() necessary on 8xx boards? Shouldn't I2C have already > been initialized? There are some 8xx boards where I2C is used very early so it might be necessary. I have to admit that I don't remember - that code is more than 6 years old. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de No one may kill a man. Not for any purpose. It cannot be condoned. -- Kirk, "Spock's Brain", stardate 5431.6

1 0

[U-Boot] [PATCH] ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directory (fixed patch)
by Roman Mashak 22 Oct '08

22 Oct '08

OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory. It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap Signed-off-by: Roman Mashak <romez777(a)gmail.com> --- cpu/arm926ejs/Makefile | 2 +- cpu/arm926ejs/cpuinfo.c | 242 ------------------------------------------ cpu/arm926ejs/omap/Makefile | 2 +- cpu/arm926ejs/omap/cpuinfo.c | 242 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 244 insertions(+), 244 deletions(-) diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile index 0facce4..d5ac7d3 100644 --- a/cpu/arm926ejs/Makefile +++ b/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o cpuinfo.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm926ejs/cpuinfo.c b/cpu/arm926ejs/cpuinfo.c deleted file mode 100644 index 35ba7db..0000000 --- a/cpu/arm926ejs/cpuinfo.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * OMAP1 CPU identification code - * - * Copyright (C) 2004 Nokia Corporation - * Written by Tony Lindgren <tony(a)atomide.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <command.h> -#include <arm926ejs.h> - -#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) - -#define omap_readw(x) *(volatile unsigned short *)(x) -#define omap_readl(x) *(volatile unsigned long *)(x) - -#define OMAP_DIE_ID_0 0xfffe1800 -#define OMAP_DIE_ID_1 0xfffe1804 -#define OMAP_PRODUCTION_ID_0 0xfffe2000 -#define OMAP_PRODUCTION_ID_1 0xfffe2004 -#define OMAP32_ID_0 0xfffed400 -#define OMAP32_ID_1 0xfffed404 - -struct omap_id { - u16 jtag_id; /* Used to determine OMAP type */ - u8 die_rev; /* Processor revision */ - u32 omap_id; /* OMAP revision */ - u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */ -}; - -/* Register values to detect the OMAP version */ -static struct omap_id omap_ids[] = { - { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, - { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, - { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, - { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, - { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, - { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, - { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00}, - { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00}, - { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, - { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, - { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000}, - { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00}, - { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00}, - { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300}, - { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300}, - { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300}, - { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000}, - { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000}, - { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000}, -}; - -/* - * Get OMAP type from PROD_ID. - * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM. - * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense. - * Undocumented register in TEST BLOCK is used as fallback; This seems to - * work on 1510, 1610 & 1710. The official way hopefully will work in future - * processors. - */ -static u16 omap_get_jtag_id(void) -{ - u32 prod_id, omap_id; - - prod_id = omap_readl(OMAP_PRODUCTION_ID_1); - omap_id = omap_readl(OMAP32_ID_1); - - /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */ - if (((prod_id >> 20) == 0) || (prod_id == omap_id)) - prod_id = 0; - else - prod_id &= 0xffff; - - if (prod_id) - return prod_id; - - /* Use OMAP32_ID_1 as fallback */ - prod_id = ((omap_id >> 12) & 0xffff); - - return prod_id; -} - -/* - * Get OMAP revision from DIE_REV. - * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID. - * Undocumented register in the TEST BLOCK is used as fallback. - * REVISIT: This does not seem to work on 1510 - */ -static u8 omap_get_die_rev(void) -{ - u32 die_rev; - - die_rev = omap_readl(OMAP_DIE_ID_1); - - /* Check for broken OMAP_DIE_ID on early 1710 */ - if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id()) - die_rev = 0; - - die_rev = (die_rev >> 17) & 0xf; - if (die_rev) - return die_rev; - - die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf; - - return die_rev; -} - -static unsigned long dpll1(void) -{ - unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG); - unsigned long rate; - - rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */ - if (pll_ctl_val & 0x10) { - /* PLL enabled, apply multiplier and divisor */ - if (pll_ctl_val & 0xf80) - rate *= (pll_ctl_val & 0xf80) >> 7; - rate /= ((pll_ctl_val & 0x60) >> 5) + 1; - } else { - /* PLL disabled, apply bypass divisor */ - switch (pll_ctl_val & 0xc) { - case 0: - break; - case 0x4: - rate /= 2; - break; - default: - rate /= 4; - break; - } - } - - return rate; -} - -static unsigned long armcore(void) -{ - unsigned short arm_ckctl = omap_readw(ARM_CKCTL); - - return (dpll1() >> ((arm_ckctl & 0x0030) >> 4)); -} - -int print_cpuinfo (void) -{ - int i; - u16 jtag_id; - u8 die_rev; - u32 omap_id; - u8 cpu_type; - u32 system_serial_high; - u32 system_serial_low; - u32 system_rev = 0; - - jtag_id = omap_get_jtag_id(); - die_rev = omap_get_die_rev(); - omap_id = omap_readl(OMAP32_ID_0); - -#ifdef DEBUG - printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0)); - printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n", - omap_readl(OMAP_DIE_ID_1), - (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf); - printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0)); - printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n", - omap_readl(OMAP_PRODUCTION_ID_1), - omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff); - printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0)); - printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1)); - printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev); -#endif - - system_serial_high = omap_readl(OMAP_DIE_ID_0); - system_serial_low = omap_readl(OMAP_DIE_ID_1); - - /* First check only the major version in a safe way */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == (omap_ids[i].jtag_id)) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Check if we can find the die revision */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Finally check also the omap_id */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == omap_ids[i].jtag_id - && die_rev == omap_ids[i].die_rev - && omap_id == omap_ids[i].omap_id) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */ - cpu_type = system_rev >> 24; - - switch (cpu_type) { - case 0x07: - system_rev |= 0x07; - break; - case 0x03: - case 0x15: - system_rev |= 0x15; - break; - case 0x16: - case 0x17: - system_rev |= 0x16; - break; - case 0x24: - system_rev |= 0x24; - break; - default: - printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type); - } - - printf("CPU: OMAP%04x", system_rev >> 16); - if ((system_rev >> 8) & 0xff) - printf("%x", (system_rev >> 8) & 0xff); -#ifdef DEBUG - printf(" revision %i handled as %02xxx id: %08x%08x", - die_rev, system_rev & 0xff, system_serial_low, system_serial_high); -#endif - printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n", - armcore() / 1000000, (armcore() / 100000) % 10, - dpll1() / 1000000, (dpll1() / 100000) % 10); - - return 0; -} - -#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */ diff --git a/cpu/arm926ejs/omap/Makefile b/cpu/arm926ejs/omap/Makefile index c335d5c..74aea74 100644 --- a/cpu/arm926ejs/omap/Makefile +++ b/cpu/arm926ejs/omap/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = timer.o +COBJS = timer.o cpuinfo.o SOBJS = reset.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm926ejs/omap/cpuinfo.c b/cpu/arm926ejs/omap/cpuinfo.c new file mode 100644 index 0000000..35ba7db --- /dev/null +++ b/cpu/arm926ejs/omap/cpuinfo.c @@ -0,0 +1,242 @@ +/* + * OMAP1 CPU identification code + * + * Copyright (C) 2004 Nokia Corporation + * Written by Tony Lindgren <tony(a)atomide.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <command.h> +#include <arm926ejs.h> + +#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) + +#define omap_readw(x) *(volatile unsigned short *)(x) +#define omap_readl(x) *(volatile unsigned long *)(x) + +#define OMAP_DIE_ID_0 0xfffe1800 +#define OMAP_DIE_ID_1 0xfffe1804 +#define OMAP_PRODUCTION_ID_0 0xfffe2000 +#define OMAP_PRODUCTION_ID_1 0xfffe2004 +#define OMAP32_ID_0 0xfffed400 +#define OMAP32_ID_1 0xfffed404 + +struct omap_id { + u16 jtag_id; /* Used to determine OMAP type */ + u8 die_rev; /* Processor revision */ + u32 omap_id; /* OMAP revision */ + u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */ +}; + +/* Register values to detect the OMAP version */ +static struct omap_id omap_ids[] = { + { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, + { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, + { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, + { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, + { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, + { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, + { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00}, + { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00}, + { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, + { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, + { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000}, + { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00}, + { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00}, + { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300}, + { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300}, + { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300}, + { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000}, + { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000}, + { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000}, +}; + +/* + * Get OMAP type from PROD_ID. + * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM. + * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense. + * Undocumented register in TEST BLOCK is used as fallback; This seems to + * work on 1510, 1610 & 1710. The official way hopefully will work in future + * processors. + */ +static u16 omap_get_jtag_id(void) +{ + u32 prod_id, omap_id; + + prod_id = omap_readl(OMAP_PRODUCTION_ID_1); + omap_id = omap_readl(OMAP32_ID_1); + + /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */ + if (((prod_id >> 20) == 0) || (prod_id == omap_id)) + prod_id = 0; + else + prod_id &= 0xffff; + + if (prod_id) + return prod_id; + + /* Use OMAP32_ID_1 as fallback */ + prod_id = ((omap_id >> 12) & 0xffff); + + return prod_id; +} + +/* + * Get OMAP revision from DIE_REV. + * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID. + * Undocumented register in the TEST BLOCK is used as fallback. + * REVISIT: This does not seem to work on 1510 + */ +static u8 omap_get_die_rev(void) +{ + u32 die_rev; + + die_rev = omap_readl(OMAP_DIE_ID_1); + + /* Check for broken OMAP_DIE_ID on early 1710 */ + if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id()) + die_rev = 0; + + die_rev = (die_rev >> 17) & 0xf; + if (die_rev) + return die_rev; + + die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf; + + return die_rev; +} + +static unsigned long dpll1(void) +{ + unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG); + unsigned long rate; + + rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */ + if (pll_ctl_val & 0x10) { + /* PLL enabled, apply multiplier and divisor */ + if (pll_ctl_val & 0xf80) + rate *= (pll_ctl_val & 0xf80) >> 7; + rate /= ((pll_ctl_val & 0x60) >> 5) + 1; + } else { + /* PLL disabled, apply bypass divisor */ + switch (pll_ctl_val & 0xc) { + case 0: + break; + case 0x4: + rate /= 2; + break; + default: + rate /= 4; + break; + } + } + + return rate; +} + +static unsigned long armcore(void) +{ + unsigned short arm_ckctl = omap_readw(ARM_CKCTL); + + return (dpll1() >> ((arm_ckctl & 0x0030) >> 4)); +} + +int print_cpuinfo (void) +{ + int i; + u16 jtag_id; + u8 die_rev; + u32 omap_id; + u8 cpu_type; + u32 system_serial_high; + u32 system_serial_low; + u32 system_rev = 0; + + jtag_id = omap_get_jtag_id(); + die_rev = omap_get_die_rev(); + omap_id = omap_readl(OMAP32_ID_0); + +#ifdef DEBUG + printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0)); + printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n", + omap_readl(OMAP_DIE_ID_1), + (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf); + printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0)); + printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n", + omap_readl(OMAP_PRODUCTION_ID_1), + omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff); + printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0)); + printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1)); + printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev); +#endif + + system_serial_high = omap_readl(OMAP_DIE_ID_0); + system_serial_low = omap_readl(OMAP_DIE_ID_1); + + /* First check only the major version in a safe way */ + for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { + if (jtag_id == (omap_ids[i].jtag_id)) { + system_rev = omap_ids[i].type; + break; + } + } + + /* Check if we can find the die revision */ + for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { + if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) { + system_rev = omap_ids[i].type; + break; + } + } + + /* Finally check also the omap_id */ + for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { + if (jtag_id == omap_ids[i].jtag_id + && die_rev == omap_ids[i].die_rev + && omap_id == omap_ids[i].omap_id) { + system_rev = omap_ids[i].type; + break; + } + } + + /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */ + cpu_type = system_rev >> 24; + + switch (cpu_type) { + case 0x07: + system_rev |= 0x07; + break; + case 0x03: + case 0x15: + system_rev |= 0x15; + break; + case 0x16: + case 0x17: + system_rev |= 0x16; + break; + case 0x24: + system_rev |= 0x24; + break; + default: + printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type); + } + + printf("CPU: OMAP%04x", system_rev >> 16); + if ((system_rev >> 8) & 0xff) + printf("%x", (system_rev >> 8) & 0xff); +#ifdef DEBUG + printf(" revision %i handled as %02xxx id: %08x%08x", + die_rev, system_rev & 0xff, system_serial_low, system_serial_high); +#endif + printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n", + armcore() / 1000000, (armcore() / 100000) % 10, + dpll1() / 1000000, (dpll1() / 100000) % 10); + + return 0; +} + +#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */ -- 1.4.4.4

1 0

[U-Boot] i2c_reg_read() on 8xx
by Timur Tabi 22 Oct '08

22 Oct '08

Wolfgang, Mike Frysinger helped me resolve the problem with i2c_reg_read() on Blackfin, so I'll be posting a new patch soon. However, I noticed that 8xx has a problem, too: uchar i2c_reg_read(uchar i2c_addr, uchar reg) { uchar buf; i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_read(i2c_addr, reg, 1, &buf, 1); return (buf); } Is the call to i2c_init() necessary on 8xx boards? Shouldn't I2C have already been initialized? -- Timur Tabi Linux kernel developer at Freescale

1 0

[U-Boot] [PATCH 19/19] ColdFire: Fix compilation error
by Tsi-Chung Liew 22 Oct '08

22 Oct '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> The error was caused by the change for strmhz() in cpu.c. A few of them were one extra close parenthesis. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf5227x/cpu.c | 10 +++++----- cpu/mcf523x/cpu.c | 4 ++-- cpu/mcf532x/cpu.c | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c index 765aec6..d9f5f43 100644 --- a/cpu/mcf5227x/cpu.c +++ b/cpu/mcf5227x/cpu.c @@ -65,12 +65,12 @@ int checkcpu(void) printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, ver); printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n", - strmhz(buf1, gd->cpu_clk)), - strmhz(buf2, gd->bus_clk)), - strmhz(buf3, gd->flb_clk))); + strmhz(buf1, gd->cpu_clk), + strmhz(buf2, gd->bus_clk), + strmhz(buf3, gd->flb_clk)); printf(" INP CLK %s MHz VCO CLK %s MHz\n", - strmhz(buf1, gd->inp_clk)), - strmhz(buf2, gd->vco_clk))); + strmhz(buf1, gd->inp_clk), + strmhz(buf2, gd->vco_clk)); } return 0; diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c index b9e48aa..a1a5133 100644 --- a/cpu/mcf523x/cpu.c +++ b/cpu/mcf523x/cpu.c @@ -65,8 +65,8 @@ int checkcpu(void) printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, ver); printf(" CPU CLK %s MHz BUS CLK %s MHz\n", - strmhz(buf1, gd->cpu_clk)), - strmhz(buf2, gd->bus_clk))); + strmhz(buf1, gd->cpu_clk), + strmhz(buf2, gd->bus_clk)); } return 0; diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index bcb092d..331cc15 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -104,8 +104,8 @@ int checkcpu(void) printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, ver); printf(" CPU CLK %s MHz BUS CLK %s MHz\n", - strmhz(buf1, gd->cpu_clk)), - strmhz(buf2, gd->bus_clk))); + strmhz(buf1, gd->cpu_clk), + strmhz(buf2, gd->bus_clk)); } return 0; -- 1.5.6.4

1 0

[U-Boot] [PATCH 18/19] ColdFire: Add M53017EVB Platform
by Tsi-Chung Liew 22 Oct '08

22 Oct '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/freescale/m53017evb/Makefile | 44 ++++++ board/freescale/m53017evb/config.mk | 25 ++++ board/freescale/m53017evb/m53017evb.c | 94 +++++++++++++ board/freescale/m53017evb/u-boot.lds | 143 +++++++++++++++++++ doc/README.m53017evb | 181 ++++++++++++++++++++++++ include/configs/M53017EVB.h | 247 +++++++++++++++++++++++++++++++++ 9 files changed, 739 insertions(+), 0 deletions(-) create mode 100644 board/freescale/m53017evb/Makefile create mode 100644 board/freescale/m53017evb/config.mk create mode 100644 board/freescale/m53017evb/m53017evb.c create mode 100644 board/freescale/m53017evb/u-boot.lds create mode 100644 doc/README.m53017evb create mode 100644 include/configs/M53017EVB.h diff --git a/MAINTAINERS b/MAINTAINERS index 60cb6a6..8ef6bab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,7 @@ TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> M52277EVB mcf5227x M5235EVB mcf52x2 M5253DEMO mcf52x2 + M53017EVB mcf532x M5329EVB mcf532x M5373EVB mcf532x M54455EVB mcf5445x diff --git a/MAKEALL b/MAKEALL index aa602b7..26217fd 100755 --- a/MAKEALL +++ b/MAKEALL @@ -708,6 +708,7 @@ LIST_coldfire=" \ M5272C3 \ M5275EVB \ M5282EVB \ + M53017EVB \ M5329AFEE \ M5373EVB \ M54451EVB \ diff --git a/Makefile b/Makefile index 7a35676..3c74fd2 100644 --- a/Makefile +++ b/Makefile @@ -1978,6 +1978,9 @@ M5275EVB_config : unconfig M5282EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale +M53017EVB_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf532x m53017evb freescale + M5329AFEE_config \ M5329BFEE_config : unconfig @case "$@" in \ diff --git a/board/freescale/m53017evb/Makefile b/board/freescale/m53017evb/Makefile new file mode 100644 index 0000000..981763d --- /dev/null +++ b/board/freescale/m53017evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m53017evb/config.mk b/board/freescale/m53017evb/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m53017evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c new file mode 100644 index 0000000..f331786 --- /dev/null +++ b/board/freescale/m53017evb/m53017evb.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M53017EVB\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); +#ifdef CONFIG_SYS_SDRAM_BASE1 + sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); +#endif + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + /* Perform two refresh cycles */ + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + asm("nop"); + + /* Issue LEMR */ + sdram->mode = CONFIG_SYS_SDRAM_MODE; + asm("nop"); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + asm("nop"); + + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + asm("nop"); + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds new file mode 100644 index 0000000..dc53141 --- /dev/null +++ b/board/freescale/m53017evb/u-boot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + cpu/mcf532x/libmcf532x.a (.text) + lib_m68k/libm68k.a (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/doc/README.m53017evb b/doc/README.m53017evb new file mode 100644 index 0000000..60cfa95 --- /dev/null +++ b/doc/README.m53017evb @@ -0,0 +1,181 @@ +Freescale MCF53017EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew(a)freescale.com) +Created 10/22/08 +=========================================== + + +Changed files: +============== + +- board/freescale/m53017evb/m53017evb.c Dram setup +- board/freescale/m53017evb/mii.c Mii access +- board/freescale/m53017evb/Makefile Makefile +- board/freescale/m53017evb/config.mk config make +- board/freescale/m53017evb/u-boot.lds Linker description + +- cpu/mcf532x/cpu.c cpu specific code +- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- cpu/mcf532x/interrupts.c cpu specific interrupt support +- cpu/mcf532x/speed.c system, flexbus, and cpu clock +- cpu/mcf532x/Makefile Makefile +- cpu/mcf532x/config.mk config make +- cpu/mcf532x/start.S start up assembly code + +- doc/README.m53017evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/net/mcfmii.c ColdFire common Mii driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5301x.h mcf5301x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf5301x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M53017EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +1 MCF5301x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M53017EVB Development Board +CONFIG_MCF5301x -- define for all MCF5301x CPUs +CONFIG_M53015 -- define for MCF53015 CPUs +CONFIG_M53017EVB -- define for M53017EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_NET_MULTI -- define to use multi FEC in u-boot +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xFC000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot + make distclean + make M53017EVB_config + make + +4. SCREEN DUMP +============== +4.1 M53017EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 2008.10 (Oct 22 2007 - 11:07:57) + +CPU: Freescale MCF53015 (Mask:76 Version:0) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale M53017EVB +I2C: ready +DRAM: 64 MB +FLASH: 16 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0, FEC1 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M53017EVB +netdev=eth0 +loadaddr=40010000 +u-boot=u-boot.bin +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=65024k + +Environment size: 437/4092 bytes +-> diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h new file mode 100644 index 0000000..df54c60 --- /dev/null +++ b/include/configs/M53017EVB.h @@ -0,0 +1,247 @@ +/* + * Configuation settings for the Freescale MCF53017EVB. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M53017EVB_H +#define _M53017EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5301x /* define processor family */ +#define CONFIG_M53015 /* define processor type */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#undef CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#define CONFIG_SYS_UNIFY_CACHE + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_HAS_ETH1 + +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE +# define CONFIG_SYS_FEC1_PINMUX 0 +# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CONFIG_SYS_RTC_CNT (0x8000) +#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M53017 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x43711630 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_EMOD 0x80010000 +#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_FLASH_CFI +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash + * CS1 - Ext SRAM + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 + +#define CONFIG_SYS_CS1_BASE 0xC0000000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x00001FA0 + +#endif /* _M53017EVB_H */ -- 1.5.6.4

1 0

[U-Boot] [PATCH 17/19] ColdFire: Add MCF5301x CPU header files
by Tsi-Chung Liew 22 Oct '08

22 Oct '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- include/asm-m68k/immap.h | 32 +++ include/asm-m68k/immap_5301x.h | 324 +++++++++++++++++++++ include/asm-m68k/m5301x.h | 604 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 960 insertions(+), 0 deletions(-) create mode 100644 include/asm-m68k/immap_5301x.h create mode 100644 include/asm-m68k/m5301x.h diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index ccd7c2b..93f730f 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -227,6 +227,38 @@ #endif #endif /* CONFIG_M5282 */ +#if defined(CONFIG_MCF5301x) +#include <asm/immap_5301x.h> +#include <asm/m5301x.h> + +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) + +#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (6) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) +#endif + +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) +#endif /* CONFIG_M5301x */ + #if defined(CONFIG_M5329) || defined(CONFIG_M5373) #include <asm/immap_5329.h> #include <asm/m5329.h> diff --git a/include/asm-m68k/immap_5301x.h b/include/asm-m68k/immap_5301x.h new file mode 100644 index 0000000..87ac770 --- /dev/null +++ b/include/asm-m68k/immap_5301x.h @@ -0,0 +1,324 @@ +/* + * MCF5301x Internal Memory Map + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5301X__ +#define __IMMAP_5301X__ + +#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) +#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000) +#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) +#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000) +#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) +#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) +#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) +#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) +#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000) +#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000) +#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000) +#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000) +#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000) +#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) +#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000) +#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000) +#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000) +#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) +#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) +#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000) +#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000) +#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) + +#include <asm/coldfire/crossbar.h> +#include <asm/coldfire/dspi.h> +#include <asm/coldfire/edma.h> +#include <asm/coldfire/eport.h> +#include <asm/coldfire/flexbus.h> +#include <asm/coldfire/intctrl.h> +#include <asm/coldfire/ssi.h> +#include <asm/coldfire/rng.h> +#include <asm/rtc.h> + +/* System Controller Module */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 Peripheral Access Ctrl A */ + u32 pacrb; /* 0x24 Peripheral Access Ctrl B */ + u32 pacrc; /* 0x28 Peripheral Access Ctrl C */ + u32 pacrd; /* 0x2C Peripheral Access Ctrl D */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 Peripheral Access Ctrl E */ + u32 pacrf; /* 0x44 Peripheral Access Ctrl F */ + u32 pacrg; /* 0x48 Peripheral Access Ctrl G */ +} scm1_t; + +typedef struct scm2 { + u8 rsvd1[19]; /* 0x00 - 0x12 */ + u8 wcr; /* 0x13 */ + u16 rsvd2; /* 0x14 - 0x15 */ + u16 cwcr; /* 0x16 */ + u8 rsvd3[3]; /* 0x18 - 0x1A */ + u8 cwsr; /* 0x1B */ + u8 rsvd4[3]; /* 0x1C - 0x1E */ + u8 scmisr; /* 0x1F */ + u32 rsvd5; /* 0x20 - 0x23 */ + u8 bcr; /* 0x24 */ + u8 rsvd6[74]; /* 0x25 - 0x6F */ + u32 cfadr; /* 0x70 */ + u8 rsvd7; /* 0x74 */ + u8 cfier; /* 0x75 */ + u8 cfloc; /* 0x76 */ + u8 cfatr; /* 0x77 */ + u32 rsvd8; /* 0x78 - 0x7B */ + u32 cfdtr; /* 0x7C */ +} scm2_t; + +/* PWM module */ +typedef struct pwm_ctrl { + u8 en; /* 0x00 PWM Enable */ + u8 pol; /* 0x01 Polarity */ + u8 clk; /* 0x02 Clock Select */ + u8 prclk; /* 0x03 Prescale Clock Select */ + u8 cae; /* 0x04 Center Align Enable */ + u8 ctl; /* 0x05 Ctrl */ + u8 res1[2]; /* 0x06 - 0x07 */ + u8 scla; /* 0x08 Scale A */ + u8 sclb; /* 0x09 Scale B */ + u8 res2[2]; /* 0x0A - 0x0B */ + u8 cnt0; /* 0x0C Channel 0 Counter */ + u8 cnt1; /* 0x0D Channel 1 Counter */ + u8 cnt2; /* 0x0E Channel 2 Counter */ + u8 cnt3; /* 0x0F Channel 3 Counter */ + u8 cnt4; /* 0x10 Channel 4 Counter */ + u8 cnt5; /* 0x11 Channel 5 Counter */ + u8 cnt6; /* 0x12 Channel 6 Counter */ + u8 cnt7; /* 0x13 Channel 7 Counter */ + u8 per0; /* 0x14 Channel 0 Period */ + u8 per1; /* 0x15 Channel 1 Period */ + u8 per2; /* 0x16 Channel 2 Period */ + u8 per3; /* 0x17 Channel 3 Period */ + u8 per4; /* 0x18 Channel 4 Period */ + u8 per5; /* 0x19 Channel 5 Period */ + u8 per6; /* 0x1A Channel 6 Period */ + u8 per7; /* 0x1B Channel 7 Period */ + u8 dty0; /* 0x1C Channel 0 Duty */ + u8 dty1; /* 0x1D Channel 1 Duty */ + u8 dty2; /* 0x1E Channel 2 Duty */ + u8 dty3; /* 0x1F Channel 3 Duty */ + u8 dty4; /* 0x20 Channel 4 Duty */ + u8 dty5; /* 0x21 Channel 5 Duty */ + u8 dty6; /* 0x22 Channel 6 Duty */ + u8 dty7; /* 0x23 Channel 7 Duty */ + u8 sdn; /* 0x24 Shutdown */ + u8 res3[3]; /* 0x25 - 0x27 */ +} pwm_t; + +/* Chip configuration module */ +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +typedef struct ccm_ctrl { + u16 ccr; /* 0x00 Chip Cfg */ + u16 res1; /* 0x02 */ + u16 rcon; /* 0x04 Reset Cfg */ + u16 cir; /* 0x06 Chip ID */ + u32 res2; /* 0x08 */ + u16 misccr; /* 0x0A Misc Ctrl */ + u16 cdr; /* 0x0C Clock divider */ + u16 uhcsr; /* 0x10 USB Host status */ + u16 uocsr; /* 0x12 USB On-the-Go Status */ + u16 res3; /* 0x14 */ + u16 codeccr; /* 0x16 Codec Control */ + u16 misccr2; /* 0x18 Misc2 Ctrl */ +} ccm_t; + +/* GPIO port */ +typedef struct gpio_ctrl { + /* Port Output Data */ + u8 podr_fbctl; /* 0x00 */ + u8 podr_be; /* 0x01 */ + u8 podr_cs; /* 0x02 */ + u8 podr_dspi; /* 0x03 */ + u8 res01; /* 0x04 */ + u8 podr_fec0; /* 0x05 */ + u8 podr_feci2c; /* 0x06 */ + u8 res02[2]; /* 0x07 - 0x08 */ + u8 podr_simp1; /* 0x09 */ + u8 podr_simp0; /* 0x0A */ + u8 podr_timer; /* 0x0B */ + u8 podr_uart; /* 0x0C */ + u8 podr_debug; /* 0x0D */ + u8 res03; /* 0x0E */ + u8 podr_sdhc; /* 0x0F */ + u8 podr_ssi; /* 0x10 */ + u8 res04[3]; /* 0x11 - 0x13 */ + + /* Port Data Direction */ + u8 pddr_fbctl; /* 0x14 */ + u8 pddr_be; /* 0x15 */ + u8 pddr_cs; /* 0x16 */ + u8 pddr_dspi; /* 0x17 */ + u8 res05; /* 0x18 */ + u8 pddr_fec0; /* 0x19 */ + u8 pddr_feci2c; /* 0x1A */ + u8 res06[2]; /* 0x1B - 0x1C */ + u8 pddr_simp1; /* 0x1D */ + u8 pddr_simp0; /* 0x1E */ + u8 pddr_timer; /* 0x1F */ + u8 pddr_uart; /* 0x20 */ + u8 pddr_debug; /* 0x21 */ + u8 res07; /* 0x22 */ + u8 pddr_sdhc; /* 0x23 */ + u8 pddr_ssi; /* 0x24 */ + u8 res08[3]; /* 0x25 - 0x27 */ + + /* Port Data Direction */ + u8 ppdr_fbctl; /* 0x28 */ + u8 ppdr_be; /* 0x29 */ + u8 ppdr_cs; /* 0x2A */ + u8 ppdr_dspi; /* 0x2B */ + u8 res09; /* 0x2C */ + u8 ppdr_fec0; /* 0x2D */ + u8 ppdr_feci2c; /* 0x2E */ + u8 res10[2]; /* 0x2F - 0x30 */ + u8 ppdr_simp1; /* 0x31 */ + u8 ppdr_simp0; /* 0x32 */ + u8 ppdr_timer; /* 0x33 */ + u8 ppdr_uart; /* 0x34 */ + u8 ppdr_debug; /* 0x35 */ + u8 res11; /* 0x36 */ + u8 ppdr_sdhc; /* 0x37 */ + u8 ppdr_ssi; /* 0x38 */ + u8 res12[3]; /* 0x39 - 0x3B */ + + /* Port Clear Output Data */ + u8 pclrr_fbctl; /* 0x3C */ + u8 pclrr_be; /* 0x3D */ + u8 pclrr_cs; /* 0x3E */ + u8 pclrr_dspi; /* 0x3F */ + u8 res13; /* 0x40 */ + u8 pclrr_fec0; /* 0x41 */ + u8 pclrr_feci2c; /* 0x42 */ + u8 res14[2]; /* 0x43 - 0x44 */ + u8 pclrr_simp1; /* 0x45 */ + u8 pclrr_simp0; /* 0x46 */ + u8 pclrr_timer; /* 0x47 */ + u8 pclrr_uart; /* 0x48 */ + u8 pclrr_debug; /* 0x49 */ + u8 res15; /* 0x4A */ + u8 pclrr_sdhc; /* 0x4B */ + u8 pclrr_ssi; /* 0x4C */ + u8 res16[3]; /* 0x4D - 0x4F */ + + /* Pin Assignment */ + u8 par_fbctl; /* 0x50 */ + u8 par_be; /* 0x51 */ + u8 par_cs; /* 0x52 */ + u8 res17; /* 0x53 */ + u8 par_dspih; /* 0x54 */ + u8 par_dspil; /* 0x55 */ + u8 par_fec; /* 0x56 */ + u8 par_feci2c; /* 0x57 */ + u8 par_irq0h; /* 0x58 */ + u8 par_irq0l; /* 0x59 */ + u8 par_irq1h; /* 0x5A */ + u8 par_irq1l; /* 0x5B */ + u8 par_simp1h; /* 0x5C */ + u8 par_simp1l; /* 0x5D */ + u8 par_simp0; /* 0x5E */ + u8 par_timer; /* 0x5F */ + u8 par_uart; /* 0x60 */ + u8 res18; /* 0x61 */ + u8 par_debug; /* 0x62 */ + u8 par_sdhc; /* 0x63 */ + u8 par_ssih; /* 0x64 */ + u8 par_ssil; /* 0x65 */ + u8 res19[2]; /* 0x66 - 0x67 */ + + /* Mode Select Control */ + /* Drive Strength Control */ + u8 mscr_mscr1; /* 0x68 */ + u8 mscr_mscr2; /* 0x69 */ + u8 mscr_mscr3; /* 0x6A */ + u8 mscr_mscr45; /* 0x6B */ + u8 srcr_dspi; /* 0x6C */ + u8 dscr_fec; /* 0x6D */ + u8 srcr_i2c; /* 0x6E */ + u8 srcr_irq; /* 0x6F */ + + u8 srcr_sim; /* 0x70 */ + u8 srcr_timer; /* 0x71 */ + u8 srcr_uart; /* 0x72 */ + u8 res20; /* 0x73 */ + u8 srcr_sdhc; /* 0x74 */ + u8 srcr_ssi; /* 0x75 */ + u8 res21[2]; /* 0x76 - 0x77 */ + u8 pcr_pcrh; /* 0x78 */ + u8 pcr_pcrl; /* 0x79 */ +} gpio_t; + +/* SDRAM controller */ +typedef struct sdram_ctrl { + u32 mode; /* 0x00 Mode/Extended Mode */ + u32 ctrl; /* 0x04 Ctrl */ + u32 cfg1; /* 0x08 Cfg 1 */ + u32 cfg2; /* 0x0C Cfg 2 */ + u32 res1[64]; /* 0x10 - 0x10F */ + u32 cs0; /* 0x110 Chip Select 0 Cfg */ + u32 cs1; /* 0x114 Chip Select 1 Cfg */ +} sdram_t; + +/* Clock Module */ +typedef struct pll_ctrl { + u32 pcr; /* 0x00 Ctrl */ + u32 pdr; /* 0x04 Divider */ + u32 psr; /* 0x08 Status */ +} pll_t; + +typedef struct rtcex { + u32 rsvd1[3]; + u32 gocu; + u32 gocl; +} rtcex_t; +#endif /* __IMMAP_5301X__ */ diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h new file mode 100644 index 0000000..52bbb87 --- /dev/null +++ b/include/asm-m68k/m5301x.h @@ -0,0 +1,604 @@ +/* + * m5301x.h -- Definitions for Freescale Coldfire 5301x + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef m5301x_h +#define m5301x_h + +/* *** System Control Module (SCM) *** */ +#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) +#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) +#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) +#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) +#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) +#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) +#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) +#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) +#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) + +#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) +#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8) + +#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) +#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) +#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) +#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16) +#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) +#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) +#define SCM_PACRC_PACR23(x) ((x) & 0x0F) + +#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) +#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) +#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) +#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) +#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) +#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) +#define SCM_PACRD_PACR31(x) ((x) & 0x0F) + +#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) +#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) +#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) +#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) +#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) +#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8) +#define SCM_PACRE_PACR39(x) ((x) & 0x0F) + +#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) +#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) +#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) +#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16) +#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12) +#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8) +#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4) +#define SCM_PACRF_PACR47(x) ((x) & 0x0F) + +#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28) +#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24) +#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20) +#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16) + +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +#define SCM_CWCR_RO (0x8000) +#define SCM_CWCR_CWR_WH (0x0100) +#define SCM_CWCR_CWE (0x0080) +#define SCM_CWCR_CWRI_WINDOW (0x0060) +#define SCM_CWCR_CWRI_RESET (0x0040) +#define SCM_CWCR_CWRI_INT_RESET (0x0020) +#define SCM_CWCR_CWRI_INT (0x0000) +#define SCM_CWCR_CWT(x) (((x) & 0x001F)) + +#define SCM_ISR_CFEI (0x02) +#define SCM_ISR_CWIC (0x01) + +#define BCR_GBR (0x00000200) +#define BCR_GBW (0x00000100) +#define BCR_S7 (0x00000080) +#define BCR_S6 (0x00000040) +#define BCR_S4 (0x00000010) +#define BCR_S1 (0x00000002) + +#define SCM_CFIER_ECFEI (0x01) + +#define SCM_CFLOC_LOC (0x80) + +#define SCM_CFATR_WRITE (0x80) +#define SCM_CFATR_SZ32 (0x20) +#define SCM_CFATR_SZ16 (0x10) +#define SCM_CFATR_SZ08 (0x00) +#define SCM_CFATR_CACHE (0x08) +#define SCM_CFATR_MODE (0x02) +#define SCM_CFATR_TYPE (0x01) + +/* *** Interrupt Controller (INTC) *** */ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM_CWIC (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_DSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +#define INT0_HI_FEC1_TXF (49) +#define INT0_HI_FEC1_TXB (50) +#define INT0_HI_FEC1_UN (51) +#define INT0_HI_FEC1_RL (52) +#define INT0_HI_FEC1_RXF (53) +#define INT0_HI_FEC1_RXB (54) +#define INT0_HI_FEC1_MII (55) +#define INT0_HI_FEC1_LC (56) +#define INT0_HI_FEC1_HBERR (57) +#define INT0_HI_FEC1_GRA (58) +#define INT0_HI_FEC1_EBERR (59) +#define INT0_HI_FEC1_BABT (60) +#define INT0_HI_FEC1_BABR (61) +#define INT0_HI_SCM_CFEI (62) + +/* 0 - 24 reserved */ +#define INT1_LO_EPORT1_FLAG0 (25) +#define INT1_LO_EPORT1_FLAG1 (26) +#define INT1_LO_EPORT1_FLAG2 (27) +#define INT1_LO_EPORT1_FLAG3 (28) +#define INT1_LO_EPORT1_FLAG4 (29) +#define INT1_LO_EPORT1_FLAG5 (30) +#define INT1_LO_EPORT1_FLAG6 (31) +#define INT1_LO_EPORT1_FLAG7 (32) +#define INT1_HI_DSPI_EOQF (33) +#define INT1_HI_DSPI_TFFF (34) +#define INT1_HI_DSPI_TCF (35) +#define INT1_HI_DSPI_TFUF (36) +#define INT1_HI_DSPI_RFDF (37) +#define INT1_HI_DSPI_RFOF (38) +#define INT1_HI_DSPI_RFOF_TFUF (39) +#define INT1_HI_RNG_EI (40) +#define INT1_HI_PLL_LOCF (41) +#define INT1_HI_PLL_LOLF (42) +#define INT1_HI_PIT0 (43) +#define INT1_HI_PIT1 (44) +#define INT1_HI_PIT2 (45) +#define INT1_HI_PIT3 (46) +#define INT1_HI_USBOTG_STS (47) +#define INT1_HI_USBHOST_STS (48) +#define INT1_HI_SSI (49) +/* 50 - 51 reserved */ +#define INT1_HI_RTC (52) +#define INT1_HI_CCM_USBSTAT (53) +#define INT1_HI_CODEC_OR (54) +#define INT1_HI_CODEC_RF_TE (55) +#define INT1_HI_CODEC_ROE (56) +#define INT1_HI_CODEC_TUE (57) +/* 58 reserved */ +#define INT1_HI_SIM1_DATA (59) +#define INT1_HI_SIM1_GENERAL (60) +/* 61 - 62 reserved */ +#define INT1_HI_SDHC (63) + +/* *** Reset Controller Module (RCM) *** */ +#define RCM_RCR_SOFTRST (0x80) +#define RCM_RCR_FRCRSTOUT (0x40) + +#define RCM_RSR_SOFT (0x20) +#define RCM_RSR_LOC (0x10) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_LOL (0x01) + +/* *** Chip Configuration Module (CCM) *** */ +#define CCM_CCR_CSC (0x0020) +#define CCM_CCR_BOOTPS (0x0010) +#define CCM_CCR_LOAD (0x0008) +#define CCM_CCR_OSC_MODE (0x0004) +#define CCM_CCR_SDR_MODE (0x0002) +#define CCM_CCR_RESERVED (0x0001) + +#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012) +#define CCM_RCON_DDR_8BIT_SPLIT (0x0010) +#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002) +#define CCM_RCON_DDR_16BIT_SPLIT (0x0000) + +#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) + +#define CCM_MISCCR_FECM (0x8000) +#define CCM_MISCCR_CDCSRC (0x4000) +#define CCM_MISCCR_PLL_LOCK (0x2000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_BME (0x8000) +#define CCM_MISCCR_BMT_MASK (0xF8FF) +#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) +#define CCM_MISCCR_BMT_512 (0x0700) +#define CCM_MISCCR_BMT_1024 (0x0600) +#define CCM_MISCCR_BMT_2048 (0x0500) +#define CCM_MISCCR_BMT_4096 (0x0400) +#define CCM_MISCCR_BMT_8192 (0x0300) +#define CCM_MISCCR_BMT_16384 (0x0200) +#define CCM_MISCCR_BMT_32768 (0x0100) +#define CCM_MISCCR_BMT_65536 (0x0000) +#define CCM_MISCCR_TIM_DMA (0x0020) +#define CCM_MISCCR_SSI_SRC (0x0010) +#define CCM_MISCCR_USBH_OC (0x0008) +#define CCM_MISCCR_USBO_OC (0x0004) +#define CCM_MISCCR_USB_PUE (0x0002) +#define CCM_MISCCR_USB_SRC (0x0001) + +#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8) +#define CCM_CDR_SSIDIV(x) ((x) & 0xFF) + +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) + +#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14) +#define CCM_UHCSR_DRV_VBUS (0x0010) +#define CCM_UHCSR_PWRFLT (0x0008) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UHMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) + +#define CCM_CODCR_BGREN (0x8000) +#define CCM_CODCR_REGEN (0x0080) + +#define CCM_MISC2_IGNLL (0x0008) +#define CCM_MISC2_DPS (0x0001) + +/* *** General Purpose I/O (GPIO) *** */ +#define GPIO_PDR_FBCTL ((x) & 0x0F) +#define GPIO_PDR_BE ((x) & 0x0F) +#define GPIO_PDR_CS32 (((x) & 0x03) << 4) +#define GPIO_PDR_CS10 (((x) & 0x03) << 4) +#define GPIO_PDR_DSPI ((x) & 0x7F) +#define GPIO_PDR_FEC0 ((x) & 0x7F) +#define GPIO_PDR_FECI2C ((x) & 0x3F) +#define GPIO_PDR_SIMP1 ((x) & 0x1F) +#define GPIO_PDR_SIMP0 ((x) & 0x1F) +#define GPIO_PDR_TIMER ((x) & 0x0F) +#define GPIO_PDR_UART ((x) & 0x3F) +#define GPIO_PDR_DEBUG (0x01) +#define GPIO_PDR_SDHC ((x) & 0x3F) +#define GPIO_PDR_SSI ((x) & 0x1F) + +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_RWB (0x20) +#define GPIO_PAR_FBCTL_TS (0x18) + +#define GPIO_PAR_BE3 (0x40) +#define GPIO_PAR_BE2 (0x10) +#define GPIO_PAR_BE1 (0x04) +#define GPIO_PAR_BE0 (0x01) + +#define GPIO_PAR_CS5 (0x40) +#define GPIO_PAR_CS4 (0x10) +#define GPIO_PAR_CS1_MASK (0xF3) +#define GPIO_PAR_CS1_CS1 (0x0C) +#define GPIO_PAR_CS1_SDCS1 (0x08) +#define GPIO_PAR_CS0_MASK (0xFC) +#define GPIO_PAR_CS0_CS0 (0x03) +#define GPIO_PAR_CS0_CS4 (0x02) + +#define GPIO_PAR_DSPIH_SIN_MASK (0x3F) +#define GPIO_PAR_DSPIH_SIN (0xC0) +#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) +#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF) +#define GPIO_PAR_DSPIH_SOUT (0x30) +#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) +#define GPIO_PAR_DSPIH_SCK_MASK (0xF3) +#define GPIO_PAR_DSPIH_SCK (0x0C) +#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) +#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC) +#define GPIO_PAR_DSPIH_PCS0 (0x03) +#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) + +#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F) +#define GPIO_PAR_DSPIL_PCS1 (0xC0) +#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF) +#define GPIO_PAR_DSPIL_PCS2 (0x30) +#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) +#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3) +#define GPIO_PAR_DSPIL_PCS3 (0x0C) +#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) + +#define GPIO_PAR_FEC1_7W_FEC (0x40) +#define GPIO_PAR_FEC1_RMII_FEC (0x10) +#define GPIO_PAR_FEC0_7W_FEC (0x04) +#define GPIO_PAR_FEC0_RMII_FEC (0x01) + +/* GPIO_PAR_FECI2C */ +#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F) +#define GPIO_PAR_FECI2C_MDC0 (0x80) +#define GPIO_PAR_FECI2C_MDIO0 (0x40) +#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF) +#define GPIO_PAR_FECI2C_MDC1 (0x20) +#define GPIO_PAR_FECI2C_MDIO1 (0x10) +#define GPIO_PAR_FECI2C_SDA_MASK (0xF3) +#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) +#define GPIO_PAR_FECI2C_SDA_SDA (0x0C) +#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) +#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) +#define GPIO_PAR_FECI2C_SCL_MASK (0xFC) +#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) +#define GPIO_PAR_FECI2C_SCL_SCL (0x03) +#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) +#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) + +#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F) +#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF) +#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) +#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC) +#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) + +#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3) +#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) + +#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) +#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10) +#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04) +#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01) + +#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40) +#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10) +#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) +#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) + +#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F) +#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) +#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) +#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) +#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF) +#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) +#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) +#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) +#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3) +#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) +#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) +#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) +#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC) +#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) +#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) +#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) + +#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F) +#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) +#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) + +#define GPIO_PAR_SIMP0_DATA0 (0x10) +#define GPIO_PAR_SIMP0_VEN0 (0x08) +#define GPIO_PAR_SIMP0_RST0 (0x04) +#define GPIO_PAR_SIMP0_PD0 (0x02) +#define GPIO_PAR_SIMP0_CLK0 (0x01) + +#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6) +#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) +#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) +#define GPIO_PAR_TIN0(x) ((x) & 0x03) +#define GPIO_PAR_TIN3_MASK (0x3F) +#define GPIO_PAR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TIN3_IRQ03 (0x40) +#define GPIO_PAR_TIN2_MASK (0xCF) +#define GPIO_PAR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TIN2_IRQ02 (0x10) +#define GPIO_PAR_TIN1_MASK (0xF3) +#define GPIO_PAR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TIN1_DACK1 (0x04) +#define GPIO_PAR_TIN0_MASK (0xFC) +#define GPIO_PAR_TIN0_TIN0 (0x03) +#define GPIO_PAR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) + +#define GPIO_PAR_UART_U2TXD (0x80) +#define GPIO_PAR_UART_U2RXD (0x40) +#define GPIO_PAR_UART_U0TXD (0x20) +#define GPIO_PAR_UART_U0RXD (0x10) +#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) +#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) +#define GPIO_PAR_UART_RTS0_MASK (0xF3) +#define GPIO_PAR_UART_RTS0_U0RTS (0x0C) +#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) +#define GPIO_PAR_UART_CTS0_MASK (0xFC) +#define GPIO_PAR_UART_CTS0_U0CTS (0x03) +#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) +#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) + +#define GPIO_PAR_DEBUG_ALLPST (0x80) + +#define GPIO_PAR_SDHC_DATA3 (0x20) +#define GPIO_PAR_SDHC_DATA2 (0x10) +#define GPIO_PAR_SDHC_DATA1 (0x08) +#define GPIO_PAR_SDHC_DATA0 (0x04) +#define GPIO_PAR_SDHC_CMD (0x02) +#define GPIO_PAR_SDHC_CLK (0x01) + +#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6) +#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) +#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) +#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) +#define GPIO_PAR_SSIH_RXD_MASK (0x3F) +#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) +#define GPIO_PAR_SSIH_RXD_U1RXD (0x40) +#define GPIO_PAR_SSIH_TXD_MASK (0xCF) +#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) +#define GPIO_PAR_SSIH_TXD_U1TXD (0x10) +#define GPIO_PAR_SSIH_FS_MASK (0xF3) +#define GPIO_PAR_SSIH_FS_SSIFS (0x0C) +#define GPIO_PAR_SSIH_FS_U1RTS (0x04) +#define GPIO_PAR_SSIH_MCLK_MASK (0xFC) +#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) +#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) + +#define GPIO_PAR_SSIL_MASK (0x3F) +#define GPIO_PAR_SSIL_BCLK (0xC0) +#define GPIO_PAR_SSIL_U1CTS (0x40) + +#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCRn_MASK (0x1F) +#define GPIO_MSCR_MSCRn_SDR (0xE0) +#define GPIO_MSCR_MSCRn_25VDDR (0x60) +#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) +#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) + +#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) +#define GPIO_MSCR_MSCR5_MASK (0xE3) +#define GPIO_MSCR_MSCR5_SDR (0x1C) +#define GPIO_MSCR_MSCR5_25VDDR (0x0C) +#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) +#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) + +#define GPIO_SRCR_DSPI_MASK (0xFC) +#define GPIO_SRCR_DSPI(x) ((x) & 0x03) +#define GPIO_SRCR_I2C_MASK (0xFC) +#define GPIO_SRCR_I2C(x) ((x) & 0x03) +#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3) +#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) +#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC) +#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) +#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3) +#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) +#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC) +#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) +#define GPIO_SRCR_TIMER_MASK (0xFC) +#define GPIO_SRCR_TIMER(x) ((x) & 0x03) +#define GPIO_SRCR_UART2_MASK (0xF3) +#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) +#define GPIO_SRCR_UART0_MASK (0xFC) +#define GPIO_SRCR_UART0(x) ((x) & 0x03) +#define GPIO_SRCR_SDHC_MASK (0xFC) +#define GPIO_SRCR_SDHC(x) ((x) & 0x03) +#define GPIO_SRCR_SSI_MASK (0xFC) +#define GPIO_SRCR_SSI(x) ((x) & 0x03) + +#define SRCR_HIGHEST (0x03) +#define SRCR_HIGH (0x02) +#define SRCR_LOW (0x01) +#define SRCR_LOWEST (0x00) + +#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF) +#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) +#define GPIO_DSCR_FEC_RMII0_MASK (0xF3) +#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) +#define GPIO_DSCR_FEC_RMII1_MASK (0xFC) +#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) + +#define DSCR_50PF (0x03) +#define DSCR_30PF (0x02) +#define DSCR_20PF (0x01) +#define DSCR_10PF (0x00) + +#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80) +#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40) +#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20) +#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10) +#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08) +#define GPIO_PCRH_SSI_PULLUP_EN (0x02) +#define GPIO_PCRH_SSI_PULLUP (0x01) + +#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80) +#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40) +#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20) +#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10) +#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08) +#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04) + +/* *** Phase Locked Loop (PLL) *** */ +#define PLL_PCR_LOC_IRQ (0x00040000) +#define PLL_PCR_LOC_RE (0x00020000) +#define PLL_PCR_LOC_EN (0x00010000) +#define PLL_PCR_LOL_IRQ (0x00004000) +#define PLL_PCR_LOL_RE (0x00002000) +#define PLL_PCR_LOL_EN (0x00001000) +#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF) +#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) +#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0) +#define PLL_PCR_FBDIV(x) ((x) & 0x3F) + +#define PLL_PDR_OUTDIV4_MASK (0x0FFF) +#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) +#define PLL_PDR_OUTDIV3_MASK (0xF0FF) +#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) +#define PLL_PDR_OUTDIV2_MASK (0xFF0F) +#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) +#define PLL_PDR_OUTDIV1_MASK (0xFFF0) +#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) +#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) +#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) +#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x) +#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x) + +#define PLL_PSR_LOCF (0x00000200) +#define PLL_PSR_LOC (0x00000100) +#define PLL_PSR_LOLF (0x00000040) +#define PLL_PSR_LOCKS (0x00000020) +#define PLL_PSR_LOCK (0x00000010) +#define PLL_PSR_MODE(x) ((x) & 0x07) + +/* *** Real Time Clock *** */ +#define RTC_OCEN_OSCBYP (0x00000010) +#define RTC_OCEN_CLKEN (0x00000008) + +#endif /* m5301x_h */ -- 1.5.6.4

1 0

[U-Boot] [PATCH 16/19] ColdFire: Add MCF5301x CPU support
by Tsi-Chung Liew 22 Oct '08

22 Oct '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf532x/cpu.c | 21 +++++- cpu/mcf532x/cpu_init.c | 202 ++++++++++++++++++++++++++++++++++++++++++++---- cpu/mcf532x/speed.c | 119 ++++++++++++++++++++-------- cpu/mcf532x/start.S | 11 +++ 4 files changed, 304 insertions(+), 49 deletions(-) diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index fd77939..bcb092d 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) * * See file CREDITS for list of people who contributed to this @@ -56,6 +56,24 @@ int checkcpu(void) msk = (ccm->cir >> 6); ver = (ccm->cir & 0x003f); switch (msk) { +#ifdef CONFIG_MCF5301x + case 0x78: + id = 53010; + break; + case 0x77: + id = 53012; + break; + case 0x76: + id = 53015; + break; + case 0x74: + id = 53011; + break; + case 0x73: + id = 53013; + break; +#endif +#ifdef CONFIG_MCF532x case 0x54: id = 5329; break; @@ -77,6 +95,7 @@ int checkcpu(void) case 0x6B: id = 5372; break; +#endif } if (id) { diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 39be11f..687c7e4 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) * * See file CREDITS for list of people who contributed to this @@ -35,13 +35,180 @@ #include <asm/fec.h> #endif -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ +#ifdef CONFIG_MCF5301x +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + /*wdog->cr = 0; */ +#endif + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) + gpio->par_cs |= GPIO_PAR_CS0_CS0; + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) + gpio->par_cs |= GPIO_PAR_CS1_CS1; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS4; + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS5; + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; +#endif + + icache_enable(); +} + +/* initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFFEC + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; +#endif +#ifdef CONFIG_MCFRTC + volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); + volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; + + rtcex->gocu = CONFIG_SYS_RTC_CNT; + rtcex->gocl = CONFIG_SYS_RTC_SETUP; + +#endif +#ifdef CONFIG_MCFFEC + if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) + ccm->misccr |= CCM_MISCCR_FECM; + else + ccm->misccr &= ~CCM_MISCCR_FECM; +#endif + + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CONFIG_SYS_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + break; + case 1: +#ifdef CONFIG_SYS_UART1_ALT1_GPIO + gpio->par_simp1h &= + ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK); + gpio->par_simp1h |= + (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); +#elif defined(CONFIG_SYS_UART1_ALT2_GPIO) + gpio->par_ssih &= + ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK); + gpio->par_ssih |= + (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); +#endif + break; + case 2: +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); +#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->par_dspih &= + ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK); + gpio->par_dspih |= + (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_fec |= + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; + } else { + gpio->par_fec |= + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; + } + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_fec &= + ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK; + } else { + gpio->par_fec &= + ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK; + } + } + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif /* CONFIG_MCF5301x */ + +#ifdef CONFIG_MCF532x void cpu_init_f(void) { volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; @@ -68,13 +235,15 @@ void cpu_init_f(void) /* Port configuration */ gpio->par_cs = 0; -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) fbcs->csar0 = CONFIG_SYS_CS0_BASE; fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ gpio->par_cs |= GPIO_PAR_CS1; fbcs->csar1 = CONFIG_SYS_CS1_BASE; @@ -82,28 +251,32 @@ void cpu_init_f(void) fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) gpio->par_cs |= GPIO_PAR_CS2; fbcs->csar2 = CONFIG_SYS_CS2_BASE; fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) gpio->par_cs |= GPIO_PAR_CS3; fbcs->csar3 = CONFIG_SYS_CS3_BASE; fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) gpio->par_cs |= GPIO_PAR_CS4; fbcs->csar4 = CONFIG_SYS_CS4_BASE; fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) gpio->par_cs |= GPIO_PAR_CS5; fbcs->csar5 = CONFIG_SYS_CS5_BASE; fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; @@ -162,3 +335,4 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } #endif +#endif /* CONFIG_MCF532x */ diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index 1e40374..0d378e6 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) * * See file CREDITS for list of people who contributed to this @@ -36,26 +36,33 @@ DECLARE_GLOBAL_DATA_PTR; #define MAX_FVCO 500000 /* KHz */ #define MAX_FSYS 80000 /* KHz */ #define MIN_FSYS 58333 /* KHz */ + +#ifdef CONFIG_MCF5301x +#define FREF 20000 /* KHz */ +#define MAX_MFD 63 /* Multiplier */ +#define MIN_MFD 0 /* Multiplier */ +#define USBDIV 8 + +/* Low Power Divider specifications */ +#define MIN_LPD (0) /* Divider (not encoded) */ +#define MAX_LPD (15) /* Divider (not encoded) */ +#define DEFAULT_LPD (0) /* Divider (not encoded) */ +#endif + +#ifdef CONFIG_MCF532x #define FREF 16000 /* KHz */ #define MAX_MFD 135 /* Multiplier */ #define MIN_MFD 88 /* Multiplier */ -#define BUSDIV 6 /* Divider */ -/* - * Low Power Divider specifications - */ + +/* Low Power Divider specifications */ #define MIN_LPD (1 << 0) /* Divider (not encoded) */ #define MAX_LPD (1 << 15) /* Divider (not encoded) */ #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ +#endif -/* - * Get the value of the current system clock - * - * Parameters: - * none - * - * Return Value: - * The current output system frequency - */ +#define BUSDIV 6 /* Divider */ + +/* Get the value of the current system clock */ int get_sys_clock(void) { volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); @@ -65,9 +72,23 @@ int get_sys_clock(void) /* Test to see if device is in LIMP mode */ if (ccm->misccr & CCM_MISCCR_LIMP) { divider = ccm->cdr & CCM_CDR_LPDIV(0xF); +#ifdef CONFIG_MCF5301x + return (FREF / (3 * (1 << divider))); +#endif +#ifdef CONFIG_MCF532x return (FREF / (2 << divider)); +#endif } else { +#ifdef CONFIG_MCF5301x + u32 pfdr = (pll->pcr & 0x3F) + 1; + u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8)); + u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1; + + return (((FREF * pfdr) / refdiv) / busdiv); +#endif +#ifdef CONFIG_MCF532x return ((FREF * pll->pfdr) / (BUSDIV * 4)); +#endif } } @@ -92,7 +113,7 @@ int clock_limp(int div) div = MAX_LPD; /* Save of the current value of the SSIDIV so we don't overwrite the value */ - temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF)); + temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF)); /* Apply the divider to the system clock */ ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); @@ -102,15 +123,7 @@ int clock_limp(int div) return (FREF / (3 * (1 << div))); } -/* - * Exit low power LIMP mode - * - * Parameters: - * div Desired system frequency divider - * - * Return Value: - * The resulting output system frequency - */ +/* Exit low power LIMP mode */ int clock_exit_limp(void) { volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); @@ -139,7 +152,10 @@ int clock_exit_limp(void) */ int clock_pll(int fsys, int flags) { +#ifdef CONFIG_MCF532x volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); +#endif + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); int fref, temp, fout, mfd; u32 i; @@ -148,9 +164,17 @@ int clock_pll(int fsys, int flags) if (fsys == 0) { /* Return current PLL output */ +#ifdef CONFIG_MCF5301x + u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1; + mfd = (pll->pcr & 0x3F) + 1; + + return (fref * mfd) / busdiv; +#endif +#ifdef CONFIG_MCF532x mfd = pll->pfdr; return (fref * mfd / (BUSDIV * 4)); +#endif } /* Check bounds of requested system clock */ @@ -160,21 +184,33 @@ int clock_pll(int fsys, int flags) if (fsys < MIN_FSYS) fsys = MIN_FSYS; - /* Multiplying by 100 when calculating the temp value, - and then dividing by 100 to calculate the mfd allows - for exact values without needing to include floating - point libraries. */ + /* + * Multiplying by 100 when calculating the temp value, + * and then dividing by 100 to calculate the mfd allows + * for exact values without needing to include floating + * point libraries. + */ temp = (100 * fsys) / fref; +#ifdef CONFIG_MCF5301x + mfd = (BUSDIV * temp) / 100; + + /* Determine the output frequency for selected values */ + fout = ((fref * mfd) / BUSDIV); +#endif +#ifdef CONFIG_MCF532x mfd = (4 * BUSDIV * temp) / 100; /* Determine the output frequency for selected values */ fout = ((fref * mfd) / (BUSDIV * 4)); +#endif /* * Check to see if the SDRAM has already been initialized. * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL. */ + if (sdram->ctrl & SDRAMC_SDCR_REF) + sdram->ctrl &= ~SDRAMC_SDCR_CKE; /* * Initialize the PLL to generate the new system clock frequency. @@ -184,20 +220,37 @@ int clock_pll(int fsys, int flags) /* Enter LIMP mode */ clock_limp(DEFAULT_LPD); +#ifdef CONFIG_MCF5301x + pll->pdr = + PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | + PLL_PDR_OUTDIV2(BUSDIV - 1) | + PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | + PLL_PDR_OUTDIV4(USBDIV - 1); + + pll->pcr &= PLL_PCR_FBDIV_MASK; + pll->pcr |= PLL_PCR_FBDIV(mfd - 1); +#endif +#ifdef CONFIG_MCF532x /* Reprogram PLL for desired fsys */ pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); pll->pfdr = mfd; +#endif /* Exit LIMP mode */ clock_exit_limp(); + /* Return the SDRAM to normal operation if it is in use. */ + if (sdram->ctrl & SDRAMC_SDCR_REF) + sdram->ctrl |= SDRAMC_SDCR_CKE; + +#ifdef CONFIG_MCF532x /* - * Return the SDRAM to normal operation if it is in use. + * software workaround for SDRAM opeartion after exiting LIMP + * mode errata */ - - /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ *sdram_workaround = CONFIG_SYS_SDRAM_BASE; +#endif /* wait for DQS logic to relock */ for (i = 0; i < 0x200; i++) ; @@ -205,9 +258,7 @@ int clock_pll(int fsys, int flags) return fout; } -/* - * get_clocks() fills in gd->cpu_clock and gd->bus_clk - */ +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 7a3eb5f..8fa605a 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -2,6 +2,9 @@ * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner(a)telex.de> * Based on code from Bernhard Kuhn <bkuhn(a)metrowerks.com> * + * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -140,6 +143,14 @@ _start: movec %d0, %ACR0 movec %d0, %ACR1 +#ifdef CONFIG_MCF5301x + move.l #(0xFC0a0010), %a0 + move.w (%a0), %d0 + and.l %d0, 0xEFFF + + move.w %d0, (%a0) +#endif + /* initialize general use internal ram */ move.l #0, %d0 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 -- 1.5.6.4

1 0

[U-Boot] [PATCH 15/19] ColdFire: Add SBF support for M52277EVB
by Tsi-Chung Liew 22 Oct '08

22 Oct '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Add serial boot support Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 22 +++- board/freescale/m52277evb/config.mk | 4 +- board/freescale/m52277evb/m52277evb.c | 26 +++- board/freescale/m52277evb/u-boot.lds | 144 ------------------ board/freescale/m52277evb/u-boot.spa | 144 ++++++++++++++++++ board/freescale/m52277evb/u-boot.stm | 136 +++++++++++++++++ cpu/mcf5227x/Makefile | 2 +- cpu/mcf5227x/cpu_init.c | 20 ++- cpu/mcf5227x/dspi.c | 261 +++++++++++++++++++++++++++++++++ cpu/mcf5227x/speed.c | 30 +++- cpu/mcf5227x/start.S | 245 ++++++++++++++++++++++++++++++- include/asm-m68k/m5227x.h | 4 +- include/configs/M52277EVB.h | 155 +++++++++++++++----- 13 files changed, 987 insertions(+), 206 deletions(-) delete mode 100644 board/freescale/m52277evb/u-boot.lds create mode 100644 board/freescale/m52277evb/u-boot.spa create mode 100644 board/freescale/m52277evb/u-boot.stm create mode 100644 cpu/mcf5227x/dspi.c diff --git a/Makefile b/Makefile index fceb8a2..7a35676 100644 --- a/Makefile +++ b/Makefile @@ -1898,7 +1898,27 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### -M52277EVB_config: unconfig +M52277EVB_config \ +M52277EVB_spansion_config \ +M52277EVB_stmicro_config : unconfig + @case "$@" in \ + M52277EVB_config) FLASH=SPANSION;; \ + M52277EVB_spansion_config) FLASH=SPANSION;; \ + M52277EVB_stmicro_config) FLASH=STMICRO;; \ + esac; \ + if [ "$${FLASH}" = "SPANSION" ] ; then \ + echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \ + cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \ + $(XECHO) "... with SPANSION boot..." ; \ + fi; \ + if [ "$${FLASH}" = "STMICRO" ] ; then \ + echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \ + cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \ + $(XECHO) "... with ST Micro boot..." ; \ + fi @$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale M5235EVB_config \ diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk index ce014ed..b42fcc9 100644 --- a/board/freescale/m52277evb/config.mk +++ b/board/freescale/m52277evb/config.mk @@ -22,4 +22,6 @@ # MA 02111-1307 USA # -TEXT_BASE = 0 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c index 838a6de..9109edb 100644 --- a/board/freescale/m52277evb/m52277evb.c +++ b/board/freescale/m52277evb/m52277evb.c @@ -38,8 +38,18 @@ int checkboard(void) phys_size_t initdram(int board_type) { + u32 dramsize; + +#ifdef CONFIG_CF_SBF + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; +#else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - u32 dramsize, i; + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -49,6 +59,8 @@ phys_size_t initdram(int board_type) } i--; + gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; @@ -56,24 +68,30 @@ phys_size_t initdram(int board_type) /* Issue PALL */ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + __asm__("nop"); /* Issue LEMR */ - /*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */ sdram->sdmr = CONFIG_SYS_SDRAM_MODE; + __asm__("nop"); + sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; + __asm__("nop"); udelay(1000); /* Issue PALL */ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + __asm__("nop"); /* Perform two refresh cycles */ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + __asm__("nop"); sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + __asm__("nop"); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00; udelay(100); - +#endif return (dramsize); }; diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds deleted file mode 100644 index 7ae70d4..0000000 --- a/board/freescale/m52277evb/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf5227x/start.o (.text) - cpu/mcf5227x/libmcf5227x.a (.text) - lib_m68k/libm68k.a (.text) - lib_generic/libgeneric.a (.text) - common/cmd_mem.o (.text) - common/main.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/freescale/m52277evb/u-boot.spa b/board/freescale/m52277evb/u-boot.spa new file mode 100644 index 0000000..7ae70d4 --- /dev/null +++ b/board/freescale/m52277evb/u-boot.spa @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5227x/start.o (.text) + cpu/mcf5227x/libmcf5227x.a (.text) + lib_m68k/libm68k.a (.text) + lib_generic/libgeneric.a (.text) + common/cmd_mem.o (.text) + common/main.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m52277evb/u-boot.stm b/board/freescale/m52277evb/u-boot.stm new file mode 100644 index 0000000..03ff532 --- /dev/null +++ b/board/freescale/m52277evb/u-boot.stm @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5227x/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile index d0e9b45..44f9385 100644 --- a/cpu/mcf5227x/Makefile +++ b/cpu/mcf5227x/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c index 0f1dd1f..8945ef3 100644 --- a/cpu/mcf5227x/cpu_init.c +++ b/cpu/mcf5227x/cpu_init.c @@ -45,6 +45,7 @@ void cpu_init_f(void) volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; +#if !defined(CONFIG_CF_SBF) /* Workaround, must place before fbcs */ pll->psr = 0x12; @@ -58,37 +59,44 @@ void cpu_init_f(void) scm1->pacrg = 0; scm1->pacri = 0; -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) fbcs->csar0 = CONFIG_SYS_CS0_BASE; fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif +#endif /* CONFIG_CF_SBF */ -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) fbcs->csar1 = CONFIG_SYS_CS1_BASE; fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) fbcs->csar2 = CONFIG_SYS_CS2_BASE; fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) fbcs->csar3 = CONFIG_SYS_CS3_BASE; fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) fbcs->csar4 = CONFIG_SYS_CS4_BASE; fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) fbcs->csar5 = CONFIG_SYS_CS5_BASE; fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; fbcs->csmr5 = CONFIG_SYS_CS5_MASK; diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c new file mode 100644 index 0000000..7f48f91 --- /dev/null +++ b/cpu/mcf5227x/dspi.c @@ -0,0 +1,261 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> +#include <malloc.h> + +#if defined(CONFIG_CF_DSPI) +#include <asm/immap.h> + +void dspi_init(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + gpio->par_dspi = + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; + + dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 | + DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 | + DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | + DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; + +#ifdef CONFIG_SYS_DSPI_DCTAR0 + dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR1 + dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR2 + dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR3 + dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR4 + dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR5 + dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR6 + dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6; +#endif +#ifdef CONFIG_SYS_DSPI_DCTAR7 + dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7; +#endif +} + +void dspi_tx(int chipsel, u8 attrib, u16 data) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->dsr & 0x0000F000) >= 4) ; + + dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data; +} + +u16 dspi_rx(void) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->dsr & 0x000000F0) == 0) ; + + return (dspi->drfr & 0xFFFF); +} + +#if defined(CONFIG_CMD_SPI) +void spi_init_f(void) +{ +} + +void spi_init_r(void) +{ +} + +void spi_init(void) +{ + dspi_init(); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct spi_slave *slave; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 2: + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; + break; + } + + slave->bus = bus; + slave->cs = cs; + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + switch (slave->cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 2: + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + break; + } + + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + static int bWrite = 0; + u8 *spi_rd, *spi_wr; + int len = bitlen >> 3; + + spi_rd = (u8 *) din; + spi_wr = (u8 *) dout; + + /* command handling */ + if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) { + switch (*spi_wr) { + case 0x02: /* Page Prog */ + bWrite = 1; + dspi_tx(slave->cs, 0x80, spi_wr[0]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[1]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[2]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[3]); + dspi_rx(); + return 0; + case 0x05: /* Read Status */ + if (len == 4) + if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF) + && (spi_wr[3] == 0xFF)) { + dspi_tx(slave->cs, 0x80, *spi_wr); + dspi_rx(); + } + return 0; + case 0x06: /* WREN */ + dspi_tx(slave->cs, 0x00, *spi_wr); + dspi_rx(); + return 0; + case 0x0B: /* Fast read */ + if ((len == 5) && (spi_wr[4] == 0)) { + dspi_tx(slave->cs, 0x80, spi_wr[0]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[1]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[2]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[3]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[4]); + dspi_rx(); + } + return 0; + case 0x9F: /* RDID */ + dspi_tx(slave->cs, 0x80, *spi_wr); + dspi_rx(); + return 0; + case 0xD8: /* Sector erase */ + if (len == 4) + if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) { + dspi_tx(slave->cs, 0x80, spi_wr[0]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[1]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[2]); + dspi_rx(); + dspi_tx(slave->cs, 0x00, spi_wr[3]); + dspi_rx(); + } + return 0; + } + } + + if (bWrite) + len--; + + while (len--) { + if (dout != NULL) { + dspi_tx(slave->cs, 0x80, *spi_wr); + dspi_rx(); + spi_wr++; + } + + if (din != NULL) { + dspi_tx(slave->cs, 0x80, 0); + *spi_rd = dspi_rx(); + spi_rd++; + } + } + + if (flags == SPI_XFER_END) { + if (bWrite) { + dspi_tx(slave->cs, 0x00, *spi_wr); + dspi_rx(); + bWrite = 0; + } else { + dspi_tx(slave->cs, 0x00, 0); + dspi_rx(); + } + } + + return 0; +} +#endif /* CONFIG_CMD_SPI */ + +#endif /* CONFIG_CF_DSPI */ diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c index 74b9059..7e385d3 100644 --- a/cpu/mcf5227x/speed.c +++ b/cpu/mcf5227x/speed.c @@ -90,17 +90,33 @@ int get_clocks(void) int vco, temp, pcrvalue, pfdr; u8 bootmode; - bootmode = (ccm->ccr & 0x000C) >> 2; - pcrvalue = pll->pcr & 0xFF0F0FFF; pfdr = pcrvalue >> 24; - if (pfdr != 0x1E) { + if (pfdr == 0x1E) + bootmode = 0; /* Normal Mode */ + +#ifdef CONFIG_CF_SBF + bootmode = 3; /* Serial Mode */ +#endif + + if (bootmode == 0) { + /* Normal mode */ + vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { + /* Default value */ + pcrvalue = (pll->pcr & 0x00FFFFFF); + pcrvalue |= 0x1E << 24; + pll->pcr = pcrvalue; + vco = + ((pll->pcr & 0xFF000000) >> 24) * + CONFIG_SYS_INPUT_CLKSRC; + } + gd->vco_clk = vco; /* Vco clock */ + } else if (bootmode == 3) { /* serial mode */ - } else { - /* Normal Mode */ - vco = pfdr * CONFIG_SYS_INPUT_CLKSRC; - gd->vco_clk = vco; + vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + gd->vco_clk = vco; /* Vco clock */ } if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index becaab7..9387250 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -46,6 +46,11 @@ addl #60,%sp; /* space for 15 regs */ \ rte; +#if defined(CONFIG_CF_SBF) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#endif + .text /* * Vector table. This is used for initial platform startup. @@ -53,8 +58,14 @@ */ _vectors: -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +#if defined(CONFIG_CF_SBF) +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ +#else +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +#endif + vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ @@ -83,6 +94,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */ vector1E: .long _FAULT /* Autovector Level 6 */ vector1F: .long _FAULT /* Autovector Level 7 */ +#if !defined(CONFIG_CF_SBF) /* TRAP #0 - #15 */ vector20_2F: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -122,9 +134,231 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif - .text +#if defined(CONFIG_CF_SBF) + /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ +asm_sbf_img_hdr: + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00020000 /* image length */ + .long TEXT_BASE /* image to be relocated at */ + +asm_dram_init: + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 /* init Rambar */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CONFIG_SYS_CS0_MASK), (%a1) + + /* + * Dram Initialization + * a1, a2, and d0 + */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 +#ifdef CONFIG_SYS_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop + + /* SDRAM Chip 0 and 1 */ + move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CONFIG_SYS_SDRAM_BASE1 + move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) + nop + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Issue LEMR */ + move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) + nop + move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) + nop + + move.l #1000, %d0 +wait1000: + nop + subq.l #1, %d0 + bne wait1000 + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop + + move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 + and.l #0x7FFFFFFF, %d0 + or.l #0x10000c00, %d0 + move.l %d0, (%a2) + nop + + /* + * DSPI Initialization + * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h + * a1 - dspi status + * a2 - dtfr + * a3 - drfr + * a4 - Dst addr + */ + + /* Enable pins for DSPI mode - chip-selects are enabled later */ + move.l #0xFC0A4036, %a0 + move.b #0x3F, %d0 + move.b %d0, (%a0) + + /* DSPI CS */ +#ifdef CONFIG_SYS_DSPI_CS0 + move.b (%a0), %d0 + or.l #0xC0, %d0 + move.b %d0, (%a0) +#endif +#ifdef CONFIG_SYS_DSPI_CS2 + move.l #0xFC0A4037, %a0 + move.b (%a0), %d0 + or.l #0x10, %d0 + move.b %d0, (%a0) +#endif + nop + + /* Configure DSPI module */ + move.l #0xFC05C000, %a0 + move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ + + move.l #0xFC05C00C, %a0 + move.l #0x3E000011, (%a0) + + move.l #0xFC05C034, %a2 /* dtfr */ + move.l #0xFC05C03B, %a3 /* drfr */ + + move.l #(ASM_SBF_IMG_HDR + 4), %a1 + move.l (%a1)+, %d5 + move.l (%a1), %a4 + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + + move.l #0xFC05C02C, %a1 /* dspi status */ + + /* Issue commands and address */ + move.l #0x8004000B, %d2 /* Fast Read Cmd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Address byte 2 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Address byte 1 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Address byte 0 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Dummy Wr and Rd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* Transfer serial boot header to sram */ +asm_dspi_rd_loop1: + move.l #0x80040000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a0) /* read, copy to dst */ + + add.l #1, %a0 /* inc dst by 1 */ + sub.l #1, %d4 /* dec cnt by 1 */ + bne asm_dspi_rd_loop1 + + /* Transfer u-boot from serial flash to memory */ +asm_dspi_rd_loop2: + move.l #0x80040000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a4) /* read, copy to dst */ + + add.l #1, %a4 /* inc dst by 1 */ + sub.l #1, %d5 /* dec cnt by 1 */ + bne asm_dspi_rd_loop2 + + move.l #0x00040000, %d2 /* Terminate */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + move.l %a0, (%a1) + jmp (%a0) + +asm_dspi_wr_status: + move.l (%a1), %d0 /* status */ + and.l #0x0000F000, %d0 + cmp.l #0x00003000, %d0 + bgt asm_dspi_wr_status + + move.l %d2, (%a2) + rts + +asm_dspi_rd_status: + move.l (%a1), %d0 /* status */ + and.l #0x000000F0, %d0 + lsr.l #4, %d0 + cmp.l #0, %d0 + beq asm_dspi_rd_status + + move.b (%a3), %d1 + rts +#endif /* CONFIG_CF_SBF */ + + .text + . = 0x400 .globl _start _start: nop @@ -132,11 +366,16 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ +#if defined(CONFIG_CF_SBF) + move.l #TEXT_BASE, %d0 + movec %d0, %VBR +#else move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 +#endif /* initialize general use internal ram */ move.l #0, %d0 diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h index 61bc0ad..824d333 100644 --- a/include/asm-m68k/m5227x.h +++ b/include/asm-m68k/m5227x.h @@ -282,8 +282,8 @@ /* Bit definitions and macros for PAR_DSPI */ #define GPIO_PAR_DSPI_PCS0_MASK (0x3F) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0x80) -#define GPIO_PAR_DSPI_PCS0_U2RTS (0x40) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) +#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) #define GPIO_PAR_DSPI_SIN_MASK (0xCF) #define GPIO_PAR_DSPI_SIN_SIN (0x30) diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index b6226c6..5d5966f 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -40,7 +40,7 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG @@ -72,21 +72,50 @@ #define CONFIG_CMD_REGINFO #undef CONFIG_CMD_USB #undef CONFIG_CMD_BMP - -#define CONFIG_HOSTNAME M52277EVB +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF + +#define CONFIG_HOSTNAME M52277EVB +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#ifdef CONFIG_SYS_STMICRO_BOOT +/* ST Micro serial flash */ #define CONFIG_EXTRA_ENV_SETTINGS \ "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=loadb ${loadaddr} ${baudrate};" \ + "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 0x3ffff;" \ - "era 0 3ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=sf probe 0:2 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ "save\0" \ "" +#endif +#ifdef CONFIG_SYS_SPANSION_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=loadb ${loadaddr} ${baudrate}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \ + " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \ + "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \ + MK_STR(CONFIG_SYS_UBOOT_END) ";" \ + "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \ + " ${filesize}; save\0" \ + "updsbf=run loadsbf; run progsbf\0" \ + "loadsbf=loadb ${loadaddr} ${baudrate};" \ + "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ + "progsbf=sf probe 0:2 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ + "" +#endif -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ /* LCD */ #ifdef CONFIG_CMD_BMP #define CONFIG_LCD @@ -102,7 +131,7 @@ #define CONFIG_DOS_PARTITION #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION -#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 +#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 #define CONFIG_SYS_USB_EHCI_CPU_INIT #endif @@ -122,30 +151,53 @@ #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_HARD_SPI +#define CONFIG_SYS_SER_FLASH_BASE 0x01000000 +#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#ifdef CONFIG_CMD_SPI +# define CONFIG_SYS_DSPI_CS2 +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_STMICRO + +# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ + DSPI_DCTAR_CPOL | \ + DSPI_DCTAR_CPHA | \ + DSPI_DCTAR_PCSSCK_1CLK | \ + DSPI_DCTAR_PASC(0) | \ + DSPI_DCTAR_PDT(0) | \ + DSPI_DCTAR_CSSCK(0) | \ + DSPI_DCTAR_ASC(0) | \ + DSPI_DCTAR_PBR(0) | \ + DSPI_DCTAR_DT(1) | \ + DSPI_DCTAR_BR(1)) +#endif /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK #define CONFIG_SYS_INPUT_CLKSRC 16000000 -#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_MBAR 0xFC000000 @@ -155,17 +207,18 @@ * You should know what you are doing if you make changes here. */ -/*----------------------------------------------------------------------- +/* * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 16) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32) -/*----------------------------------------------------------------------- +/* * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 @@ -177,11 +230,16 @@ #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#ifdef CONFIG_CF_SBF +# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) +#else +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -189,24 +247,40 @@ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -/* Configuration for environment +/* + * Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OVERWRITE 1 +#ifdef CONFIG_CF_SBF +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_CS 2 +#else +# define CONFIG_ENV_IS_IN_FLASH 1 +#endif +#define CONFIG_ENV_OVERWRITE 1 #undef CONFIG_ENV_IS_EMBEDDED /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000) -#define CONFIG_ENV_SECT_SIZE 0x8000 +#ifdef CONFIG_SYS_STMICRO_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE +# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_ENV_OFFSET 0x30000 +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_SECT_SIZE 0x10000 +#endif +#ifdef CONFIG_SYS_SPANSION_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000) +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_SECT_SIZE 0x8000 +#endif #define CONFIG_SYS_FLASH_CFI #ifdef CONFIG_SYS_FLASH_CFI - # define CONFIG_FLASH_CFI_DRIVER 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT @@ -214,6 +288,7 @@ # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ # define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } #endif /* @@ -229,7 +304,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 +#define CONFIG_SYS_CACHELINE_SIZE 16 /*----------------------------------------------------------------------- * Memory bank definitions @@ -243,8 +318,14 @@ * CS5 - Available */ +#ifdef CONFIG_CF_SBF +#define CONFIG_SYS_CS0_BASE 0x04000000 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#else #define CONFIG_SYS_CS0_BASE 0x00000000 #define CONFIG_SYS_CS0_MASK 0x00FF0001 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#endif #endif /* _M52277EVB_H */ -- 1.5.6.4

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