October 2007 - U-Boot

[U-Boot-Users] Hang in env_relocate
by Rune Torgersen 23 Oct '07

23 Oct '07

Hi I am trying to update a board (Freescale 8280 cpu) from u-boot 1.1.4 to 1.3.0-rc3 Right now it is hanging in env_relocate (env_common.c:124). It is calling malloc for a size of 64k (65536) and malloc is hanging in a for loop in dlmalloc.c:2191 Does anybody have any pointer to what could be happening? screen output with debug and DEBUGF enabled U-Boot 1.3.0-rc3 (Oct 19 2007 - 16:21:08) MPC8260 Reset Status: External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 4.5x, VCO Div 2, 60x Bus Freq 22-65 , Core Freq 100-300 - dfbrg 0, corecnf 0x17, busdf 5, cpmdf 1, plldf 0, pllmf 5, pcidf 11 - vco_out 597196800, scc_clk 149299200, brg_clk 149299200 - cpu_clk 447897600, cpm_clk 298598400, bus_clk 99532800 CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 447.897 MHz Board: Innovative Systems AP2, CPU1 UPMs: Configured FPGA: (cfgaddr 0xff810000)............ Status = OK Altera ID: 0x110e I2C: ready DRAM: DIMM socket probe: Slot1 = 1, Slot2 =1 SDRAM configuration read from SPD Size per side = 256MB Organization: 4 sides, 4 banks, 10 Columns, 13 Rows, Width = 64 bits Refresh rate = 13, CAS latency = 2, Using Page Based interleave Total size: 1024 MB Top of RAM usable for U-Boot at: 10000000 Reserving 212k for U-Boot at: 0ffca000 Reserving 192k for malloc() at: 0ff9a000 Reserving 84 Bytes for Board Info at: 0ff99fac Reserving 72 Bytes for Global Data at: 0ff99f64 Stack Pointer at: 0ff99f48 New Stack Pointer is: 0ff99f48 Now running in RAM - U-Boot at: 0ffca000 FLASH: flash_protect ON: from 0xFFF00000 to 0xFFF3FFFF flash_protect ON: from 0xFFF40000 to 0xFFF4FFFF 8 MB env_relocate[197] offset = 0x0

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[U-Boot-Users] mx1ads hangs up
by giorrrgio＠gmail.com 23 Oct '07

23 Oct '07

Hi to all, I'm new to the mailing list and I'm working on the mx1ads board (v. 1.1) for a project at the university. I've compiled the 1.3 rc3 version of u-boot with the proper configure and loaded it on the board with motorola bootloader utilities through usb. After reboot, the systems hangs up immediately and no output is given. By now I can't use JTAG and I'd like to know if there are known issues for this board in the 1.1 version or if you have any trick to make it work. Thanks a lot. Giorgio Cefaro Rome

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[U-Boot-Users] reserving RAM via bootargs
by Surya Ravikiran 22 Oct '07

22 Oct '07

I have a 256MB SDRAM, and setting the mem=252m for somereason results in the kernel using a total memory of 186MB, can anyone comment on why this would be hapenning? During bootup this is what I see: Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=64Mb residual: 48Mb Memory: 191232k available (2628k kernel code, 800k data, 128k init, 0k highmem) and after bootup: cat /proc/meminfo gives this.. MemTotal: 191404 kB MemFree: 172372 kB Buffers: 0 kB Cached: 10276 kB SwapCached: 0 kB Active: 8720 kB Inactive: 3836 kB HighTotal: 0 kB HighFree: 0 kB LowTotal: 191404 kB LowFree: 172372 kB SwapTotal: 0 kB SwapFree: 0 kB Dirty: 76 kB Writeback: 0 kB Mapped: 5464 kB Slab: 4824 kB CommitLimit: 95700 kB Committed_AS: 6644 kB PageTables: 288 kB VmallocTotal: 786144 kB VmallocUsed: 476 kB VmallocChunk: 785292 kB thanks

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[U-Boot-Users] reserving RAM
by Surya Ravikiran 22 Oct '07

22 Oct '07

Hi, I am using a freescale eval board with 256M DDR, and want to bootup the Linux kernel with only a part of this memory, I tried setting the memsize env variable to (equivalent of this value in hex), no use. then i appened bootargs with "boot=128m", and saveenv. Linux still boots without the appended bootargs, any ideas what is causing this? thanks

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[U-Boot-Users] subscription
by Surya Ravikiran 22 Oct '07

22 Oct '07

I want to subscribe to this list

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[U-Boot-Users] 85xx running in RAM problems
by robert lazarski 22 Oct '07

22 Oct '07

Hi all, On my custom 8548 board I'm getting two different results - with a BDI [INIT] config, and without. With the BDI [INIT] config, I can get farther by setting the DDR2 ram size to be 256MB instead of what I have, 1GB. I have no other SDRAM besides DDR2. Sorry for the long post. I can set in the BDI the following: ;# CS0_BNDS ;# bit 8-15 - starting address ;# bit 24-31 - ending address, configured for 256MB WM32 0xE0002000 0x0000000f ; DDR CS0 ;# CS0_CONFIG WM32 0xE0002080 0x80000102 ;# TIMING_CFG_0 WM32 0xE0002104 0x00260802 ;# TIMING_CFG_1 WM32 0xE0002108 0x38355322 And by doing so, I can get U-boot running in ram: U-Boot 1.3.0-rc1-g67c31036-dirty (Oct 18 2007 - 11:43:18) CPU: 8548_E, Version: 2.0, (0x80390020) Core: E500, Version: 2.0, (0x80210020) Clock Configuration: CPU: 888 MHz, CCB: 355 MHz, DDR: 177 MHz, LBC: 22 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: MPC8548ATUM I2C: ready DRAM: Initializing spd_sdram cs0 already configured, bnds=f Reusing current 256MB configuration DDR: MAS0=0x10080000 DDR: MAS1=0xc0000900 DDR: MAS2=0x00000000 DDR: MAS3=0x00000015 DDR: LAWBAR1=0x00000000 DDR: LARAR1=0x80f0001b DDR: 256 MB Top of RAM usable for U-Boot at: 10000000 Reserving 207k for U-Boot at: 0ffc0000 Reserving 136k for malloc() at: 0ff9e000 Reserving 80 Bytes for Board Info at: 0ff9dfb0 Reserving 48 Bytes for Global Data at: 0ff9df80 Stack Pointer at: 0ff9df68 New Stack Pointer is: 0ff9df68 Now running in RAM - U-Boot at: 0ffc0000 FLASH: flash detect cfi fwc addr f8000000 cmd 0 0 8bit x 8 bit fwc addr f8000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr f8000010 is= ff 51 fwc addr f8000555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr f8000010 is= ff 51 fwc addr f8000000 cmd 0 0000 16bit x 8 bit fwc addr f80000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr f8000020 is= 0051 5151 fwc addr f8000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr f8000020 is= 0051 5151 fwc addr f8000000 cmd 0 0000 16bit x 16 bit fwc addr f80000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr f8000020 is= 0051 0051 is= cmd 52(R) addr f8000022 is= 0052 0052 is= cmd 59(Y) addr f8000024 is= 0059 0059 ushort addr is at f8000050 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 device interface is 2 found port 2 chip 2 port 16 bits chip 16 bits ushort addr is at f8000026 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 fwc addr f8000000 cmd f0 00f0 16bit x 16 bit fwc addr f8000aaa cmd aa 00aa 16bit x 16 bit fwc addr f8000554 cmd 55 0055 16bit x 16 bit fwc addr f8000aaa cmd 90 0090 16bit x 16 bit fwc addr f8000000 cmd f0 00f0 16bit x 16 bit fwc addr f80000aa cmd 98 0098 16bit x 16 bit ushort addr is at f800002a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x40 addr[2] = 0x0 addr[3] = 0x0 retval = 0x40 f8000020 : 00 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 .Q.R.Y.....@.... f8000030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 06 .......'.6...... f8000040 : 00 06 00 09 00 13 00 03 00 05 00 03 00 02 00 1b ................ f8000050 : 00 02 00 00 00 06 00 00 00 01 00 ff 00 03 00 00 ................ f8000060 : 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ f8000070 : 00 00 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ................ f8000080 : 00 50 00 52 00 49 00 31 00 33 00 14 00 02 00 01 .P.R.I.1.3...... f8000090 : 00 00 00 08 00 00 00 00 00 02 00 b5 00 c5 00 05 ................ manufacturer is 2 manufacturer id is 0x1 device id is 0x7e device id2 is 0x2801 cfi version is 0x3133 size_ratio 1 port 16 bits chip 16 bits found 1 erase regions long addr is at f800005a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0xff addr[2] = 0x0 addr[3] = 0x3 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x0 addr[7] = 0x2 erase_region_count = 1024 erase_region_size = 131072 ushort addr is at f8000054 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x6 addr[2] = 0x0 addr[3] = 0x0 retval = 0x6 fwc addr f8000000 cmd f0 00f0 16bit x 16 bit flash_protect ON: from 0xFFF80000 to 0xFFFAD4FF protect on 1020 protect on 1021 flash_protect ON: from 0xFFFC0000 to 0xFFFFFFFF protect on 1022 protect on 1023 128 MB L2 cache 512KB: already enabled. *** Warning - bad CRC, using default environment pci_init_board: devdisr=700c0001, io_sel=6, host_agent=7 PCIE1: disabled PCI1: 32 bit, 33 MHz, sync, host, arbiter (base address e0008000) Scanning PCI bus 00 PCI1 on bus 00 - 00 PCI2: disabled In: serial Out: serial Err: serial U-Boot relocated to 0ffc0000 iivpr1@e005 Where it hangs after setting IVPR - another problem I'll tackle after my DDR2 issues. Note the above "cs0 already configured, bnds=f" from spd_sdram() . If I set bnds=3f (1GB) via the BDI - or run with any BDI INIT and just rely on spd_sdram() , it hangs here: Stack Pointer at: 3ff9df68 New Stack Pointer is: 3ff9df68 The only place I'm setting up DDR2 besides calling spd_sdram() is here: .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN And here: #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ Any ideas? Robert

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[U-Boot-Users] [PATCH 1/1] Fix mips_io_port_base multiple declaration
by Jean-Christophe PLAGNIOL-VILLARD 22 Oct '07

22 Oct '07

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index d29e8d5..687a69c 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -26,6 +26,8 @@ #include <asm/au1x00.h> #include <asm/mipsregs.h> +unsigned long mips_io_port_base = 0; + long int initdram(int board_type) { /* Sdram is setup by assembler code */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index bb064ea..feb89d6 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -54,10 +54,6 @@ #ifndef __PPC__ #include <asm/io.h> -#ifdef __MIPS__ -/* Macros depend on this variable */ -unsigned long mips_io_port_base = 0; -#endif #endif #ifdef CONFIG_IDE_8xx_DIRECT -- 1.5.3.2

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[U-Boot-Users] [PATCH] TQM5200: fix spurious characters on second serial interface
by Martin Krause 22 Oct '07

22 Oct '07

With this patch PSC3 is configured as UART. This is done, because if the pins of PSC3 are not configured at all (-> all pins are GPI), due to crosstalk, spurious characters may be send over the RX232_2_TXD signal line. Signed-off-by: Martin Krause <martin.krause(a)tqs.de> --- If I receive no negative comments to this patch, I will pick it to the u-boot-tq-group repository and send a pull request. Best regards, Martin include/configs/TQM5200.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index d553404..c3f16f5 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -547,7 +547,7 @@ # if defined (CONFIG_TQM5200_REV100) # error TQM5200 REV100 not supported on STK52XX REV200 or above # else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 +# define CFG_GPS_PORT_CONFIG 0x91500404 # endif # endif #elif defined (CONFIG_FO300)

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[U-Boot-Users] download the u-boot.bin to flash ...but when power on ...nothing promted out
by xbc_5419 22 Oct '07

22 Oct '07

hi,guys... i am new to the u-boot....and wanna to port the u-boot.1.2.0....to a board based on at91rm9200, i had a compiled u-boot.bin...but when i downloaded it to the flash....reboot...nothing promt out i modified according the at91rm9200dk.... what does boot.bin and loader.bin work for? Do I have to have these two file? 1.Add a new configuration option for my board to the toplevel "Makefile" and to the "MAKEALL" script 2.Create a new directory to hold the specific code. Add any files you need. In your board directory, you will need at least the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds". 3.Create a new configuration file "include/configs/<board>.h" for my board... 4. Run "make <board>_config" with your new name. 5.make everything is all right except not message promted out. thanks Jack Xu 2007-10-22

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[U-Boot-Users] PXA GPIOs settings on resume
by Rodolfo Giometti 22 Oct '07

22 Oct '07

Hello, looking at CPU init during resume I noticed that the GPIOs settings is always executed (see for instance the first lines of file board/adsvix/lowlevel_init.S), but since PXA27x Developer's manual says at paragraph 3.8.1.9 that: "These registers [PGSRx] are reset upon sleep or deep-sleep exit, so the configuration of the GPIO pins must be read from external memory. However, the GPIO state itself is not changed until software resets PSSR[PH]. we should setup, during resume, the GPIOs from Linux (or whatever OS we are using). So the code: lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 ldr r1, =CFG_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 ldr r1, =CFG_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 ldr r1, =CFG_GPSR2_VAL str r1, [r0] ldr r0, =GPSR3 ldr r1, =CFG_GPSR3_VAL str r1, [r0] ldr r0, =GPCR0 ldr r1, =CFG_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 ldr r1, =CFG_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 ldr r1, =CFG_GPCR2_VAL str r1, [r0] ldr r0, =GPCR3 ldr r1, =CFG_GPCR3_VAL str r1, [r0] ldr r0, =GPDR0 ldr r1, =CFG_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 ldr r1, =CFG_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 ldr r1, =CFG_GPDR2_VAL str r1, [r0] ldr r0, =GPDR3 ldr r1, =CFG_GPDR3_VAL str r1, [r0] ldr r0, =GAFR0_L ldr r1, =CFG_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U ldr r1, =CFG_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L ldr r1, =CFG_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U ldr r1, =CFG_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L ldr r1, =CFG_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U ldr r1, =CFG_GAFR2_U_VAL str r1, [r0] ldr r0, =GAFR3_L ldr r1, =CFG_GAFR3_L_VAL str r1, [r0] ldr r0, =GAFR3_U ldr r1, =CFG_GAFR3_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ ldr r1, =CFG_PSSR_VAL str r1, [r0] should be remove from per-board lowlevel_init.S and put into cpu/pxa/start.S after the lowlevel_init alling: /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will * find a lowlevel_init.S in your board directory. */ mov ip, lr bl lowlevel_init mov lr, ip <<HERE>> or, at least, after the test: wakeup: /* Are we waking from sleep? */ ldr r0, =RCSR ldr r1, [r0] and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) str r1, [r0] teq r1, #RCSR_SMR in lowlevel_init.S. Then the OS should manage the GPIOs resume at their old status before sleeping. In this manner we can get fully configurable GPIOs status setting during transition from suspend to resume. Comments? :) Ciao, Rodolfo P.S. Of course, if my supposition is correct I'll provide GPIOs resume in Linux too. -- GNU/Linux Solutions e-mail: giometti(a)enneenne.com Linux Device Driver giometti(a)gnudd.com Embedded Systems giometti(a)linux.it UNIX programming phone: +39 349 2432127

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