September 2024 - U-Boot

[PATCH 1/3] tpm: update tpm hash algorithm according to tpm2.0 spec 1.59
by Benjamin BARATTE 09 Sep '24

09 Sep '24

The hash algorithm structure shall reflect the TCG specification for TPM2.0 With vesion 1.59, the SHA3 algorithm has been added and shall be reflected in this structure. The fact that U-Boot does or does not support SHA3 algo yet is not relevant for this structure. It's up to the end user to configure the active PCR bank to supported hash algorithm by all boot chain component. Also, by default, TPM2.0 shall support at least SHA256 and SHA384, in practice dTPM support 2 actives banks with this 2 hash algorithms Signed-off-by: Benjamin BARATTE mailto:benjamin.baratte@st.com --- include/tpm-v2.h | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 4fd19c52fd..9848e1fd10 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -253,6 +253,9 @@ enum tpm2_algorithms { TPM2_ALG_SHA512 = 0x0D, TPM2_ALG_NULL = 0x10, TPM2_ALG_SM3_256 = 0x12, + TPM2_ALG_SHA3_256 = 0x27, + TPM2_ALG_SHA3_384 = 0x28, + TPM2_ALG_SHA3_512 = 0x29, }; /** @@ -271,11 +274,15 @@ struct digest_info { }; /* Algorithm Registry */ -#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001 -#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002 -#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004 -#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008 -#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 +#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001 +#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002 +#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004 +#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008 +#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 +#define TCG2_BOOT_HASH_ALG_SHA3_256 0x00000020 +#define TCG2_BOOT_HASH_ALG_SHA3_384 0x00000040 +#define TCG2_BOOT_HASH_ALG_SHA3_512 0x00000080 + static const struct digest_info hash_algo_list[] = { #if IS_ENABLED(CONFIG_SHA1) @@ -310,6 +317,24 @@ static const struct digest_info hash_algo_list[] = { TPM2_SHA512_DIGEST_SIZE, }, #endif + { + "sha3_256", + TPM2_ALG_SHA3_256, + TCG2_BOOT_HASH_ALG_SHA3_256, + TPM2_SHA256_DIGEST_SIZE, + }, + { + "sha3_384", + TPM2_ALG_SHA3_384, + TCG2_BOOT_HASH_ALG_SHA3_384, + TPM2_SHA384_DIGEST_SIZE, + }, + { + "sha3_512", + TPM2_ALG_SHA3_512, + TCG2_BOOT_HASH_ALG_SHA3_512, + TPM2_SHA512_DIGEST_SIZE, + }, }; /* NV index attributes */ -- 2.34.1 ST Restricted

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[PATCH 3/3] tpm_tcg2: hash algo optimization
by Benjamin BARATTE 09 Sep '24

09 Sep '24

To properly enable code optimization with hash algorithm, all the reference of the hash algo should condition to hash enablement. It is possible to fine tune the list of hash algorithms based on dTPM configuration. Therefore if dTPM supports only one bank, on one hash algorithm could be selected (TCG PTP specification mention in case of single bank support that SHA256 must be support and default value) Signed-off-by: Benjamin BARATTE <benjamin.baratte(a)st.com> --- include/tpm-v2.h | 8 -------- lib/efi_loader/Kconfig | 4 ---- lib/tpm_tcg2.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 12 deletions(-) diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 9848e1fd10..ec3504de44 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -285,38 +285,30 @@ struct digest_info { static const struct digest_info hash_algo_list[] = { -#if IS_ENABLED(CONFIG_SHA1) { "sha1", TPM2_ALG_SHA1, TCG2_BOOT_HASH_ALG_SHA1, TPM2_SHA1_DIGEST_SIZE, }, -#endif -#if IS_ENABLED(CONFIG_SHA256) { "sha256", TPM2_ALG_SHA256, TCG2_BOOT_HASH_ALG_SHA256, TPM2_SHA256_DIGEST_SIZE, }, -#endif -#if IS_ENABLED(CONFIG_SHA384) { "sha384", TPM2_ALG_SHA384, TCG2_BOOT_HASH_ALG_SHA384, TPM2_SHA384_DIGEST_SIZE, }, -#endif -#if IS_ENABLED(CONFIG_SHA512) { "sha512", TPM2_ALG_SHA512, TCG2_BOOT_HASH_ALG_SHA512, TPM2_SHA512_DIGEST_SIZE, }, -#endif { "sha3_256", TPM2_ALG_SHA3_256, diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index ee71f41714..512fb710b5 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -405,10 +405,6 @@ config EFI_TCG2_PROTOCOL bool "EFI_TCG2_PROTOCOL support" default y depends on TPM_V2 - select SHA1 - select SHA256 - select SHA384 - select SHA512 select HASH select SMBIOS_PARSER help diff --git a/lib/tpm_tcg2.c b/lib/tpm_tcg2.c index 7f868cc883..66573b838d 100644 --- a/lib/tpm_tcg2.c +++ b/lib/tpm_tcg2.c @@ -96,9 +96,15 @@ int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, struct tpml_digest_values *digest_list) { u8 final[sizeof(union tpmu_ha)]; +#if IS_ENABLED(CONFIG_SHA256) sha256_context ctx_256; +#endif +#if IS_ENABLED(CONFIG_SHA384) || IS_ENABLED(CONFIG_SHA512) sha512_context ctx_512; +#endif +#if IS_ENABLED(CONFIG_SHA1) sha1_context ctx; +#endif u32 active; size_t i; u32 len; @@ -114,30 +120,38 @@ int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, continue; switch (hash_algo_list[i].hash_alg) { +#if IS_ENABLED(CONFIG_SHA1) case TPM2_ALG_SHA1: sha1_starts(&ctx); sha1_update(&ctx, input, length); sha1_finish(&ctx, final); len = TPM2_SHA1_DIGEST_SIZE; break; +#endif +#if IS_ENABLED(CONFIG_SHA256) case TPM2_ALG_SHA256: sha256_starts(&ctx_256); sha256_update(&ctx_256, input, length); sha256_finish(&ctx_256, final); len = TPM2_SHA256_DIGEST_SIZE; break; +#endif +#if IS_ENABLED(CONFIG_SHA384) case TPM2_ALG_SHA384: sha384_starts(&ctx_512); sha384_update(&ctx_512, input, length); sha384_finish(&ctx_512, final); len = TPM2_SHA384_DIGEST_SIZE; break; +#endif +#if IS_ENABLED(CONFIG_SHA512) case TPM2_ALG_SHA512: sha512_starts(&ctx_512); sha512_update(&ctx_512, input, length); sha512_finish(&ctx_512, final); len = TPM2_SHA512_DIGEST_SIZE; break; +#endif default: printf("%s: unsupported algorithm %x\n", __func__, hash_algo_list[i].hash_alg); @@ -236,10 +250,18 @@ static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog) continue; switch (hash_algo_list[i].hash_alg) { +#if IS_ENABLED(CONFIG_SHA1) case TPM2_ALG_SHA1: +#endif +#if IS_ENABLED(CONFIG_SHA256) case TPM2_ALG_SHA256: +#endif +#if IS_ENABLED(CONFIG_SHA384) case TPM2_ALG_SHA384: +#endif +#if IS_ENABLED(CONFIG_SHA512) case TPM2_ALG_SHA512: +#endif count++; break; default: @@ -337,10 +359,18 @@ static int tcg2_replay_eventlog(struct tcg2_event_log *elog, algo = get_unaligned_le16(log + pos); pos += offsetof(struct tpmt_ha, digest); switch (algo) { +#if IS_ENABLED(CONFIG_SHA1) case TPM2_ALG_SHA1: +#endif +#if IS_ENABLED(CONFIG_SHA256) case TPM2_ALG_SHA256: +#endif +#if IS_ENABLED(CONFIG_SHA384) case TPM2_ALG_SHA384: +#endif +#if IS_ENABLED(CONFIG_SHA512) case TPM2_ALG_SHA512: +#endif len = tpm2_algorithm_to_len(algo); break; default: @@ -450,10 +480,18 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) return 0; switch (algo) { +#if IS_ENABLED(CONFIG_SHA1) case TPM2_ALG_SHA1: +#endif +#if IS_ENABLED(CONFIG_SHA256) case TPM2_ALG_SHA256: +#endif +#if IS_ENABLED(CONFIG_SHA384) case TPM2_ALG_SHA384: +#endif +#if IS_ENABLED(CONFIG_SHA512) case TPM2_ALG_SHA512: +#endif len = get_unaligned_le16(&event->digest_sizes[i].digest_size); if (tpm2_algorithm_to_len(algo) != len) return 0; -- 2.34.1 ST Restricted

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[PATCH v3 0/2] clk: add a stub clock driver
by Caleb Connolly 09 Sep '24

09 Sep '24

As U-Boot works to align itself with upstream devicetrees, there are some common issues we start to run into, that of hardware blocks which might be important for an OS like Linux, but which aren't useful in U-Boot. For example, the Resource Power Manager found on Qualcomm platforms includes clock controllers and power domains which are only useful for managing power consumption and enabling low power states. As this is not at all relevant for U-Boot, we can safely ignore these devices, but we don't have a good way to communicate that to U-Boot. As an initial step, implement a "stub" clock driver which can be bound to these devices so that drivers will work as expected. Add the necessary compatibles for the rpmcc and rpmh-clk controllers on older rpm (non-h) platforms and the sm8250/8550/8650 platforms. To: Tom Rini <trini(a)konsulko.com> To: Lukasz Majewski <lukma(a)denx.de> To: Sean Anderson <seanga2(a)gmail.com> To: Caleb Connolly <caleb.connolly(a)linaro.org> To: Neil Armstrong <neil.armstrong(a)linaro.org> To: Sumit Garg <sumit.garg(a)linaro.org> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> Cc: u-boot(a)lists.denx.de Cc: u-boot-qcom(a)groups.io Changes in v3: - Add 8250/855/8650 rpmh clk stubs - Link to v2: https://lore.kernel.org/r/20240527-b4-clk-stub-v2-0-29013855e343@linaro.org Changes in v2: - Take the other discussed approach of just implementing a stub driver. - Link to v1: https://lore.kernel.org/r/20240410-b4-stub-drivers-v1-0-6935bd2c07d1@linaro… --- Caleb Connolly (2): clk: add stub clock driver qcom_defconfig: enable stub clock configs/qcom_defconfig | 1 + drivers/clk/Kconfig | 7 ++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-stub.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 75 insertions(+) --- base-commit: d0f74bd417daf6492975ce346843ba0767caf51c // Caleb (they/them)

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[PATCH] net: ftgmac100: Modify desc. size to cache line
by Jacky Chou 09 Sep '24

09 Sep '24

The TX/RX descriptor size is 16 byte. When the cache line size is larger than 16 bytes, descriptors flushed to RAM will flush more than one descriptor. It is possible that it may mistakenly flush to other descriptor that has been updated by MAC in RAM. To avoid this issue, align the descriptors to cache line size. Only one desc will be flushed or invalidated at a time. Signed-off-by: Jacky Chou <jacky_chou(a)aspeedtech.com> --- drivers/net/ftgmac100.c | 13 ++++++++++++- drivers/net/ftgmac100.h | 5 +++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 256a519020..9fb8c12838 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -322,7 +322,7 @@ static int ftgmac100_start(struct udevice *dev) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct phy_device *phydev = priv->phydev; - unsigned int maccr; + unsigned int maccr, dblac, desc_size; ulong start, end; int ret; int i; @@ -367,6 +367,17 @@ static int ftgmac100_start(struct udevice *dev) /* receive ring */ writel((u32)priv->rxdes, &ftgmac100->rxr_badr); + /* Configure TX/RX decsriptor size + * This size is calculated based on cache line. + */ + desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT; + /* The descriptor size is at least 2 descriptor units. */ + if (desc_size < 2) + desc_size = 2; + dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12); + dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size); + writel(dblac, &ftgmac100->dblac); + /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index f7874ae68b..37c029aded 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -111,6 +111,7 @@ struct ftgmac100 { #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DESC_UNIT 8 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) #define FTGMAC100_DBLAC_IFG_INC BIT(23) @@ -183,7 +184,7 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) #define FTGMAC100_TXDES0_EDOTR BIT(15) @@ -209,7 +210,7 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) #define FTGMAC100_RXDES0_EDORR BIT(15) -- 2.25.1

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[PATCH] net: ftgmac100: Fixed NC-SI PHY device cannot get
by Jacky Chou 09 Sep '24

09 Sep '24

The NC-SI interface does not need the MDIO bus and the NC-SI PHY device cannot get from dm_eth_phy_connect. Therefore, use phy_connect directly here. Signed-off-by: Jacky Chou <jacky_chou(a)aspeedtech.com> --- drivers/net/ftgmac100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9b536fd5ab..256a519020 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -223,7 +223,7 @@ static int ftgmac100_phy_init(struct udevice *dev) struct phy_device *phydev; int ret; - if (IS_ENABLED(CONFIG_DM_MDIO)) + if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) phydev = dm_eth_phy_connect(dev); else phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); -- 2.25.1

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[PATCH] net: ftgmac100: Fixed the cache coherency issues of rx memory
by Jacky Chou 09 Sep '24

09 Sep '24

When executing TFTP, the ARP will be replied to after receiving the ARP. U-boot's ARP routine modifies the data in the receive packet in response to the ARP packet and then copies it into the transmit packet. At this point, the received packet cache is inconsistent. It is possible that the cache will perform a writeback action to affect the MAC receiving packets. Avoid the same problem that occurs in other networking protocols. In the free_pkt function, ensure cache and memory consistency. Signed-off-by: Jacky Chou <jacky_chou(a)aspeedtech.com> --- drivers/net/ftgmac100.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9b536fd5ab..56854dfab8 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -411,6 +411,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + /* + * Make sure there are no stale data in write-back over this area, which + * might get written into the memory while the ftgmac100 also writes + * into the same memory area. + */ + flush_dcache_range((ulong)net_rx_packets[priv->rx_index], + (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN); + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; flush_dcache_range(des_start, des_end); -- 2.34.1

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[PATCH v2 1/3] phy: Extend generic_setup_phy() with PHY mode and submode
by Marek Vasut 09 Sep '24

09 Sep '24

Extend generic_setup_phy() parameter list with PHY mode and submode and call generic_phy_set_mode() in generic_setup_phy(), so the generic PHY setup function can configure the PHY into correct mode before powering the PHY up. Update all call sites of generic_setup_phy() as well, all of which are USB host related, except for DM test which now behaves as a USB host test. Note that if the PHY driver does not implement the .set_mode callback, generic_phy_set_mode() call returns 0 and does not error out, so this should not break any existing systems. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Caleb Connolly <caleb.connolly(a)linaro.org> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> Cc: Jonas Karlman <jonas(a)kwiboo.se> Cc: Mathieu Othacehe <othacehe(a)gnu.org> Cc: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> Cc: Neil Armstrong <neil.armstrong(a)linaro.org> Cc: Nishanth Menon <nm(a)ti.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Sumit Garg <sumit.garg(a)linaro.org> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Xavier Drudis Ferran <xdrudis(a)tinet.cat> Cc: u-boot-qcom(a)groups.io Cc: u-boot(a)lists.denx.de --- V2: Add failpath to return errno from generic_phy_set_mode() --- drivers/phy/phy-uclass.c | 13 +++++++++++-- drivers/usb/host/ehci-generic.c | 2 +- drivers/usb/host/ehci-msm.c | 2 +- drivers/usb/host/ehci-mx6.c | 2 +- drivers/usb/host/ehci-pci.c | 2 +- drivers/usb/host/ohci-generic.c | 2 +- include/generic-phy.h | 5 ++++- test/dm/phy.c | 8 ++++---- 8 files changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index acdcda15b5b..777d952b041 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -508,7 +508,8 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) return ret; } -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode) { int ret; @@ -520,10 +521,18 @@ int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) if (ret) return ret; + ret = generic_phy_set_mode(phy, mode, submode); + if (ret) + goto phys_mode_err; + ret = generic_phy_power_on(phy); if (ret) - generic_phy_exit(phy); + goto phys_mode_err; + + return 0; +phys_mode_err: + generic_phy_exit(phy); return ret; } diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 23c3ed25554..1ae3619ce25 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -94,7 +94,7 @@ static int ehci_usb_probe(struct udevice *dev) if (err) goto reset_err; - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto regulator_err; diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index a081f71b187..b0c060b8173 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -56,7 +56,7 @@ static int ehci_usb_probe(struct udevice *dev) hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); - ret = generic_setup_phy(dev, &p->phy, 0); + ret = generic_setup_phy(dev, &p->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) return ret; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 31cd8a50f4a..a93fa5d5455 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -703,7 +703,7 @@ static int ehci_usb_probe(struct udevice *dev) usb_phy_enable(ehci, priv->phy_addr); #endif #else - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) goto err_regulator; #endif diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 572686580cd..8d05b14e898 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -30,7 +30,7 @@ static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, int ret; u32 cmd; - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) return ret; diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index f1325cd4953..cc44226f5e0 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -50,7 +50,7 @@ static int ohci_usb_probe(struct udevice *dev) goto reset_err; } - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto reset_err; diff --git a/include/generic-phy.h b/include/generic-phy.h index eaab7491660..47962023236 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -415,10 +415,13 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk); * @dev: The consumer device. * @phy: A pointer to the PHY port * @index: The index in the list of available PHYs + * @mode: PHY mode + * @submode: PHY submode * * Return: 0 if OK, or negative error code. */ -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index); +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode); /** * generic_shutdown_phy() - Power off and de-initialize phy. diff --git a/test/dm/phy.c b/test/dm/phy.c index d14117f6f7a..a90881b12ab 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -243,20 +243,20 @@ static int dm_test_phy_setup(struct unit_test_state *uts) "gen_phy_user", &parent)); /* normal */ - ut_assertok(generic_setup_phy(parent, &phy, 0)); + ut_assertok(generic_setup_phy(parent, &phy, 0, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); /* power_off fail with -EIO */ - ut_assertok(generic_setup_phy(parent, &phy, 1)); + ut_assertok(generic_setup_phy(parent, &phy, 1, PHY_MODE_USB_HOST, 0)); ut_asserteq(-EIO, generic_shutdown_phy(&phy)); /* power_on fail with -EIO */ - ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2)); + ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); /* generic_phy_get_by_index fail with -ENOENT */ ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3, &phy)); - ut_assertok(generic_setup_phy(parent, &phy, 3)); + ut_assertok(generic_setup_phy(parent, &phy, 3, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); return 0; -- 2.43.0

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[PATCH 1/3] riscv: qemu: Enable booting from NVMe
by Eva Kurchatova 09 Sep '24

09 Sep '24

>From da876ced5ff607a4f21e30ab26fb1a972af56570 Mon Sep 17 00:00:00 2001 From: LekKit <50500857+LekKit(a)users.noreply.github.com> Date: Wed, 17 Jul 2024 20:31:21 +0300 Subject: [PATCH 1/3] riscv: qemu: Enable booting from NVMe QEMU supports NVMe devices, but U-Boot only tries to boot from Virtio. This is problematic when explicitly using NVMe, so fix that. Additionally, RVVM virtual machine is almost fully compatible with QEMU, except it only implements NVMe drives instead of VirtIO. --- include/configs/qemu-riscv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 2f594bfc..cf4fcb90 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -22,6 +22,7 @@ "stderr=serial,vidconsole\0" #define BOOT_TARGET_DEVICES(func) \ + func(NVME, nvme, 0) \ func(VIRTIO, virtio, 0) \ func(VIRTIO, virtio, 1) \ func(SCSI, scsi, 0) \ -- 2.45.2

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[PATCH 1/1] riscv: define find_{first,next}_zero_bit in asm/bitops.h
by Maxim Kochetkov 09 Sep '24

09 Sep '24

These seem to be missing, and trying to build fastboot cmd without them is causing errors due to these being missing. Signed-off-by: Maxim Kochetkov <fido_max(a)inbox.ru> --- arch/riscv/include/asm/bitops.h | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 35f1368b83..2f2994c4dd 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -138,6 +138,43 @@ static inline unsigned long ffz(unsigned long word) return k; } +static inline int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG); + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= (BITS_PER_LONG - 1); + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG - 1)) { + tmp = *(p++); + if (~tmp) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore @@ -158,6 +195,9 @@ static inline unsigned long ffz(unsigned long word) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + #define test_and_set_bit __test_and_set_bit #define test_and_clear_bit __test_and_clear_bit -- 2.45.2

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[PATCH 1/1] board: fix compatible property Milk-V Mars CM
by Heinrich Schuchardt 09 Sep '24

09 Sep '24

For the Milk-V Mars CM (lite) we have only been copying sizeof(void *) bytes to the compatible property instead of the whole string list. Fixes: de3229599d4f ("board: add support for Milk-V Mars CM") Reported-by: E Shattow <lucent(a)gmail.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- board/starfive/visionfive2/spl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index b794b73b6bd..f55c6b5d34c 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -170,23 +170,32 @@ void spl_fdt_fixup_mars_cm(void *fdt) { const char *compat; const char *model; + int compat_size; spl_fdt_fixup_mars(fdt); if (!get_mmc_size_from_eeprom()) { int offset; + static const char + compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110"; model = "Milk-V Mars CM Lite"; - compat = "milkv,mars-cm-lite\0starfive,jh7110"; + compat = compat_cm_lite; + compat_size = sizeof(compat_cm_lite); offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest"); /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */ fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016); } else { + static const char + compat_cm[] = "milkv,mars-cm\0starfive,jh7110"; + model = "Milk-V Mars CM"; - compat = "milkv,mars-cm\0starfive,jh7110"; + compat = compat_cm; + compat_size = sizeof(compat_cm); } - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), + "compatible", compat, compat_size); fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model); } -- 2.45.2

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