July 2024 - U-Boot

[PATCH] ARM: imx: Enable cat and xxd commands on DH i.MX8M Plus DHCOM
by Marek Vasut 06 Jul '24

06 Jul '24

Enable 'cat' command to print file from filesystem to stdout. Enable 'xxd' command to hexdump file from filesystem to stdout. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de --- configs/imx8mp_dhcom_pdk2_defconfig | 2 ++ configs/imx8mp_dhcom_pdk3_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 7fde7ad769d..79b3e96c8e3 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -108,6 +108,8 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 7b3dae504f8..6c7ee7ba3fa 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -111,6 +111,8 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y -- 2.43.0

2 1

[PATCH v3] ARM: imx: verdin-imx8mm: Set CAN oscillator frequency based on model
by Marek Vasut 06 Jul '24

06 Jul '24

The older i.MX8M Mini Verdin SoMs may came with 20 MHz SPI CAN controller oscillator, the newer SoMs always use 40 MHz oscillator. Handle both by overriding the oscillator frequency just before booting the kernel. These are the known variants with 20 MHz oscillator: - 0055, V1.1A, V1.1B, V1.1C and V1.1D, use a 20MHz oscillator - 0059, V1.1A and V1.1B, use a 20MHz oscillator Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Francesco Dolcini <francesco.dolcini(a)toradex.com> Cc: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Cc: Martyn Welch <martyn.welch(a)collabora.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: u-boot(a)lists.denx.de --- V2: - Update the comment in conditional statement - Update ver_assembly check for 0055 rev.A/B/C/D V3: - Update code comment per upstream feedback --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 29 +++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 55c02653da6..59cc28f652f 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -125,6 +125,35 @@ int board_phys_sdram_size(phys_size_t *size) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { + const char *canoscpath = "/oscillator"; + int freq = 40000000; /* 40 MHz is used on most variants */ + int canoscoff, ret; + + canoscoff = fdt_path_offset(blob, canoscpath); + if (canoscoff < 0) /* No CAN oscillator found. */ + goto exit; + + /* + * The following "prodid" (PID4 in Toradex naming) use + * a 20MHz CAN oscillator: + * - 0055, V1.1A, V1.1B, V1.1C and V1.1D + * - 0059, V1.1A and V1.1B + */ + if ((tdx_hw_tag.ver_major == 1 && tdx_hw_tag.ver_minor == 1) && + ((tdx_hw_tag.prodid == VERDIN_IMX8MMQ_IT && + tdx_hw_tag.ver_assembly <= 1) || /* 0059 rev. A or B */ + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT && + tdx_hw_tag.ver_assembly <= 3))) { /* 0055 rev. A/B/C/D */ + freq = 20000000; + } + + ret = fdt_setprop_u32(blob, canoscoff, "clock-frequency", freq); + if (ret < 0) { + printf("Failed to set CAN oscillator clock-frequency, ret=%d\n", + ret); + } + +exit: return ft_common_board_setup(blob, bd); } #endif -- 2.43.0

3 2

[PATCH] configs: phycore-imx8mp_defconfig: Initialize caam
by Leonard Anderweit 06 Jul '24

06 Jul '24

Initialize the Cryptographic Accelerator and Assurance Module. Signed-off-by: Leonard Anderweit <l.anderweit(a)phytec.de> --- configs/phycore-imx8mp_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index e84d761aeb8c..74d381058190 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -33,6 +33,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y @@ -45,6 +46,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_CRYPTO is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y @@ -87,6 +89,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x42800000 CONFIG_FASTBOOT_BUF_SIZE=0x13000000 @@ -102,7 +105,6 @@ CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -152,3 +154,4 @@ CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_IMX_WATCHDOG=y +# CONFIG_SPL_SHA_HW_ACCEL is not set -- 2.25.1

2 1

[PATCH v2] msc_sm2s_imx8mp: Adjust the initrd_addr location
by Fabio Estevam 06 Jul '24

06 Jul '24

From: Fabio Estevam <festevam(a)denx.de> Booting an initramfs with the current initrd_addr address may lead to initramfs corruption and boot failure. Fix the initramfs problem by applying the following layout suggested by Tom Rini: loadaddr=0x40480000 --> Gets moved to 0x40600000 in run-time: Uncompressing Kernel Image Moving Image from 0x40480000 to 0x40600000, end=41e80000 fdt_addr_r= moved loadaddr + 128 MiB = 0x48600000 initrd_addr=fdt_addr_r + 512 KiB = 0x48680000 Signed-off-by: Fabio Estevam <festevam(a)denx.de> Tested-by: Stefano Babic <sbabic(a)denx.de> --- Changes since v2: - Apply Tom's suggested layout. - Added Stefano's Tested-by. include/configs/msc_sm2s_imx8mp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index 3c7d96cb3c0..d0c5da7b98d 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -36,10 +36,10 @@ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ - "fdt_addr_r=0x43000000\0" \ + "fdt_addr_r=0x48600000\0" \ "boot_fdt=try\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ + "initrd_addr=0x48680000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ -- 2.34.1

2 2

[PATCH 1/1] mmc: fsl_esdhc_imx: Fix error message
by Alexander Stein 06 Jul '24

06 Jul '24

Add missing newline character and also add the return code of regulator_set_value() to the output. Signed-off-by: Alexander Stein <alexander.stein(a)ew.tq-group.com> --- drivers/mmc/fsl_esdhc_imx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index a9b8d7dd67f..03de7dcd505 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -766,7 +766,7 @@ static int esdhc_set_voltage(struct mmc *mmc) ret = regulator_set_value(priv->vqmmc_dev, 3300000); if (ret) { - printf("Setting to 3.3V error"); + printf("Setting to 3.3V error: %d\n", ret); return -EIO; } mdelay(5); @@ -784,7 +784,7 @@ static int esdhc_set_voltage(struct mmc *mmc) ret = regulator_set_value(priv->vqmmc_dev, 1800000); if (ret) { - printf("Setting to 1.8V error"); + printf("Setting to 1.8V error: %d\n", ret); return -EIO; } } -- 2.34.1

2 1

[PATCH] ARM: dts: imx8mp-beacon-kit-u-boot: Drop EQoS clock work-around
by Adam Ford 06 Jul '24

06 Jul '24

Since commit ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock"), the clocks for the DWMAC driver can be configured, and removing them breaks operation. Fixes: ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock") Suggested-by: Tim Harvey <tharvey(a)gateworks.com> Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi index ed183f83a7..380146596c 100644 --- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -32,12 +32,6 @@ bootph-pre-ram; }; -&eqos { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; -}; - &ethphy0 { reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>; -- 2.43.0

3 2

[PATCH 0/5] finish using .dtso for overlay source files
by Rasmus Villemoes 06 Jul '24

06 Jul '24

This is a followup to the patches that landed in 2024.01 and nearly made sure that source files for producing .dtbo files use the .dtso extension. In the same release, a few new .dts files snuck in, and there was also some test code involving .dtbo -> .dtbo.S -> .dtbo.o I didn't really know how to handle at the time. This should finish the job, bring us in sync with linux (at least in this respect), and drop the .dts -> .dtbo build rule. Patch 3 depends on 2, and patch 5 depends on the rest. Rasmus Villemoes (5): arm64: dts: imx8mp: rename DHCOM SoM overlays to .dtso kbuild: Allow DTB overlays to built into .dtbo.S files test: overlay: rename overlay source files to .dtso test/py: efi_capsule: rename device tree overlay source to .dtso kbuild: Disallow DTB overlays to built from .dts named source files ...> imx8mp-dhcom-pdk-overlay-eth2xfast.dtso} | 0 ... => imx8mp-dhcom-pdk3-overlay-rev100.dtso} | 0 ...> imx8mp-dhcom-som-overlay-eth1xfast.dtso} | 0 ...s => imx8mp-dhcom-som-overlay-rev100.dtso} | 0 scripts/Makefile.lib | 23 +++++++++++++++---- test/overlay/Makefile | 4 ++-- test/overlay/cmd_ut_overlay.c | 8 +++---- ...cked.dts => test-fdt-overlay-stacked.dtso} | 0 ...-fdt-overlay.dts => test-fdt-overlay.dtso} | 0 test/py/tests/test_efi_capsule/conftest.py | 6 ++--- .../{version.dts => version.dtso} | 0 11 files changed, 28 insertions(+), 13 deletions(-) rename arch/arm/dts/{imx8mp-dhcom-pdk-overlay-eth2xfast.dts => imx8mp-dhcom-pdk-overlay-eth2xfast.dtso} (100%) rename arch/arm/dts/{imx8mp-dhcom-pdk3-overlay-rev100.dts => imx8mp-dhcom-pdk3-overlay-rev100.dtso} (100%) rename arch/arm/dts/{imx8mp-dhcom-som-overlay-eth1xfast.dts => imx8mp-dhcom-som-overlay-eth1xfast.dtso} (100%) rename arch/arm/dts/{imx8mp-dhcom-som-overlay-rev100.dts => imx8mp-dhcom-som-overlay-rev100.dtso} (100%) rename test/overlay/{test-fdt-overlay-stacked.dts => test-fdt-overlay-stacked.dtso} (100%) rename test/overlay/{test-fdt-overlay.dts => test-fdt-overlay.dtso} (100%) rename test/py/tests/test_efi_capsule/{version.dts => version.dtso} (100%) -- 2.45.2

2 7

[PATCH] watchdog: mpc8xxx: Fix timer value
by Christophe Leroy 06 Jul '24

06 Jul '24

Timer value is a 16 bits calculated from the wanted timeout and the system clock. On powerpc/8xx, a timeout of 2s gives a value which is over U16_MAX so U16_MAX shall be used. But the calculation is casted to u16 so at the end the result is 63770 instead of 128906. So the timer gets loaded with 63770 instead of 65535. It is not a big difference in that case, but lets make the code correct and cast to u32 instead of u16. Fixes: 26e8ebcd7cb7 ("watchdog: mpc8xxx: Make it generic") Signed-off-by: Christophe Leroy <christophe.leroy(a)csgroup.eu> --- drivers/watchdog/mpc8xxx_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index f28636ca90..67e687a364 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -44,7 +44,7 @@ static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); const char *mode = env_get("watchdog_mode"); ulong prescaler = dev_get_driver_data(dev); - u16 swtc = min_t(u16, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX); + u16 swtc = min_t(u32, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX); u32 val; mpc8xxx_wdt_reset(dev); -- 2.44.0

2 1

[PATCH] pci_ids: fix i225 unprogrammed value
by Marjolaine Amate 06 Jul '24

06 Jul '24

This patch fixes the I225 hardware default value at 0x15FD meaning empty flash image or the NVM configuration loading failed Signed-off-by: Marjolaine Amate <marjolaine.amate(a)odyssee-systemes.fr> --- include/pci_ids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pci_ids.h b/include/pci_ids.h index f1886c3a75..b2136d3e9d 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2710,7 +2710,7 @@ #define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539 #define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b #define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c -#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15dF +#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15fd #define PCI_DEVICE_ID_INTEL_I225_IT 0x0d9f #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 -- 2.43.0

2 1

[PATCH] e1000: add support for i226
by Marjolaine Amate 06 Jul '24

06 Jul '24

This patch adds support for Intel Foxville I226 devices LM,V,I,K in e1000 driver. Signed-off-by: Marjolaine Amate <marjolaine.amate(a)odyssee-systemes.fr> --- drivers/net/e1000.c | 18 ++++++++++++++++++ drivers/net/e1000.h | 2 ++ include/pci_ids.h | 7 +++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 4e7ba66677..f9803b92b0 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -108,6 +108,12 @@ static struct pci_device_id e1000_supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_K) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LMVP) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_V) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_IT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, @@ -1569,6 +1575,12 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_ICH8_IGP_M: hw->mac_type = e1000_ich8lan; break; + case PCI_DEVICE_ID_INTEL_I226_K: + case PCI_DEVICE_ID_INTEL_I226_LMVP: + case PCI_DEVICE_ID_INTEL_I226_LM: + case PCI_DEVICE_ID_INTEL_I226_V: + case PCI_DEVICE_ID_INTEL_I226_IT: + case PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I210_COPPER: @@ -4843,6 +4855,8 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->phy_type = e1000_phy_igb; break; case I225_I_PHY_ID: + case I226_LM_PHY_ID: + case I226_I_PHY_ID: hw->phy_type = e1000_phy_igc; break; /* Fall Through */ @@ -4954,6 +4968,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) match = true; if (hw->phy_id == I225_I_PHY_ID) match = true; + if (hw->phy_id == I226_LM_PHY_ID) + match = true; + if (hw->phy_id == I226_I_PHY_ID) + match = true; break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index e1311126a3..aa649328f5 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -2421,7 +2421,9 @@ struct e1000_hw { #define BME1000_E_PHY_ID 0x01410CB0 #define I210_I_PHY_ID 0x01410C00 +#define I226_LM_PHY_ID 0x67C9DC10 #define I225_I_PHY_ID 0x67C9DCC0 +#define I226_I_PHY_ID 0x67C9DCD0 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF diff --git a/include/pci_ids.h b/include/pci_ids.h index f1886c3a75..834ec926b5 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2701,6 +2701,11 @@ #define PCI_DEVICE_ID_INTEL_82441 0x1237 #define PCI_DEVICE_ID_INTEL_82380FB 0x124b #define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_I226_LM 0x125b +#define PCI_DEVICE_ID_INTEL_I226_V 0x125c +#define PCI_DEVICE_ID_INTEL_I226_IT 0x125d +#define PCI_DEVICE_ID_INTEL_I221_V 0x125e +#define PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED 0x125f #define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED 0x1531 #define PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED 0x1532 #define PCI_DEVICE_ID_INTEL_I210_COPPER 0x1533 @@ -2930,6 +2935,7 @@ #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2 0x2db1 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2 0x2db2 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2 0x2db3 +#define PCI_DEVICE_ID_INTEL_I226_K 0x3102 #define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 #define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429 #define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a @@ -3001,6 +3007,7 @@ #define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 #define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f +#define PCI_DEVICE_ID_INTEL_I226_LMVP 0x5503 #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 #define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 -- 2.43.0

2 1