June 2024 - U-Boot

[PATCH] lds: align u-boot-nodtb with 8 bytes boundary
by Eugen Hristev 29 Jan '25

29 Jan '25

Newer DTC require that the DTB start address is aligned at 8 bytes. In the u-boot.bin case, the u-boot-nodtb.bin is concatenated with the DTB, but there is no alignment/padding to the next 8byte aligned address. This causes the board to fail booting, because the FDT will claim that the DTB inside u-boot.bin is not a valid DTB, it will fail with -FDT_ERR_ALIGNMENT. To solve this, have the u-boot binary `_end` aligned with 8 bytes. The objcopy in the Makefile will create the u-boot-nodtb.bin and it has to be truncated to 8 bytes to correspond to the u-boot.map file which will have the `_end` aligned to 8 bytes. The lds files which use devicetrees have been changed to align the `_end` tag with 8 bytes. This patch is also a prerequisite to have the possibility to update the dtc inside u-boot to newer versions (1.6.1+) Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- Hi, I could not test all affected boards, it's an impossible task. I tried this on at91 boards which I have, and ran the CI on denx. I cannot guarantee that no other boards are affected, so this patch is a bit of an RFC. If the u-boot-nodtb.bin does not have the size equal with the corresponding one in u-boot.map, the binary_size_check will fail at build time with something like this: u-boot.map shows a binary size of 502684 but u-boot-nodtb.bin shows 502688 Thanks, Eugen Makefile | 2 ++ arch/arm/cpu/armv8/u-boot.lds | 4 ++-- arch/arm/cpu/u-boot-spl.lds | 1 + arch/arm/cpu/u-boot.lds | 1 + arch/arm/lib/elf_arm_efi.lds | 5 +++++ arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 +- arch/arm/mach-at91/armv7/u-boot-spl.lds | 2 +- arch/arm/mach-zynq/u-boot-spl.lds | 2 +- arch/mips/cpu/u-boot.lds | 2 +- arch/sandbox/cpu/u-boot.lds | 6 ++++++ arch/sh/cpu/u-boot.lds | 2 ++ board/ti/am335x/u-boot.lds | 1 + tools/binman/test/u_boot_binman_embed.lds | 2 +- 13 files changed, 25 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 9d84f96481..b4d387bcce 100644 --- a/Makefile +++ b/Makefile @@ -1317,6 +1317,8 @@ endif u-boot-nodtb.bin: u-boot FORCE $(call if_changed,objcopy_uboot) +# Make sure the size is 8 byte-aligned. + @truncate -s %8 $@ $(BOARD_SIZE_CHECK) u-boot.ldr: u-boot diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 8fe4682dd2..e5fa4ef95c 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -145,10 +145,10 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; - . = ALIGN(8); + _end = .; + .bss_start : { KEEP(*(.__bss_start)); } diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index fb2189d50d..732ed42db1 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -55,6 +55,7 @@ SECTIONS .end : { + . = ALIGN(8); *(.__end) } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index f25f72b2e0..274e1a7d30 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -193,6 +193,7 @@ SECTIONS .end : { + . = ALIGN(8); *(.__end) } diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds index 767ebda635..f3867021d3 100644 --- a/arch/arm/lib/elf_arm_efi.lds +++ b/arch/arm/lib/elf_arm_efi.lds @@ -54,6 +54,11 @@ SECTIONS .rel.data : { *(.rel.data) *(.rel.data*) } _data_size = . - _etext; + .end : { + . = ALIGN(8); + *(.__end) + } + /DISCARD/ : { *(.rel.reloc) *(.eh_frame) diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 1a8bf94dee..d7e5d81ecc 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -31,7 +31,7 @@ SECTIONS . = ALIGN(4); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))) } > .sram - . = ALIGN(4); + . = ALIGN(8); __image_copy_end = .; .end : diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index 6ca725fc4c..2a0a1b4b86 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -38,7 +38,7 @@ SECTIONS . = ALIGN(4); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))) } > .sram - . = ALIGN(4); + . = ALIGN(8); __image_copy_end = .; .end : diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds index 8c18d3f91f..c0320dbe1e 100644 --- a/arch/arm/mach-zynq/u-boot-spl.lds +++ b/arch/arm/mach-zynq/u-boot-spl.lds @@ -41,7 +41,7 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } > .sram - . = ALIGN(4); + . = ALIGN(8); _image_binary_end = .; diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 9a4ebcd151..182e9bc6e5 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS . += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4; } - . = ALIGN(4); + . = ALIGN(8); _end = .; .bss __rel_start (OVERLAY) : { diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index ba8dee50c7..3fbca6d248 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -51,6 +51,12 @@ SECTIONS *(.dynsym) __dyn_sym_end = .; } + + .end : + { + . = ALIGN(8); + *(.__end) + } } INSERT BEFORE .data; diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index d360eea7eb..226f50b19c 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -74,6 +74,8 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } >ram + . = ALIGN(8); + PROVIDE (__init_end = .); PROVIDE (reloc_dst_end = .); PROVIDE (_end = .); diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index 087dee8bb2..deb9098a90 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -118,6 +118,7 @@ SECTIONS .end : { + . = ALIGN(8); *(.__end) } diff --git a/tools/binman/test/u_boot_binman_embed.lds b/tools/binman/test/u_boot_binman_embed.lds index e213fa8a84..93c0ae6aed 100644 --- a/tools/binman/test/u_boot_binman_embed.lds +++ b/tools/binman/test/u_boot_binman_embed.lds @@ -18,7 +18,7 @@ SECTIONS *(.text*) } - . = ALIGN(4); + . = ALIGN(8); .data : { dtb_embed_begin = .; KEEP(*(.mydtb)); -- 2.25.1

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[PATCH 00/16] EFI: ti: Enable EFI capsule updates
by Jonathan Humphreys 28 Jan '25

28 Jan '25

Enable on disk capsule updates, which includes defining the firmware components (tiboot3, spl, u-boot) and enabling processing of raw capsule updates. This is enabled for several TI SoC based platforms: AM64, AM62, AM62p, BeaglePlay, J7, and BeagleboneAI. This series also includes enabling seral flash DFU for AM62 and MMC DFU for beagleplay, and adding the sysreset controller node for AM62 to enable system reset. Jonathan Humphreys (16): board: Define GUIDs for firmware images board: am64x: Define capsule update firmware info configs: am64x: Enable EFI capsule update board: j721e: Define capsule update firmware info configs: j721e: Enable EFI capsule update board: beagleplay: Define capsule update firmware info configs: beagleplay: Enable DFU for MMC configs: beagleplay: Enable EFI capsule update board: am62px: Define capsule update firmware info configs: am62px: Enable EFI capsule update configs: am62x: Enable serial flash DFU arm: dts: k3-am625-sk-u-boot: Add sysreset-controller node board: am62x: Define capsule update firmware info configs: am62x: Enable EFI capsule update board: beagleboneai64: Define capsule update firmware info configs: beagleboneai64: Enable EFI capsule update arch/arm/dts/k3-am625-sk-u-boot.dtsi | 9 +++++ board/beagle/beagleboneai64/beagleboneai64.c | 33 +++++++++++++++++ board/beagle/beagleplay/beagleplay.c | 33 +++++++++++++++++ board/ti/am62px/evm.c | 32 +++++++++++++++++ board/ti/am62x/evm.c | 32 +++++++++++++++++ board/ti/am64x/evm.c | 33 +++++++++++++++++ board/ti/j721e/evm.c | 38 ++++++++++++++++++++ configs/am62px_evm_a53_defconfig | 2 ++ configs/am62x_beagleplay_a53_defconfig | 5 +++ configs/am62x_evm_a53_defconfig | 3 ++ configs/am64x_evm_a53_defconfig | 2 ++ configs/j721e_beagleboneai64_a72_defconfig | 2 ++ configs/j721e_evm_a72_defconfig | 2 ++ include/configs/ti_armv7_common.h | 17 +++++++++ 14 files changed, 243 insertions(+) -- 2.34.1

2 17

[PATCH v2] mmc: Remove alignment hole for cmdidx in struct mmc_cmd
by Jonas Karlman 27 Jan '25

27 Jan '25

The alignment hole caused by cmdidx in struct mmc_cmd cause strange issues together with the peephole2 optimization on Amlogic SoCs. Following was observed while working on SPL support for Amlogic SoCs. sd_get_capabilities() normally issue a CMD55 followed by a CMD51. However, on at least Amlogic S905 (Cortex-A53) and S905X3 (Cortex-A55), CMD55 was instead followed by CMD8 (and a few reties) in SPL. Code from the call site: cmd.cmdidx = SD_CMD_APP_SEND_SCR; // 51 ... data.blocksize = 8; ... err = mmc_send_cmd_retry(mmc, &cmd, &data, 3); Running the code with MMC_TRACE enabled shows: CMD_SEND:55 ARG 0x50480000 MMC_RSP_R1,5,6,7 0x00000920 CMD_SEND:8 ARG 0x00000000 RET -110 Removing the alignment hole by changing cmdidx from ushort to uint or building with -fno-peephole2 flag seem to resolve this issue. CMD_SEND:55 ARG 0x50480000 MMC_RSP_R1,5,6,7 0x00000920 CMD_SEND:51 ARG 0x00000000 MMC_RSP_R1,5,6,7 0x00000920 Same issue was observed building U-Boot with gcc 8 - 13. Remove this alignment hole by changing cmdidx from ushort to uint. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- Changes in v2: - Drop use of -fno-peephole2 flag Link to RFC: https://patchwork.ozlabs.org/patch/1841495/ --- include/mmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mmc.h b/include/mmc.h index 1022db3ffa7c..031ea0fb3545 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -413,7 +413,7 @@ struct mmc_cid { }; struct mmc_cmd { - ushort cmdidx; + uint cmdidx; uint resp_type; uint cmdarg; uint response[4]; -- 2.43.0

4 5

[PATCH] usb: dwc3-generic: Fix build errors when USB_DWC3_GADGET is disabled
by Jonas Karlman 07 Jan '25

07 Jan '25

Build fail with the following error when DM_USB_GADGET is enabled and USB_DWC3_GADGET is disabled: dwc3/dwc3-generic.o: in function `dm_usb_gadget_handle_interrupts': dwc3/dwc3-generic.c:201:(.text.dm_usb_gadget_handle_interrupts+0x10): undefined reference to `dwc3_gadget_uboot_handle_interrupt' Build also fail with the following error when USB_GADGET_DWC2_OTG + DM_USB_GADGET is enabled and USB_DWC3_GADGET is disabled: gadget/dwc2_udc_otg.o: in function `dm_usb_gadget_handle_interrupts': gadget/dwc2_udc_otg.c:947: multiple definition of `dm_usb_gadget_handle_interrupts'; dwc3/dwc3-generic.o:dwc3/dwc3-generic.c:197: first defined here Fix this by checking for USB_DWC3_GADGET in addition to DM_USB_GADGET. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/usb/dwc3/dwc3-generic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 6fb2de8a5ace..891d01957619 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -192,7 +192,7 @@ static int dwc3_generic_of_to_plat(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(DM_USB_GADGET) +#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) && CONFIG_IS_ENABLED(DM_USB_GADGET) int dm_usb_gadget_handle_interrupts(struct udevice *dev) { struct dwc3_generic_priv *priv = dev_get_priv(dev); @@ -435,7 +435,7 @@ static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) if (!dr_mode) dr_mode = usb_get_dr_mode(node); - if (CONFIG_IS_ENABLED(DM_USB_GADGET) && + if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) && CONFIG_IS_ENABLED(DM_USB_GADGET) && (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) { debug("%s: dr_mode: OTG or Peripheral\n", __func__); driver = "dwc3-generic-peripheral"; -- 2.43.0

4 16

[PATCH] usb: dwc3-of-simple: Remove Amlogic and Rockchip compatible
by Jonas Karlman 07 Jan '25

07 Jan '25

Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple driver now that all boards have changed to use the dwc3-generic driver. Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in use by any device tree in mainline linux or U-Boot. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/usb/host/dwc3-of-simple.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index f9df59d2e5d7..de1797d02ec0 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -90,8 +90,6 @@ static int dwc3_of_simple_remove(struct udevice *dev) } static const struct udevice_id dwc3_of_simple_ids[] = { - { .compatible = "amlogic,meson-gxl-dwc3" }, - { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "ti,dwc3" }, { } }; -- 2.43.0

4 3

[PATCH] Fix neighbor discovery ethernet address saving
by seanedmond＠linux.microsoft.com 01 Jan '25

01 Jan '25

From: Sean Edmond <seanedmond(a)microsoft.com> When a successful neighbor advertisement is received, the ethernet address should be saved for later use to avoid having to redo the neighbor discovery process. For example, with TFTP the address should get saved into "net_server_ethaddr". This is being done correctly with ARP for IPv4, but not for neighbor discovery with IPv6. Signed-off-by: Sean Edmond <seanedmond(a)microsoft.com> --- net/ndisc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ndisc.c b/net/ndisc.c index d1cec0601c8..505515f2d95 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -461,8 +461,8 @@ int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) ndisc_extract_enetaddr(ndisc, neigh_eth_addr); /* save address for later use */ - if (!net_nd_packet_mac) - net_nd_packet_mac = neigh_eth_addr; + if (net_nd_packet_mac) + memcpy(net_nd_packet_mac, neigh_eth_addr, 6); /* modify header, and transmit it */ memcpy(((struct ethernet_hdr *)net_nd_tx_packet)->et_dest, -- 2.42.0

4 4

[PATCH 00/10] Make bootph tags transistive to parents
by Simon Glass 19 Dec '24

19 Dec '24

The bootph binding[1] is defined such that if a tag is present in a subnode then it is supposed to apply to the parent node as well. This series aligned U-Boot with that binding. It also includes a few clean-ups. [1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/ schemas/bootph.yaml Simon Glass (10): x86: coral: Align bootph SPI-flash subnodes with parent fdtgrep: Tidy up a few type warnings and comments fdtgrep: Correct ordering of flags fdtgrep: Correct references to fdt_find_regions() fdtgrep: Tidy up comment for h_include() fdtgrep: Simplify code to inverting the match fdtgrep: Move property checking into a function sandbox: Correct SPL condition for building devicetree fdtgrep: Allow propagating properties up to supernodes Makefile: Use the fdtgrep -u flag arch/x86/dts/chromebook_coral.dts | 6 +- scripts/Makefile.lib | 2 +- scripts/Makefile.spl | 2 +- tools/fdtgrep.c | 123 ++++++++++++++++++++---------- 4 files changed, 87 insertions(+), 46 deletions(-) -- 2.43.0.472.g3155946c3a-goog

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[PATCH v3 0/3] mtd: nand: raw: Collected improvements
by Alexander Dahl 19 Dec '24

19 Dec '24

Hello everyone, while working on NAND flash support for a custom board based on the at91 SAM9X60 SoC I stumbled over some issues in the raw nand subsystem. Some trivial patches of previous iterations of this series were already applied. Patch 1 introduces a new subcommand for the new atmel nand controller driver. Patch 2 introduces a new subcommand for the nand command to override ONFI timing mode. Both are are for debugging purposes only and thus optional, and need to be enabled through menu. Both helped me a lot when investigating issues. Patch 3 is a fix carried over from at91bootstrap for faster at91 SoCs with certain raw NAND chips. Series is based on post v2024.04 master now. Greets Alex v3: - 4 patches removed, applied to master - other 2 patches from v2 unchanged, still under test - added new third patch with a fix for atmel nand timings (forgot to send that with v2) v2: Link: https://lore.kernel.org/u-boot/20240320090214.40465-1-ada@thorsis.com/ - rebased on recent next - collected tags - improved patch 4 after feedback from Mihai - added new patch 5 with another help text fix - added new patch 6 with a new debug command - reworded cover letter v1: Link: https://lore.kernel.org/u-boot/20240307091014.39796-1-ada@thorsis.com/ See per patch changes in patches for more detailed changes. Alexander Dahl (3): mtd: nand: raw: atmel: Introduce optional debug commands cmd: nand: Add new optional sub-command 'onfi' mtd: nand: raw: atmel: Fix pulse read timing for certain NAND flashes cmd/Kconfig | 10 + cmd/nand.c | 61 ++++ drivers/mtd/nand/raw/Kconfig | 9 + drivers/mtd/nand/raw/atmel/nand-controller.c | 308 ++++++++++++++++++- drivers/mtd/nand/raw/nand_base.c | 2 +- include/linux/mtd/rawnand.h | 1 + 6 files changed, 386 insertions(+), 5 deletions(-) base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91 -- 2.39.2

4 10

[PATCH 0/3] patman: A fix and some new tags
by Sean Anderson 14 Dec '24

14 Dec '24

This series has a fix along with a couple of convenient tags. Sean Anderson (3): patman: Fix tests if add_maintainers is set to False patman: Add Commit-cc as an alias for Patch-cc patman: Add a tag for when a patch gets added to a series tools/patman/func_test.py | 10 ++++++++-- tools/patman/patchstream.py | 7 +++++++ tools/patman/patman.rst | 15 ++++++++++++++- ...cast-for-sandbox-in-fdtdec_setup_mem_siz.patch | 2 ++ tools/patman/test/test01.txt | 2 ++ 5 files changed, 33 insertions(+), 3 deletions(-) -- 2.37.1

3 11

[PATCH] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
by Sam Protsenko 13 Dec '24

13 Dec '24

Sometimes clocks provided to a consumer might not have .set_rate operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag set. In that case it's usually possible to find a parent up the tree which is capable of setting the rate (div, pll, etc). Implement a simple lookup procedure for such cases, to traverse the clock tree until .set_rate capable parent is found, and use that parent to actually change the rate. The search will stop once the first .set_rate capable clock is found, which is usually enough to handle most cases. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- drivers/clk/clk-uclass.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc4841..755f05f34669 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -571,8 +571,20 @@ ulong clk_set_rate(struct clk *clk, ulong rate) return 0; ops = clk_dev_ops(clk->dev); - if (!ops->set_rate) - return -ENOSYS; + /* Try to find parents which can set rate */ + while (!ops->set_rate) { + struct clk *parent; + + if (!(clk->flags & CLK_SET_RATE_PARENT)) + return -ENOSYS; + + parent = clk_get_parent(clk); + if (IS_ERR_OR_NULL(parent) || !clk_valid(parent)) + return -ENODEV; + + clk = parent; + ops = clk_dev_ops(clk->dev); + } /* get private clock struct used for cache */ clk_get_priv(clk, &clkp); -- 2.39.2

5 16

[PATCH] nand: Add a watch command
by Miquel Raynal 02 Dec '24

02 Dec '24

This is a debug command to monitor the retention state of the data on the array. The command needs a duplication of the mtd_read_oob() function to actually return the maximum number of bitflips encountered while reading the page. We could write a specific implementation for the Sunxi driver but this is probably enough. nand watch <off> <size> - check an area for bitflips nand watch.part <part> - check a partition for bitflips nand watch.chip - check the whole device for bitflips The output may be a bit verbose and could look like: => nand watch.chip device 0 whole chip size adjusted to 0xff60000 (5 bad blocks) NAND watch for bitflips in area 0x0-0xff60000: Page 0 (0x00000000) -> error -74 Page 1 (0x00000800) -> error -74 Page 2 (0x00001000) -> error -74 Page 3 (0x00001800) -> error -74 Page 4 (0x00002000) -> error -74 Page 5 (0x00002800) -> error -74 Page 6 (0x00003000) -> error -74 Page 7 (0x00003800) -> error -74 Page 8 (0x00004000) -> error -74 Page 9 (0x00004800) -> error -74 Page 10 (0x00005000) -> error -74 Page 11 (0x00005800) -> error -74 Page 12 (0x00006000) -> error -74 Page 13 (0x00006800) -> error -74 Page 14 (0x00007000) -> error -74 Page 15 (0x00007800) -> error -74 Page 16 (0x00008000) -> error -74 Page 17 (0x00008800) -> error -74 Page 18 (0x00009000) -> error -74 Page 19 (0x00009800) -> error -74 Page 20 (0x0000a000) -> error -74 Page 21 (0x0000a800) -> error -74 Page 22 (0x0000b000) -> error -74 Page 23 (0x0000b800) -> error -74 Page 1110 (0x0022b000) -> up to 1 bf/chunk Page 1122 (0x00231000) -> up to 1 bf/chunk Page 1132 (0x00236000) -> up to 1 bf/chunk Page 1362 (0x002a9000) -> up to 1 bf/chunk Page 4990 (0x009bf000) -> up to 1 bf/chunk Page 5728 (0x00b30000) -> up to 1 bf/chunk Page 7116 (0x00de6000) -> up to 1 bf/chunk Page 7160 (0x00dfc000) -> up to 1 bf/chunk Page 7494 (0x00ea3000) -> up to 1 bf/chunk Page 10842 (0x0152d000) -> up to 1 bf/chunk Page 11614 (0x016af000) -> up to 1 bf/chunk Page 11970 (0x01761000) -> up to 1 bf/chunk Page 12536 (0x0187c000) -> up to 1 bf/chunk Page 12687 (0x018c7800) -> up to 1 bf/chunk Page 14298 (0x01bed000) -> up to 1 bf/chunk Page 18268 (0x023ae000) -> up to 1 bf/chunk Page 18760 (0x024a4000) -> up to 1 bf/chunk Page 21440 (0x029e0000) -> up to 1 bf/chunk Page 22336 (0x02ba0000) -> up to 1 bf/chunk Page 22592 (0x02c20000) -> up to 1 bf/chunk Page 23872 (0x02ea0000) -> up to 1 bf/chunk Page 27584 (0x035e0000) -> up to 1 bf/chunk Page 35008 (0x04460000) -> up to 1 bf/chunk Page 37184 (0x048a0000) -> up to 1 bf/chunk Page 41728 (0x05180000) -> up to 1 bf/chunk Page 42176 (0x05260000) -> up to 1 bf/chunk Page 43200 (0x05460000) -> up to 1 bf/chunk Page 43328 (0x054a0000) -> up to 1 bf/chunk Page 45376 (0x058a0000) -> up to 1 bf/chunk Page 47040 (0x05be0000) -> up to 1 bf/chunk Page 47552 (0x05ce0000) -> up to 1 bf/chunk Page 49344 (0x06060000) -> up to 1 bf/chunk Page 49856 (0x06160000) -> up to 1 bf/chunk Page 62784 (0x07aa0000) -> up to 1 bf/chunk Page 65153 (0x07f40800) -> up to 1 bf/chunk Page 65228 (0x07f66000) -> up to 1 bf/chunk Page 65382 (0x07fb3000) -> up to 1 bf/chunk Page 98624 (0x0c0a0000) -> up to 1 bf/chunk Page 101952 (0x0c720000) -> up to 1 bf/chunk Page 107584 (0x0d220000) -> up to 1 bf/chunk Page 118208 (0x0e6e0000) -> up to 1 bf/chunk Page 126656 (0x0f760000) -> up to 1 bf/chunk Page 127680 (0x0f960000) -> up to 1 bf/chunk Page 129920 (0x0fdc0000) -> up to 1 bf/chunk Maximum number of bitflips: 1 Pages with bitflips: 44/130752 It is also possible to reduce the output with the .quiet suffix in order to just show the summary. => nand watch.chip device 0 whole chip size adjusted to 0xff60000 (5 bad blocks) NAND watch for bitflips in area 0x0-0xff60000: Maximum number of bitflips: 1 Pages with bitflips: 44/130752 Signed-off-by: Miquel Raynal <miquel.raynal(a)bootlin.com> --- Hello, I recently came across a batch of NANDs with a lot of "natural" bitflips so in order to easily and objectively characterize how unstable these parts were, I wrote this little tool which was pretty handy to have in U-Boot. I believe it can be useful for others as well, so here is the patch. Cheers, Miquèl cmd/Kconfig | 5 ++ cmd/nand.c | 103 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/mtdcore.c | 22 +++++++++ include/linux/mtd/mtd.h | 1 + 4 files changed, 131 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 451baa3ecac..0524328d373 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1384,6 +1384,11 @@ config CMD_NAND_TORTURE help NAND torture support. +config CMD_NAND_WATCH + bool "nand watch" + help + NAND watch bitflip support. + endif # CMD_NAND config CMD_NVME diff --git a/cmd/nand.c b/cmd/nand.c index 71b8f964429..3bf67f5b65e 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -231,6 +231,54 @@ free_dat: return ret; } +#ifdef CONFIG_CMD_NAND_WATCH +static int nand_watch_bf(struct mtd_info *mtd, ulong off, ulong size, bool quiet) +{ + unsigned int max_bf = 0, pages_wbf = 0; + unsigned int first_page, pages, i; + struct mtd_oob_ops ops = {}; + u_char *buf; + int ret; + + buf = memalign(ARCH_DMA_MINALIGN, mtd->writesize); + if (!buf) { + puts("No memory for page buffer\n"); + return 1; + } + + first_page = off / mtd->writesize; + pages = size / mtd->writesize; + + ops.datbuf = buf; + ops.len = mtd->writesize; + for (i = first_page; i < first_page + pages; i++) { + ulong addr = mtd->writesize * i; + ret = mtd_read_oob_bf(mtd, addr, &ops); + if (ret < 0) { + if (quiet) + continue; + + printf("Page %7d (0x%08lx) -> error %d\n", + i, addr, ret); + } else if (ret) { + max_bf = max(max_bf, (unsigned int)ret); + pages_wbf++; + if (quiet) + continue; + printf("Page %7d (0x%08lx) -> up to %2d bf/chunk\n", + i, addr, ret); + } + } + + printf("Maximum number of bitflips: %u\n", max_bf); + printf("Pages with bitflips: %u/%u\n", pages_wbf, pages); + + free(buf); + + return 0; +} +#endif + /* ------------------------------------------------------------------------- */ static int set_dev(int dev) @@ -778,6 +826,55 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, return ret == 0 ? 0 : 1; } +#ifdef CONFIG_CMD_NAND_WATCH + if (strncmp(cmd, "watch", 5) == 0) { + int args = 2; + + if (cmd[5]) { + if (!strncmp(&cmd[5], ".part", 5)) { + args = 1; + } else if (!strncmp(&cmd[5], ".chip", 5)) { + args = 0; + } else { + goto usage; + } + } + + if (cmd[10]) + if (!strncmp(&cmd[10], ".quiet", 6)) + quiet = true; + + if (argc != 2 + args) + goto usage; + + ret = mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size, + &maxsize, MTD_DEV_TYPE_NAND, mtd->size); + if (ret) + return ret; + + /* size is unspecified */ + if (argc < 4) + adjust_size_for_badblocks(&size, off, dev); + + if ((off & (mtd->writesize - 1)) || + (size & (mtd->writesize - 1))) { + printf("Attempt to read non page-aligned data\n"); + return -EINVAL; + } + + ret = set_dev(dev); + if (ret) + return ret; + + mtd = get_nand_dev_by_index(dev); + + printf("\nNAND watch for bitflips in area 0x%llx-0x%llx:\n", + off, off + size); + + return nand_watch_bf(mtd, off, size, quiet); + } +#endif + #ifdef CONFIG_CMD_NAND_TORTURE if (strcmp(cmd, "torture") == 0) { loff_t endoff; @@ -943,6 +1040,12 @@ U_BOOT_LONGHELP(nand, "nand erase.chip [clean] - erase entire chip'\n" "nand bad - show bad blocks\n" "nand dump[.oob] off - dump page\n" +#ifdef CONFIG_CMD_NAND_WATCH + "nand watch <off> <size> - check an area for bitflips\n" + "nand watch.part <part> - check a partition for bitflips\n" + "nand watch.chip - check the whole device for bitflips\n" + "\t\t.quiet - Query only the summary, not the details\n" +#endif #ifdef CONFIG_CMD_NAND_TORTURE "nand torture off - torture one block at offset\n" "nand torture off [size] - torture blocks from off to off+size\n" diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index aa78d41a55e..2baf92a9056 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1126,6 +1126,28 @@ int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) } EXPORT_SYMBOL_GPL(mtd_read_oob); +/* This is a bare copy of mtd_read_oob returning the actual number of bitflips */ +int mtd_read_oob_bf(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) +{ + int ret_code; + ops->retlen = ops->oobretlen = 0; + if (!mtd->_read_oob) + return -EOPNOTSUPP; + /* + * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics + * similar to mtd->_read(), returning a non-negative integer + * representing max bitflips. In other cases, mtd->_read_oob() may + * return -EUCLEAN. In all cases, perform similar logic to mtd_read(). + */ + ret_code = mtd->_read_oob(mtd, from, ops); + if (unlikely(ret_code < 0)) + return ret_code; + if (mtd->ecc_strength == 0) + return 0; /* device lacks ecc */ + return ret_code; +} +EXPORT_SYMBOL_GPL(mtd_read_oob_bf); + int mtd_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 09f52698877..28afbb86ea9 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -413,6 +413,7 @@ int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); +int mtd_read_oob_bf(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); int mtd_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops); int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, -- 2.34.1

2 2

[PATCH 1/4] virtio: blk: introduce virtio-block erase support
by Dmitrii Merkurev 26 Nov '24

26 Nov '24

Co-developed-by: Cody Schuffelen <schuffelen(a)google.com> Signed-off-by: Cody Schuffelen <schuffelen(a)google.com> Signed-off-by: Dmitrii Merkurev <dimorinny(a)google.com> Cc: Tuomas Tynkkynen <tuomas.tynkkynen(a)iki.fi> Cc: Simon Glass <sjg(a)chromium.org> Cc: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> Cc: Ying-Chun Liu (PaulLiu) <paul.liu(a)linaro.org> --- drivers/virtio/virtio_blk.c | 91 +++++++++++++++++++++++++++++++------ drivers/virtio/virtio_blk.h | 47 +++++++++++++++++++ 2 files changed, 124 insertions(+), 14 deletions(-) diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 9581058286..225b65c4d1 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -19,30 +19,82 @@ struct virtio_blk_priv { struct virtqueue *vq; }; +static const u32 feature[] = { + VIRTIO_BLK_F_WRITE_ZEROES +}; + +static void virtio_blk_init_header_sg(struct udevice *dev, u64 sector, u32 type, + struct virtio_blk_outhdr *out_hdr, struct virtio_sg *sg) +{ + const bool sector_is_needed = type == VIRTIO_BLK_T_IN || + type == VIRTIO_BLK_T_OUT; + + out_hdr->type = cpu_to_virtio32(dev, type); + out_hdr->sector = cpu_to_virtio64(dev, sector_is_needed ? sector : 0); + + sg->addr = out_hdr; + sg->length = sizeof(*out_hdr); +} + +static void virtio_blk_init_write_zeroes_sg(struct udevice *dev, u64 sector, lbaint_t blkcnt, + struct virtio_blk_discard_write_zeroes *wz, + struct virtio_sg *sg) +{ + wz->sector = cpu_to_virtio64(dev, sector); + wz->num_sectors = cpu_to_virtio32(dev, blkcnt); + wz->flags = cpu_to_virtio32(dev, 0); + + sg->addr = wz; + sg->length = sizeof(*wz); +} + +static void virtio_blk_init_status_sg(u8 *status, struct virtio_sg *sg) +{ + sg->addr = status; + sg->length = sizeof(*status); +} + +static void virtio_blk_init_data_sg(void *buffer, lbaint_t blkcnt, struct virtio_sg *sg) +{ + sg->addr = buffer; + sg->length = blkcnt * 512; +} + static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, lbaint_t blkcnt, void *buffer, u32 type) { struct virtio_blk_priv *priv = dev_get_priv(dev); + struct virtio_blk_outhdr out_hdr; + struct virtio_blk_discard_write_zeroes wz_hdr; unsigned int num_out = 0, num_in = 0; + struct virtio_sg hdr_sg, wz_sg, data_sg, status_sg; struct virtio_sg *sgs[3]; u8 status; int ret; - struct virtio_blk_outhdr out_hdr = { - .type = cpu_to_virtio32(dev, type), - .sector = cpu_to_virtio64(dev, sector), - }; - struct virtio_sg hdr_sg = { &out_hdr, sizeof(out_hdr) }; - struct virtio_sg data_sg = { buffer, blkcnt * 512 }; - struct virtio_sg status_sg = { &status, sizeof(status) }; - + virtio_blk_init_header_sg(dev, sector, type, &out_hdr, &hdr_sg); sgs[num_out++] = &hdr_sg; - if (type & VIRTIO_BLK_T_OUT) - sgs[num_out++] = &data_sg; - else - sgs[num_out + num_in++] = &data_sg; - + switch (type) { + case VIRTIO_BLK_T_IN: + case VIRTIO_BLK_T_OUT: + virtio_blk_init_data_sg(buffer, blkcnt, &data_sg); + if (type & VIRTIO_BLK_T_OUT) + sgs[num_out++] = &data_sg; + else + sgs[num_out + num_in++] = &data_sg; + break; + + case VIRTIO_BLK_T_WRITE_ZEROES: + virtio_blk_init_write_zeroes_sg(dev, sector, blkcnt, &wz_hdr, &wz_sg); + sgs[num_out++] = &wz_sg; + break; + + default: + return -EINVAL; + } + + virtio_blk_init_status_sg(&status, &status_sg); sgs[num_out + num_in++] = &status_sg; log_debug("dev=%s, active=%d, priv=%p, priv->vq=%p\n", dev->name, device_active(dev), priv, priv->vq); @@ -76,6 +128,15 @@ static ulong virtio_blk_write(struct udevice *dev, lbaint_t start, VIRTIO_BLK_T_OUT); } +static ulong virtio_blk_erase(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt) +{ + if (!virtio_has_feature(dev, VIRTIO_BLK_F_WRITE_ZEROES)) + return -EOPNOTSUPP; + + return virtio_blk_do_req(dev, start, blkcnt, NULL, VIRTIO_BLK_T_WRITE_ZEROES); +} + static int virtio_blk_bind(struct udevice *dev) { struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent); @@ -105,7 +166,8 @@ static int virtio_blk_bind(struct udevice *dev) desc->bdev = dev; /* Indicate what driver features we support */ - virtio_driver_features_init(uc_priv, NULL, 0, NULL, 0); + virtio_driver_features_init(uc_priv, feature, ARRAY_SIZE(feature), + NULL, 0); return 0; } @@ -132,6 +194,7 @@ static int virtio_blk_probe(struct udevice *dev) static const struct blk_ops virtio_blk_ops = { .read = virtio_blk_read, .write = virtio_blk_write, + .erase = virtio_blk_erase, }; U_BOOT_DRIVER(virtio_blk) = { diff --git a/drivers/virtio/virtio_blk.h b/drivers/virtio/virtio_blk.h index 8d8e02fa2e..b37ba264df 100644 --- a/drivers/virtio/virtio_blk.h +++ b/drivers/virtio/virtio_blk.h @@ -17,6 +17,8 @@ #define VIRTIO_BLK_F_BLK_SIZE 6 /* Block size of disk is available */ #define VIRTIO_BLK_F_TOPOLOGY 10 /* Topology information is available */ #define VIRTIO_BLK_F_MQ 12 /* Support more than one vq */ +#define VIRTIO_BLK_F_DISCARD 13 /* Discard is supported */ +#define VIRTIO_BLK_F_WRITE_ZEROES 14 /* Write zeroes is supported */ /* Legacy feature bits */ #ifndef VIRTIO_BLK_NO_LEGACY @@ -65,6 +67,39 @@ struct __packed virtio_blk_config { /* number of vqs, only available when VIRTIO_BLK_F_MQ is set */ __u16 num_queues; + + /* the next 3 entries are guarded by VIRTIO_BLK_F_DISCARD */ + /* + * The maximum discard sectors (in 512-byte sectors) for + * one segment. + */ + __u32 max_discard_sectors; + /* + * The maximum number of discard segments in a + * discard command. + */ + __u32 max_discard_seg; + /* Discard commands must be aligned to this number of sectors. */ + __u32 discard_sector_alignment; + + /* the next 3 entries are guarded by VIRTIO_BLK_F_WRITE_ZEROES */ + /* + * The maximum number of write zeroes sectors (in 512-byte sectors) in + * one segment. + */ + __u32 max_write_zeroes_sectors; + /* + * The maximum number of segments in a write zeroes + * command. + */ + __u32 max_write_zeroes_seg; + /* + * Set if a VIRTIO_BLK_T_WRITE_ZEROES request may result in the + * deallocation of one or more of the sectors. + */ + __u8 write_zeroes_may_unmap; + + __u8 unused1[3]; }; /* @@ -93,6 +128,9 @@ struct __packed virtio_blk_config { /* Get device ID command */ #define VIRTIO_BLK_T_GET_ID 8 +/* Write zeroes command */ +#define VIRTIO_BLK_T_WRITE_ZEROES 13 + #ifndef VIRTIO_BLK_NO_LEGACY /* Barrier before this op */ #define VIRTIO_BLK_T_BARRIER 0x80000000 @@ -112,6 +150,15 @@ struct virtio_blk_outhdr { __virtio64 sector; }; +struct virtio_blk_discard_write_zeroes { + /* discard/write zeroes start sector */ + __virtio64 sector; + /* number of discard/write zeroes sectors */ + __virtio32 num_sectors; + /* flags for this range */ + __virtio32 flags; +}; + #ifndef VIRTIO_BLK_NO_LEGACY struct virtio_scsi_inhdr { __virtio32 errors; -- 2.44.0.278.ge034bb2e1d-goog

4 11

[PATCH] mtd: spi-nor: Add support for Macronix flash part
by Tejas Bhumkar 15 Nov '24

15 Nov '24

Added support for Macronix OSPI flash parts MX25UM51345G and MX66UM2G45G, with initial testing conducted on the Tenzing-se1 board using STR mode for basic erase, write, and readback operations. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index f86e7ff8e5..a08f105549 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -267,6 +267,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("mx25um51345g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_4B_OPCODES) }, + { INFO("mx66um2g45g", 0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_4B_OPCODES) }, { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, -- 2.37.6

4 3

[PATCH 1/3] binman: Add nxp_imx8mimage etype
by Marek Vasut 08 Nov '24

08 Nov '24

Add new binman etype derived from mkimage etype which generates configuration input file for mkimage -T imx8mimage, and runs the mkimage on input data. The mkimage -T imx8mimage is used to generate combined image with SPL and DDR PHY blobs which is bootable on i.MX8M. The configuration file generated here is equivalent of imx8mimage.cfg, which is the file passed to '$ mkimage -T imx8mimage -n imx8mimage.cfg ...' . The settings generated into the imx8mimage.cfg file are configured via supported binman DT properties, nxp,boot-from, nxp,loader-address, nxp,rom-version. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Adam Ford <aford173(a)gmail.com> Cc: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Cc: Andrejs Cainikovs <andrejs.cainikovs(a)toradex.com> Cc: Angus Ainslie <angus(a)akkea.ca> Cc: Emanuele Ghidoli <emanuele.ghidoli(a)toradex.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Francesco Dolcini <francesco.dolcini(a)toradex.com> Cc: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Cc: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefan Eichenberger <stefan.eichenberger(a)toradex.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: kernel(a)puri.sm Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de --- tools/binman/etype/nxp_imx8mimage.py | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 tools/binman/etype/nxp_imx8mimage.py diff --git a/tools/binman/etype/nxp_imx8mimage.py b/tools/binman/etype/nxp_imx8mimage.py new file mode 100644 index 00000000000..5a106e0a76e --- /dev/null +++ b/tools/binman/etype/nxp_imx8mimage.py @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2023-2024 Marek Vasut <marex(a)denx.de> +# Written with much help from Simon Glass <sjg(a)chromium.org> +# +# Entry-type module for generating the i.MX8M mkimage -T imx8mimage +# configuration file and invocation of mkimage -T imx8mimage on the +# configuration file and input data. +# + +from collections import OrderedDict + +from binman.entry import Entry +from binman.etype.mkimage import Entry_mkimage +from binman import elf +from dtoc import fdt_util +from u_boot_pylib import tools + +class Entry_nxp_imx8mimage(Entry_mkimage): + """NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker + + Properties / Entry arguments: + - nxp,boot-from - device to boot from (e.g. 'sd') + - nxp,loader-address - loader address (SPL text base) + - nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus) + """ + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.required_props = ['nxp,boot-from', 'nxp,rom-version', 'nxp,loader-address'] + + def ReadNode(self): + super().ReadNode() + self.boot_from = fdt_util.GetString(self._node, 'nxp,boot-from') + self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address') + self.rom_version = fdt_util.GetInt(self._node, 'nxp,rom-version') + self.ReadEntries() + + def BuildSectionData(self, required): + _, input_fname, uniq = self.collect_contents_to_file( + self._entries.values(), 'input') + # Generate mkimage configuration file similar to imx8mimage.cfg + # and pass it to mkimage to generate SPL image for us here. + cfg_fname = tools.get_output_filename('nxp.imx8mimage.cfg.%s' % uniq) + with open(cfg_fname, 'w') as outf: + print('ROM_VERSION v%d' % self.rom_version, file=outf) + print('BOOT_FROM %s' % self.boot_from, file=outf) + print('LOADER %s %#x' % (input_fname, self.loader_address), file=outf) + + output_fname = tools.get_output_filename(f'cfg-out.{uniq}') + args = ['-d', input_fname, '-n', cfg_fname, '-T', 'imx8mimage', + output_fname] + if self.mkimage.run_cmd(*args) is not None: + return tools.read_file(output_fname) + else: + # Bintool is missing; just use the input data as the output + self.record_missing_bintool(self.mkimage) + return data + + def SetImagePos(self, image_pos): + # Customized SoC specific SetImagePos which skips the mkimage etype + # implementation and removes the 0x48 offset introduced there. That + # offset is only used for uImage/fitImage, which is not the case in + # here. + upto = 0x00 + for entry in super().GetEntries().values(): + entry.SetOffsetSize(upto, None) + + # Give up if any entries lack a size + if entry.size is None: + return + upto += entry.size + + super(Entry_mkimage, self).SetImagePos(image_pos) -- 2.43.0

5 8

[PATCH] mtd: spi-nor: Clear Winbond SR3 WPS bit on boot
by Marek Vasut 24 Oct '24

24 Oct '24

Some Winbond SPI NORs have special SR3 register which is used among other things to control whether non-standard "Individual Block/Sector Write Protection" (WPS bit) locking scheme is activated. This non-standard locking scheme is not supported by either U-Boot or Linux SPI NOR stack so make sure it is disabled, otherwise the SPI NOR may appear locked for no obvious reason. This SR3 WPS appears e.g. on W25Q16FW which has the same ID as W25Q16DW, but the W25Q16DW does not implement the SR3 WPS bit. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Hai Pham <hai.pham.ud(a)renesas.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Johann Neuhauser <jneuhauser(a)dh-electronics.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> Cc: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> Cc: Vignesh R <vigneshr(a)ti.com> --- drivers/mtd/spi/spi-nor-core.c | 47 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 5 ++++ 2 files changed, 52 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9a1801ba93d..68dee57258d 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -544,6 +544,24 @@ static int read_cr(struct spi_nor *nor) } #endif +/** + * read_sr3() - Read status register 3 unique to newer Winbond flashes + * @nor: pointer to a 'struct spi_nor' + */ +static int read_sr3(struct spi_nor *nor) +{ + int ret; + u8 val; + + ret = nor->read_reg(nor, SPINOR_OP_RDSR3, &val, 1); + if (ret < 0) { + dev_dbg(nor->dev, "error %d reading SR3\n", ret); + return ret; + } + + return val; +} + /* * Write status register 1 byte * Returns negative if error occurred. @@ -554,6 +572,17 @@ static int write_sr(struct spi_nor *nor, u8 val) return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); } +/** + * write_sr3() - Write status register 3 unique to newer Winbond flashes + * @nor: pointer to a 'struct spi_nor' + * @val: value to be written into SR3 + */ +static int write_sr3(struct spi_nor *nor, u8 val) +{ + nor->cmd_buf[0] = val; + return nor->write_reg(nor, SPINOR_OP_WRSR3, nor->cmd_buf, 1); +} + /* * Set write enable latch with Write Enable command. * Returns negative if error occurred. @@ -3890,6 +3919,24 @@ static int spi_nor_init(struct spi_nor *nor) write_enable(nor); write_sr(nor, 0); spi_nor_wait_till_ready(nor); + + /* + * Some Winbond SPI NORs have special SR3 register which is + * used among other things to control whether non-standard + * "Individual Block/Sector Write Protection" (WPS bit) + * locking scheme is activated. This non-standard locking + * scheme is not supported by either U-Boot or Linux SPI + * NOR stack so make sure it is disabled, otherwise the + * SPI NOR may appear locked for no obvious reason. + */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) { + err = read_sr3(nor); + if (err > 0 && err & SR3_WPS) { + write_enable(nor); + write_sr3(nor, err & ~SR3_WPS); + write_disable(nor); + } + } } if (nor->quad_enable) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2861b73edbc..ceb32e3906f 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -45,6 +45,8 @@ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ +#define SPINOR_OP_RDSR3 0x15 /* Read status register 3 */ +#define SPINOR_OP_WRSR3 0x11 /* Write status register 3 */ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ @@ -185,6 +187,9 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* Status Register 3 bits. */ +#define SR3_WPS BIT(2) + /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ -- 2.43.0

4 20

[PATCH 1/2] video: Allow querying the font size
by Simon Glass 18 Oct '24

18 Oct '24

All the font size to be queried using the 'font size' command. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- cmd/font.c | 17 +++++++++-------- doc/usage/cmd/font.rst | 6 ++++-- test/cmd/font.c | 9 +++++++++ 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/cmd/font.c b/cmd/font.c index cb39c88063f..c7fe2a70a49 100644 --- a/cmd/font.c +++ b/cmd/font.c @@ -56,9 +56,6 @@ static int do_font_size(struct cmd_tbl *cmdtp, int flag, int argc, uint size; int ret; - if (argc != 2) - return CMD_RET_USAGE; - if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev)) return CMD_RET_FAILURE; ret = vidconsole_get_font_size(dev, &font_name, &size); @@ -67,12 +64,16 @@ static int do_font_size(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - size = dectoul(argv[1], NULL); + if (argc < 2) { + printf("%d\n", size); + } else { + size = dectoul(argv[1], NULL); - ret = vidconsole_select_font(dev, font_name, size); - if (ret) { - printf("Failed (error %d)\n", ret); - return CMD_RET_FAILURE; + ret = vidconsole_select_font(dev, font_name, size); + if (ret) { + printf("Failed (error %d)\n", ret); + return CMD_RET_FAILURE; + } } return 0; diff --git a/doc/usage/cmd/font.rst b/doc/usage/cmd/font.rst index 8ba149d7599..fea0df3f745 100644 --- a/doc/usage/cmd/font.rst +++ b/doc/usage/cmd/font.rst @@ -10,7 +10,7 @@ Synopis font list font select <name> [<size>] - font size <size> + font size [<size>] Description ----------- @@ -31,7 +31,7 @@ This selects a new font and optionally changes the size. font size ~~~~~~~~~ -This changes the font size only. +This changes the font size only. With no argument it shows the current size. Examples -------- @@ -41,6 +41,8 @@ Examples => font list nimbus_sans_l_regular cantoraone_regular + => font size + 30 => font size 40 => font select cantoraone_regular 20 => diff --git a/test/cmd/font.c b/test/cmd/font.c index 1fe05c1ead5..9c1eebf799e 100644 --- a/test/cmd/font.c +++ b/test/cmd/font.c @@ -60,10 +60,19 @@ static int font_test_base(struct unit_test_state *uts) ut_assertok(vidconsole_get_font_size(dev, &name, &size)); ut_asserteq_str("cantoraone_regular", name); ut_asserteq(40, size); + ut_assertok(ut_check_console_end(uts)); + + ut_assertok(run_command("font size", 0)); + ut_assert_nextline("40"); + ut_assertok(ut_check_console_end(uts)); ut_assertok(run_command("font size 30", 0)); ut_assertok(ut_check_console_end(uts)); + ut_assertok(run_command("font size", 0)); + ut_assert_nextline("30"); + ut_assertok(ut_check_console_end(uts)); + ut_assertok(vidconsole_get_font_size(dev, &name, &size)); ut_asserteq_str("cantoraone_regular", name); ut_asserteq(30, size); -- 2.34.1

5 7

[PATCH] x86: Make default_print_cpuinfo be a weak alias for print_cpuinfo
by Tom Rini 18 Oct '24

18 Oct '24

While a few SoCs have a unique print_cpuinfo function, a number of them just use default_print_cpuinfo. Make default_print_cpuinfo have a weak alias to provie print_cpuinfo. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- This will make re-using arch/x86/cpu/efi/ as a generic set of support code for U-Boot as EFI payload/app a little bit easier. Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/coreboot/coreboot.c | 5 ----- arch/x86/cpu/cpu.c | 2 ++ arch/x86/cpu/efi/app.c | 5 ----- arch/x86/cpu/efi/payload.c | 5 ----- arch/x86/cpu/slimbootloader/slimbootloader.c | 5 ----- arch/x86/cpu/tangier/tangier.c | 5 ----- 6 files changed, 2 insertions(+), 25 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 82fe4c71cd27..5c8d32ff6acd 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -44,11 +44,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} - static void board_final_init(void) { /* diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ce55efc454bf..5090f5cad746 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -165,6 +165,8 @@ char *cpu_get_name(char *name) return ptr; } +int print_cpuinfo(void) __attribute__((weak, alias("default_print_cpuinfo"))); + int default_print_cpuinfo(void) { printf("CPU: %s, vendor %s, device %xh\n", diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index f754489784a7..0eea9e2b0975 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -19,11 +19,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} - void board_final_init(void) { } diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 708bfbe7ee48..2bf4fefc19e6 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -144,11 +144,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} - /* Find any available tables and copy them to a safe place */ int reserve_arch(void) { diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c index ec5b87cfd63f..1f98db1f7c77 100644 --- a/arch/x86/cpu/slimbootloader/slimbootloader.c +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -55,8 +55,3 @@ int checkcpu(void) { return 0; } - -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c index 1e2f6cc8b700..35bbecbf8479 100644 --- a/arch/x86/cpu/tangier/tangier.c +++ b/arch/x86/cpu/tangier/tangier.c @@ -20,8 +20,3 @@ int checkcpu(void) { return 0; } - -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} -- 2.34.1

2 1

[PATCH v2] cmd: setexpr: fix no matching string in gsub return empty value
by Massimiliano Minella 16 Oct '24

16 Oct '24

From: Massimiliano Minella <massimiliano.minella(a)se.com> In gsub, when the destination string is empty, the string 't' is provided and the regular expression doesn't match, then the final result is an empty string. Example: => echo ${foo} => setenv foo => setexpr foo gsub e a bar => echo ${foo} => The variable ${foo} should contain "bar" and the lack of match shouldn't be considered an error. This patch fixes the erroneous behavior by removing the return statement and breaking out of the loop in case of lack of match. Also add a test for the no match case. Signed-off-by: Massimiliano Minella <massimiliano.minella(a)se.com> --- Changes in V2: - update documentation to describe the behavior cmd/setexpr.c | 9 ++++----- doc/usage/cmd/setexpr.rst | 1 + test/cmd/setexpr.c | 10 ++++++++++ 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/cmd/setexpr.c b/cmd/setexpr.c index 233471f6cb..ab76824a32 100644 --- a/cmd/setexpr.c +++ b/cmd/setexpr.c @@ -216,14 +216,12 @@ int setexpr_regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size, if (res == 0) { if (loop == 0) { debug("%s: No match\n", data); - return 1; } else { - break; + debug("## MATCH ## %s\n", data); } + break; } - debug("## MATCH ## %s\n", data); - if (!s) return 1; @@ -540,7 +538,8 @@ U_BOOT_CMD( " - For each substring matching the regular expression <r> in the\n" " string <t>, substitute the string <s>. The result is\n" " assigned to <name>. If <t> is not supplied, use the old\n" - " value of <name>\n" + " value of <name>. If no substring matching <r> is found in <t>,\n" + " assign <t> to <name>.\n" "setexpr name sub r s [t]\n" " - Just like gsub(), but replace only the first matching substring" #endif diff --git a/doc/usage/cmd/setexpr.rst b/doc/usage/cmd/setexpr.rst index d245a13ca8..593a0ea91e 100644 --- a/doc/usage/cmd/setexpr.rst +++ b/doc/usage/cmd/setexpr.rst @@ -39,6 +39,7 @@ setexpr name gsub <r> <s> [<t>] string <t>, substitute the string <s>. The result is assigned to <name>. If <t> is not supplied, use the old value of <name>. + If no substring matching <r> is found in <t>, assign <t> to <name>. setexpr name sub <r> <s> [<t>] Just like gsub(), but replace only the first matching substring diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c index 312593e1e3..ee329e94b8 100644 --- a/test/cmd/setexpr.c +++ b/test/cmd/setexpr.c @@ -179,6 +179,16 @@ static int setexpr_test_regex(struct unit_test_state *uts) val = env_get("mary"); ut_asserteq_str("this is a test", val); + /* No match */ + ut_assertok(run_command("setenv fred 'this is a test'", 0)); + ut_assertok(run_command("setenv mary ''", 0)); + ut_assertok(run_command("setexpr fred gsub us is \"${fred}\"", 0)); + ut_assertok(run_command("setexpr mary gsub us is \"${fred}\"", 0)); + val = env_get("fred"); + ut_asserteq_str("this is a test", val); + val = env_get("mary"); + ut_asserteq_str("this is a test", val); + unmap_sysmem(buf); return 0; -- 2.43.0

4 6

[PATCH] ufs: core: remove link_startup_again logic
by Neil Armstrong 14 Oct '24

14 Oct '24

The link_startup_again logic was added in Linux to handle device that were set in LinkDown state, which should not be the case since U-boot doesn't set LinkDown state are init, and Linux sets the device active in ufshcd_init() for the first link startup. While it worked to far, it breaks link startup for Qualcomm Controllers v5, let's just remove the logic. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- drivers/ufs/ufs.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index be64bf971f1..28c244b70e5 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -456,9 +456,7 @@ static int ufshcd_link_startup(struct ufs_hba *hba) { int ret; int retries = DME_LINKSTARTUP_RETRIES; - bool link_startup_again = true; -link_startup: do { ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); @@ -484,12 +482,6 @@ link_startup: /* failed to get the link up... retire */ goto out; - if (link_startup_again) { - link_startup_again = false; - retries = DME_LINKSTARTUP_RETRIES; - goto link_startup; - } - /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ ufshcd_init_pwr_info(hba); --- base-commit: 7e52d6ccfb76e2afc2d183b357abe2a2e2f948cf change-id: 20240528-topic-sm8x50-ufs-core-link-startup-again-bc2cf907c164 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

2 2

[PATCH] power: mp5416: Fix LDO SVAL for MP5416 PMIC
by Sidharth Prabukumar 10 Oct '24

10 Oct '24

The MP5416 PMIC's LDO set-value formula is incorrect. This patch fixes it by using the correct formula. Signed-off-by: Sidharth Prabukumar <sidharth.prabukumar(a)gmail.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- include/power/mp5416.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/power/mp5416.h b/include/power/mp5416.h index dc096fed3f..4326baaa42 100644 --- a/include/power/mp5416.h +++ b/include/power/mp5416.h @@ -32,7 +32,7 @@ enum { #define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000) #define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) #define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) -#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_LDO_SVAL(x) (((x) - 800000) / 25000) #define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500) #define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000) #define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500) -- 2.34.1

3 2

[PATCH] tools: docker: Drop the git user name and email configuration
by Bin Meng 10 Oct '24

10 Oct '24

Since commit b45ab9ca6621 ("CI: Update to QEMU 8.0.3"), the manual patch applying was removed, hence there is no need to do a git user name and email configuration. Signed-off-by: Bin Meng <bmeng(a)tinylab.org> --- tools/docker/Dockerfile | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index c4a2596b48..c12ed0fd9b 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -179,9 +179,6 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ cd /tmp/qemu && \ git checkout v8.0.3 && \ - # config user.name and user.email to make 'git am' happy - git config user.name u-boot && \ - git config user.email u-boot(a)denx.de && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu -- 2.34.1

3 3

[PATCH] doc: coreboot: Update stale graphics enabling instructions
by Bin Meng 10 Oct '24

10 Oct '24

From: Bin Meng <bmeng.cn(a)gmail.com> With latest coreboot (e.g.: v4.22.01), the instructions to enable graphics support has changed. Refresh the doc. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- doc/board/coreboot/coreboot.rst | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index f2c6452b5b..8408461617 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -32,10 +32,9 @@ of _x86boot_start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. -To enable video you must enable these options in coreboot: +To enable video you must enable CONFIG_GENERIC_LINEAR_FRAMEBUFFER in coreboot: - - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) - - Keep VESA framebuffer + - Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This @@ -184,9 +183,9 @@ boot as a coreboot payload, based on a known-good build of coreboot. To update the `coreboot.rom` file which is used: -#. Build coreboot with `CONFIG_LINEAR_FRAMEBUFFER=y`. If using `make menuconfig` - this is under - `Devices ->Display->Framebuffer mode->Linear "high resolution" framebuffer`. +#. Build coreboot with `CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y`. If using + `make menuconfig`, this is under + `Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer`. #. Compress the resulting `coreboot.rom`:: -- 2.34.1

2 1

[PATCH 0/4] spi: Various Kconfig fixes
by John Watts 10 Oct '24

10 Oct '24

I'm doing some SPI work so I tried to compile all the drivers on my sunxi board to try and avoid some regressions. This failed, so here are some fixes for this. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (4): spi: Kconfig: Add some required arch depends for drivers spi: mtk_spim: Remove completion.h include spi: ca_sflash: Add missing dm include spi: rockchip_sfc: Select BOUNCE_BUFFER drivers/spi/Kconfig | 17 +++++++++++++++++ drivers/spi/ca_sflash.c | 1 + drivers/spi/mtk_spim.c | 1 - 3 files changed, 18 insertions(+), 1 deletion(-) --- base-commit: 174ac987655c888017c82df1883c0c2ea0dc2495 change-id: 20240427-spikconfig-2417bbcf4c14 Best regards, -- John Watts <contact(a)jookia.org>

2 6

[PATCH 1/1] mtd: simplify CONFIG_DM_SPI_FLASH dependencies
by Heinrich Schuchardt 10 Oct '24

10 Oct '24

CONFIG_DM_SPI depends on CONFIG_DM. There is no need to list CONFIG_DM explicitly as dependency for CONFIG_DM_SPI_FLASH Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/mtd/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index bedc4e970e..63b0fd899f 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -2,7 +2,7 @@ menu "SPI Flash Support" config DM_SPI_FLASH bool "Enable Driver Model for SPI flash" - depends on DM && DM_SPI + depends on DM_SPI imply SPI_FLASH help Enable driver model for SPI flash. This SPI flash interface -- 2.43.0

2 1

[PATCH v2 0/4] dm: core: fix several debug messages and migrate debug() to dm_warn
by Quentin Schulz 03 Oct '24

03 Oct '24

Fix a few misleading or incorrect debug messages and prompt text for a Kconfig symbol. Migrate debug() messages to use dm_warn() instead so that we can print them without selecting DM_DEBUG which does too much (e.g. makes assert() reset U-boot if it fails). Tested on top of next branch but it applies without complaints on top of master as well, so up to you to which branch to merge it. Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> --- Changes in v2: - add missing dm/util.h header includes - Link to v1: https://lore.kernel.org/r/20240610-misc-20240610-v1-0-6914f1725dd4@cherry.de --- Quentin Schulz (4): dm: core: fix misleading debug message when matching compatible dm: core: fix signedness in debug messages dm: core: migrate debug() messages to use dm_warn dm: core: fix typo in SPL_DM_WARN prompt text drivers/core/Kconfig | 2 +- drivers/core/device.c | 2 +- drivers/core/fdtaddr.c | 7 +++-- drivers/core/lists.c | 7 ++--- drivers/core/of_access.c | 51 +++++++++++++++--------------- drivers/core/of_addr.c | 41 ++++++++++++------------ drivers/core/of_extra.c | 33 ++++++++++---------- drivers/core/ofnode.c | 81 ++++++++++++++++++++++++------------------------ drivers/core/regmap.c | 57 +++++++++++++++++----------------- drivers/core/root.c | 14 ++++----- drivers/core/uclass.c | 4 +-- 11 files changed, 152 insertions(+), 147 deletions(-) --- base-commit: f9886bc60f42d5bcfcfa4e474af7dc230400b6be change-id: 20240610-misc-20240610-f9dce050186b Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

6 15

[PATCH v2 00/14] Tools updates for Labgrid
by Simon Glass 27 Sep '24

27 Sep '24

This series includes patches to update buildman to support Labgrid better and some minor binman fixes and improvements. Changes in v2: - Move the binman assume-size feature into this series Simon Glass (14): binman: efi: Correct entry docs binman: Regenerate nxp docs binman: ti: Regenerate entry docs binman: Update the entrydocs header binman: Support an assumed size for missing binaries binman: Make Intel ME default to position 0x1000 x86: Set up some assumed sizes for binary blobs buildman: Make mrproper an argument to _reconfigure() buildman: Make mrproper an argument to _config_and_build() buildman: Make mrproper an argument to run_commit() buildman: Avoid rebuilding when --mrproper is used buildman: Add a flag to force mrproper on failure buildman: Retry the build for current source buildman: Add a way to limit the number of buildmans arch/x86/dts/u-boot.dtsi | 5 + tools/binman/binman.rst | 7 ++ tools/binman/entries.rst | 115 +++++++++++++----- tools/binman/entry.py | 3 +- tools/binman/etype/blob.py | 7 +- tools/binman/etype/efi_capsule.py | 40 +++---- tools/binman/etype/efi_empty_capsule.py | 22 ++-- tools/binman/etype/intel_descriptor.py | 2 +- tools/binman/etype/ti_secure.py | 45 ++++---- tools/binman/ftest.py | 28 +++++ tools/binman/test/326_assume_size.dts | 16 +++ tools/binman/test/327_assume_size_ok.dts | 16 +++ tools/buildman/builder.py | 18 +-- tools/buildman/builderthread.py | 44 ++++--- tools/buildman/buildman.rst | 8 +- tools/buildman/cmdline.py | 6 +- tools/buildman/control.py | 141 ++++++++++++++++++++++- tools/buildman/pyproject.toml | 6 +- tools/buildman/test.py | 121 +++++++++++++++++++ tools/u_boot_pylib/terminal.py | 7 +- 20 files changed, 545 insertions(+), 112 deletions(-) create mode 100644 tools/binman/test/326_assume_size.dts create mode 100644 tools/binman/test/327_assume_size_ok.dts -- 2.34.1

1 28

[PATCH] ARM: stm32: Fix TAMP_SMCR BKP..PROT fields on STM32MP15xx
by Marek Vasut 25 Sep '24

25 Sep '24

Update the TAMP_SMCR BKP..PROT fields to put first 10 registers into protection zone 1 and next 5 into zone 2. This fixes use of boot counter which is often in zone 3 and has to be updated from Linux, which runs in NS. Fixes: 73f7fc944cf6 ("ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx") Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index f096fe538d8..ca202bec8ee 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -148,8 +148,8 @@ static void security_init(void) */ clrsetbits_le32(TAMP_SMCR, TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, - FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | - FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x0A) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x0F)); /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); -- 2.43.0

3 5

[PATCH 1/4] power: regulator: Trigger probe of regulators which are always-on or boot-on
by Marek Vasut 25 Sep '24

25 Sep '24

In case a regulator DT node contains regulator-always-on or regulator-boot-on property, make sure the regulator gets correctly configured by U-Boot on start up. Unconditionally probe such regulator drivers. This is a preparatory patch for introduction of .regulator_post_probe() which would trigger the regulator configuration. Parsing of regulator-always-on and regulator-boot-on DT property has been moved to regulator_post_bind() as the information is required early, the rest of the DT parsing has been kept in regulator_pre_probe() to avoid slowing down the boot process. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Ben Wolsieffer <benwolsieffer(a)gmail.com> Cc: Caleb Connolly <caleb.connolly(a)linaro.org> Cc: Chris Morgan <macromorgan(a)hotmail.com> Cc: Dragan Simic <dsimic(a)manjaro.org> Cc: Eugen Hristev <eugen.hristev(a)collabora.com> Cc: Francesco Dolcini <francesco.dolcini(a)toradex.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Jonas Karlman <jonas(a)kwiboo.se> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Kostya Porotchkin <kostap(a)marvell.com> Cc: Matteo Lisi <matteo.lisi(a)engicam.com> Cc: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> Cc: Max Krummenacher <max.krummenacher(a)toradex.com> Cc: Neil Armstrong <neil.armstrong(a)linaro.org> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Quentin Schulz <quentin.schulz(a)cherry.de> Cc: Sam Day <me(a)samcday.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Sumit Garg <sumit.garg(a)linaro.org> Cc: Svyatoslav Ryhel <clamor95(a)gmail.com> Cc: Thierry Reding <treding(a)nvidia.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Volodymyr Babchuk <Volodymyr_Babchuk(a)epam.com> Cc: u-boot-amlogic(a)groups.io Cc: u-boot-qcom(a)groups.io Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- drivers/power/regulator/regulator-uclass.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 66fd531da04..ccc4ef33d83 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -433,6 +433,8 @@ static int regulator_post_bind(struct udevice *dev) const char *property = "regulator-name"; uc_pdata = dev_get_uclass_plat(dev); + uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); + uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); /* Regulator's mandatory constraint */ uc_pdata->name = dev_read_string(dev, property); @@ -444,13 +446,21 @@ static int regulator_post_bind(struct udevice *dev) return -EINVAL; } - if (regulator_name_is_unique(dev, uc_pdata->name)) - return 0; + if (!regulator_name_is_unique(dev, uc_pdata->name)) { + debug("'%s' of dev: '%s', has nonunique value: '%s\n", + property, dev->name, uc_pdata->name); + return -EINVAL; + } - debug("'%s' of dev: '%s', has nonunique value: '%s\n", - property, dev->name, uc_pdata->name); + /* + * In case the regulator has regulator-always-on or + * regulator-boot-on DT property, trigger probe() to + * configure its default state during startup. + */ + if (uc_pdata->always_on && uc_pdata->boot_on) + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); - return -EINVAL; + return 0; } static int regulator_pre_probe(struct udevice *dev) @@ -473,8 +483,6 @@ static int regulator_pre_probe(struct udevice *dev) -ENODATA); uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp", -ENODATA); - uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); - uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", 0); uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off"); -- 2.43.0

7 50

[PATCH 00/14] testb: Various tweaks and fixes for Labgrid
by Simon Glass 25 Sep '24

25 Sep '24

This series includes a number of mostly unrelated changes which are in service of running U-Boot on a lab using Labgrid. Changes in v2: - Add new patch to update u-boot.cfg with CFG_... options Simon Glass (14): trace: Update test to tolerate different trace-cmd version dm: core: Enhance comments on bind_drivers_pass() initcall: Correct use of relocation offset am33xx: Provide a function to set up the debug UART sunxi: Mark scp as optional google: Disable TPMv2 on most Chromebooks meson: Correct driver declaration for meson_axg_gpio test: Make bootstd init run only on sandbox log: Allow tests to pass with CONFIG_LOGF_FUNC_PAD set test: dm: Show failing driver name test: Decode exceptions only with sandbox test: Check help output Update u-boot.cfg to include CFG also smbios: Correct error handling when writing tables arch/arm/dts/sunxi-u-boot.dtsi | 1 + arch/arm/mach-omap2/am33xx/board.c | 18 +++++++++++++++--- configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/nyan-big_defconfig | 4 +--- configs/snow_defconfig | 1 + drivers/core/lists.c | 16 ++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 2 +- drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++-- drivers/pinctrl/meson/pinctrl-meson-axg.h | 2 +- drivers/pinctrl/meson/pinctrl-meson-g12a.c | 4 ++-- lib/initcall.c | 6 ++++-- lib/smbios.c | 10 ++++++++-- scripts/Makefile.autoconf | 2 +- test/py/tests/test_dm.py | 5 ++++- test/py/tests/test_help.py | 6 +++++- test/py/tests/test_log.py | 11 +++++++---- test/py/tests/test_trace.py | 6 +++--- test/py/tests/test_ut.py | 1 + test/py/u_boot_console_sandbox.py | 2 +- test/py/u_boot_spawn.py | 10 ++++++---- 23 files changed, 84 insertions(+), 31 deletions(-) -- 2.34.1

6 35

[PATCH] mtd: spi-nor: scale up timeout for full-chip erase
by Venkatesh Yadav Abbarapu 20 Sep '24

20 Sep '24

This patch fixes timeout issues seen on large NOR flash. For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7) opcode. Use a different timeout for full-chip erase than for other commands. [Ported from Linux kernel commit 09b6a377687b ("mtd: spi-nor: scale up timeout for full-chip erase") ] Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-core.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9a1801ba93..171c68787c 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -45,6 +45,12 @@ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) +/* + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up + * for larger flash + */ +#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) + #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) struct sfdp_parameter_header { @@ -832,6 +838,20 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) DEFAULT_READY_WAIT_JIFFIES); } +static int spi_nor_erase_chip_wait_till_ready(struct spi_nor *nor, unsigned long size) +{ + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + unsigned long timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(size / SZ_2M)); + return spi_nor_wait_till_ready_with_timeout(nor, timeout); +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -966,7 +986,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); bool addr_known = false; - u32 addr, len, rem; + u32 addr, len, rem, max_size; int ret, err; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -980,6 +1000,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr = instr->addr; len = instr->len; + max_size = instr->len; instr->state = MTD_ERASING; addr_known = true; @@ -1012,7 +1033,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr += ret; len -= ret; - ret = spi_nor_wait_till_ready(nor); + if (max_size == mtd->size && + !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + ret = spi_nor_erase_chip_wait_till_ready(nor, mtd->size); + } else { + ret = spi_nor_wait_till_ready(nor); + } + if (ret) goto erase_err; } -- 2.25.1

3 3

[PATCH v4 0/6] rpi5: initial support
by Ivan T. Ivanov 19 Sep '24

19 Sep '24

Hi, These patches are slight update for patches posted earlier here[1]. They are adding basic support for RPi5 and are based on v2 series from Dmitry Malkin[2]. What changed: * Initial memory map now includes whole first 1GB of DRAM. At runtime, the firmware will adjust this size depending on whether an HDMI cable is plugged in or not. If there is HDMI monitor connected it will reserve framebufer memory region and will add simple-framebuffer device into devicetree. * Dynamically calculate bits per pixel in video driver. This works on all prevous RPi's models that I have. * I am dropping PCIe patch for now. I made some progress on porting changes from vendor Linux tree to U-Boot. Unfortunatly testing it is little bit tricky. They are many devices behind PCIe, but more or less all of them requires missing either "reset-controller" or "clock-controller" or "pin-controller" drivers. I was able to probe "cdns,macb" device, but access to ethernet PHY over MDIO bus is stucking. Then I ported "raspberrypi,rp1-adc" driver from vendor Linux tree, but it requires missing clock. And on top of that machine that I used for developing this crashed and I lost my PCIe changes :-|. Anyway. These patches allows me to boot current openSUSE Tumbleweed without modification. I can see serial console log and boot process on HDMI connected monitor. I think these patches should be enough for start. Please consider for inclusion. Thanks, Ivan [1] https://lore.kernel.org/all/20231218210341.30073-1-iivanov@suse.de/ [2] https://lore.kernel.org/all/CAKRNjQ0dsWozGo4n8g58m4cCEk3n=qx1R+L24WBgpo-iP1… Dmitry Malkin (2): rpi5: add initial memory map for bcm2712 rpi5: Use devicetree as alternative way to read IO base addresses Ivan T. Ivanov (4): rpi5: Use devicetree to retrieve board revision bcm2835: Dynamically calculate bytes per pixel parameter mmc: bcmstb: Add support for bcm2712 SD controller configs: rpi_arm64: enable SDHCI BCMSTB driver arch/arm/mach-bcm283x/include/mach/base.h | 5 +- arch/arm/mach-bcm283x/include/mach/mbox.h | 3 +- arch/arm/mach-bcm283x/include/mach/sdhci.h | 3 +- arch/arm/mach-bcm283x/include/mach/timer.h | 3 +- arch/arm/mach-bcm283x/include/mach/wdog.h | 3 +- arch/arm/mach-bcm283x/init.c | 74 ++++++++- board/raspberrypi/rpi/rpi.c | 22 ++- configs/rpi_arm64_defconfig | 1 + drivers/mmc/bcmstb_sdhci.c | 173 ++++++++++++++++++++- drivers/video/bcm2835.c | 18 ++- 10 files changed, 282 insertions(+), 23 deletions(-) -- 2.35.3

5 18

[PATCH 1/2] mtd: spi-nor-core: allow overriding 4-byte OPCODE support
by Robert Marko 12 Sep '24

12 Sep '24

Currently, the only way to indicate 4-byte OPCODE support is by setting the SPI_NOR_4B_OPCODES feature flag for each JEDEC ID in spi_nor_ids[]. However, its becoming increasingly common practice for vendors to reuse the same JEDEC ID for new revisions of current parts. For example Winbond W25Q256FV does not fully support 4-byte OPCODE-s while newer W25Q256JV revision does fully support them but they share the same JEDEC ID thus currently its not possible to advertise support for 4-byte OPCODE-s on W25Q256JV. Luckily for us, there usually is a way to differentiate between parts with the same JEDEC ID by differences in SFDP tables, so in order to be able to apply a fixup after they are parsed lets add a feature flag that we can override. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/mtd/spi/spi-nor-core.c | 6 ++++-- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c..7615ba602f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3879,7 +3879,7 @@ static int spi_nor_init(struct spi_nor *nor) if (nor->addr_width == 4 && !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) && (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && - !(nor->info->flags & SPI_NOR_4B_OPCODES)) { + !(nor->flags & SNOR_F_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system * otherwise doesn't perform a reset command in the boot @@ -4118,6 +4118,8 @@ int spi_nor_scan(struct spi_nor *nor) nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; if (info->flags & USE_CLSR) nor->flags |= SNOR_F_USE_CLSR; + if (info->flags & SPI_NOR_4B_OPCODES) + nor->flags |= SNOR_F_4B_OPCODES; if (info->flags & SPI_NOR_NO_ERASE) mtd->flags |= MTD_NO_ERASE; @@ -4156,7 +4158,7 @@ int spi_nor_scan(struct spi_nor *nor) /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || - info->flags & SPI_NOR_4B_OPCODES) + nor->flags & SNOR_F_4B_OPCODES) spi_nor_set_4byte_opcodes(nor, info); #else /* Configure the BAR - discover bank cmds and read current bank */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1dbf3eadb..80e56cf308 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -294,6 +294,7 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET = BIT(6), SNOR_F_SOFT_RESET = BIT(7), SNOR_F_IO_MODE_EN_VOLATILE = BIT(8), + SNOR_F_4B_OPCODES = BIT(9), }; struct spi_nor; -- 2.44.0

3 5

[PATCH 1/7] m68k: Implement a default flush_dcache_all
by Tom Rini 10 Sep '24

10 Sep '24

Implement a weak default version of flush_dcache_all which is based on the ARM default, which is to flush the entire range via flush_dcache_range(...). Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Cc: Huan Wang <alison.wang(a)nxp.com> Cc: Angelo Dureghello <angelo(a)kernel-space.org> --- arch/m68k/lib/cache.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index de04124404cf..dab834c1cbd8 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -134,6 +134,15 @@ void dcache_invalid(void) #endif } +/* + * Default implementation: + * do a range flush for the entire range + */ +__weak void flush_dcache_all(void) +{ + flush_dcache_range(0, ~0); +} + __weak void invalidate_dcache_range(unsigned long start, unsigned long stop) { /* An empty stub, real implementation should be in platform code */ -- 2.34.1

4 15

[PATCH] net: ftgmac100: Modify desc. size to cache line
by Jacky Chou 09 Sep '24

09 Sep '24

The TX/RX descriptor size is 16 byte. When the cache line size is larger than 16 bytes, descriptors flushed to RAM will flush more than one descriptor. It is possible that it may mistakenly flush to other descriptor that has been updated by MAC in RAM. To avoid this issue, align the descriptors to cache line size. Only one desc will be flushed or invalidated at a time. Signed-off-by: Jacky Chou <jacky_chou(a)aspeedtech.com> --- drivers/net/ftgmac100.c | 13 ++++++++++++- drivers/net/ftgmac100.h | 5 +++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 256a519020..9fb8c12838 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -322,7 +322,7 @@ static int ftgmac100_start(struct udevice *dev) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct phy_device *phydev = priv->phydev; - unsigned int maccr; + unsigned int maccr, dblac, desc_size; ulong start, end; int ret; int i; @@ -367,6 +367,17 @@ static int ftgmac100_start(struct udevice *dev) /* receive ring */ writel((u32)priv->rxdes, &ftgmac100->rxr_badr); + /* Configure TX/RX decsriptor size + * This size is calculated based on cache line. + */ + desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT; + /* The descriptor size is at least 2 descriptor units. */ + if (desc_size < 2) + desc_size = 2; + dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12); + dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size); + writel(dblac, &ftgmac100->dblac); + /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index f7874ae68b..37c029aded 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -111,6 +111,7 @@ struct ftgmac100 { #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DESC_UNIT 8 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) #define FTGMAC100_DBLAC_IFG_INC BIT(23) @@ -183,7 +184,7 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) #define FTGMAC100_TXDES0_EDOTR BIT(15) @@ -209,7 +210,7 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) #define FTGMAC100_RXDES0_EDORR BIT(15) -- 2.25.1

2 1

[PATCH] net: ftgmac100: Fixed NC-SI PHY device cannot get
by Jacky Chou 09 Sep '24

09 Sep '24

The NC-SI interface does not need the MDIO bus and the NC-SI PHY device cannot get from dm_eth_phy_connect. Therefore, use phy_connect directly here. Signed-off-by: Jacky Chou <jacky_chou(a)aspeedtech.com> --- drivers/net/ftgmac100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9b536fd5ab..256a519020 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -223,7 +223,7 @@ static int ftgmac100_phy_init(struct udevice *dev) struct phy_device *phydev; int ret; - if (IS_ENABLED(CONFIG_DM_MDIO)) + if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) phydev = dm_eth_phy_connect(dev); else phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); -- 2.25.1

2 1

[PATCH] net: ftgmac100: Fixed the cache coherency issues of rx memory
by Jacky Chou 09 Sep '24

09 Sep '24

When executing TFTP, the ARP will be replied to after receiving the ARP. U-boot's ARP routine modifies the data in the receive packet in response to the ARP packet and then copies it into the transmit packet. At this point, the received packet cache is inconsistent. It is possible that the cache will perform a writeback action to affect the MAC receiving packets. Avoid the same problem that occurs in other networking protocols. In the free_pkt function, ensure cache and memory consistency. Signed-off-by: Jacky Chou <jacky_chou(a)aspeedtech.com> --- drivers/net/ftgmac100.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9b536fd5ab..56854dfab8 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -411,6 +411,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + /* + * Make sure there are no stale data in write-back over this area, which + * might get written into the memory while the ftgmac100 also writes + * into the same memory area. + */ + flush_dcache_range((ulong)net_rx_packets[priv->rx_index], + (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN); + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; flush_dcache_range(des_start, des_end); -- 2.34.1

2 1

[PATCH v2 1/3] phy: Extend generic_setup_phy() with PHY mode and submode
by Marek Vasut 09 Sep '24

09 Sep '24

Extend generic_setup_phy() parameter list with PHY mode and submode and call generic_phy_set_mode() in generic_setup_phy(), so the generic PHY setup function can configure the PHY into correct mode before powering the PHY up. Update all call sites of generic_setup_phy() as well, all of which are USB host related, except for DM test which now behaves as a USB host test. Note that if the PHY driver does not implement the .set_mode callback, generic_phy_set_mode() call returns 0 and does not error out, so this should not break any existing systems. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Caleb Connolly <caleb.connolly(a)linaro.org> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> Cc: Jonas Karlman <jonas(a)kwiboo.se> Cc: Mathieu Othacehe <othacehe(a)gnu.org> Cc: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> Cc: Neil Armstrong <neil.armstrong(a)linaro.org> Cc: Nishanth Menon <nm(a)ti.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Sumit Garg <sumit.garg(a)linaro.org> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Xavier Drudis Ferran <xdrudis(a)tinet.cat> Cc: u-boot-qcom(a)groups.io Cc: u-boot(a)lists.denx.de --- V2: Add failpath to return errno from generic_phy_set_mode() --- drivers/phy/phy-uclass.c | 13 +++++++++++-- drivers/usb/host/ehci-generic.c | 2 +- drivers/usb/host/ehci-msm.c | 2 +- drivers/usb/host/ehci-mx6.c | 2 +- drivers/usb/host/ehci-pci.c | 2 +- drivers/usb/host/ohci-generic.c | 2 +- include/generic-phy.h | 5 ++++- test/dm/phy.c | 8 ++++---- 8 files changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index acdcda15b5b..777d952b041 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -508,7 +508,8 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) return ret; } -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode) { int ret; @@ -520,10 +521,18 @@ int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) if (ret) return ret; + ret = generic_phy_set_mode(phy, mode, submode); + if (ret) + goto phys_mode_err; + ret = generic_phy_power_on(phy); if (ret) - generic_phy_exit(phy); + goto phys_mode_err; + + return 0; +phys_mode_err: + generic_phy_exit(phy); return ret; } diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 23c3ed25554..1ae3619ce25 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -94,7 +94,7 @@ static int ehci_usb_probe(struct udevice *dev) if (err) goto reset_err; - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto regulator_err; diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index a081f71b187..b0c060b8173 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -56,7 +56,7 @@ static int ehci_usb_probe(struct udevice *dev) hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); - ret = generic_setup_phy(dev, &p->phy, 0); + ret = generic_setup_phy(dev, &p->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) return ret; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 31cd8a50f4a..a93fa5d5455 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -703,7 +703,7 @@ static int ehci_usb_probe(struct udevice *dev) usb_phy_enable(ehci, priv->phy_addr); #endif #else - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) goto err_regulator; #endif diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 572686580cd..8d05b14e898 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -30,7 +30,7 @@ static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, int ret; u32 cmd; - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) return ret; diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index f1325cd4953..cc44226f5e0 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -50,7 +50,7 @@ static int ohci_usb_probe(struct udevice *dev) goto reset_err; } - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto reset_err; diff --git a/include/generic-phy.h b/include/generic-phy.h index eaab7491660..47962023236 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -415,10 +415,13 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk); * @dev: The consumer device. * @phy: A pointer to the PHY port * @index: The index in the list of available PHYs + * @mode: PHY mode + * @submode: PHY submode * * Return: 0 if OK, or negative error code. */ -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index); +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode); /** * generic_shutdown_phy() - Power off and de-initialize phy. diff --git a/test/dm/phy.c b/test/dm/phy.c index d14117f6f7a..a90881b12ab 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -243,20 +243,20 @@ static int dm_test_phy_setup(struct unit_test_state *uts) "gen_phy_user", &parent)); /* normal */ - ut_assertok(generic_setup_phy(parent, &phy, 0)); + ut_assertok(generic_setup_phy(parent, &phy, 0, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); /* power_off fail with -EIO */ - ut_assertok(generic_setup_phy(parent, &phy, 1)); + ut_assertok(generic_setup_phy(parent, &phy, 1, PHY_MODE_USB_HOST, 0)); ut_asserteq(-EIO, generic_shutdown_phy(&phy)); /* power_on fail with -EIO */ - ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2)); + ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); /* generic_phy_get_by_index fail with -ENOENT */ ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3, &phy)); - ut_assertok(generic_setup_phy(parent, &phy, 3)); + ut_assertok(generic_setup_phy(parent, &phy, 3, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); return 0; -- 2.43.0

3 7

[PATCH v2 0/4] clk: sophgo: milkv_duo: Add and enable clock controller driver
by Kongyang Liu 09 Sep '24

09 Sep '24

This series of patches introduces the clock controller driver for the Sophgo CV1800B SoC, updates the device tree sources to use the new clock controller, and enables the clock controller in the configuration for the Milk-V Duo board. Changes in v2: - Fix compilation error - Remove unused code Kongyang Liu (4): dt-bindings: clk: import header for clock controller of sophgo CV1800B clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC configs: milkv_duo: Enable clock controller riscv: dts: sophgo: Replace device clocks with real clocks. arch/riscv/dts/cv18xx.dtsi | 40 +- configs/milkv_duo_defconfig | 9 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 14 + drivers/clk/sophgo/Makefile | 6 + drivers/clk/sophgo/clk-common.h | 74 +++ drivers/clk/sophgo/clk-cv1800b.c | 754 ++++++++++++++++++++++ drivers/clk/sophgo/clk-cv1800b.h | 123 ++++ drivers/clk/sophgo/clk-ip.c | 594 +++++++++++++++++ drivers/clk/sophgo/clk-ip.h | 288 +++++++++ drivers/clk/sophgo/clk-pll.c | 275 ++++++++ drivers/clk/sophgo/clk-pll.h | 74 +++ include/dt-bindings/clock/sophgo,cv1800.h | 176 +++++ 14 files changed, 2401 insertions(+), 28 deletions(-) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-common.h create mode 100644 drivers/clk/sophgo/clk-cv1800b.c create mode 100644 drivers/clk/sophgo/clk-cv1800b.h create mode 100644 drivers/clk/sophgo/clk-ip.c create mode 100644 drivers/clk/sophgo/clk-ip.h create mode 100644 drivers/clk/sophgo/clk-pll.c create mode 100644 drivers/clk/sophgo/clk-pll.h create mode 100644 include/dt-bindings/clock/sophgo,cv1800.h -- 2.41.0

2 8

[PATCH 1/1] clk: sifive: avoid declaring static variables in includes
by Heinrich Schuchardt 09 Sep '24

09 Sep '24

The existing code is unnecessarily convoluted: Arrays __prci_init_clocks_fu[5|7]40 are initialized with data. In separate includes fu[5|7]40-prci.h the size of the arrays is provided as constants. By moving the structures prci_clk_fu[5|7]40 to the respective code modules we can directly use ARRAY_SIZE() to access the size of the data used for initialization. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/clk/sifive/fu540-prci.c | 7 ++++++- drivers/clk/sifive/fu540-prci.h | 22 ---------------------- drivers/clk/sifive/fu740-prci.c | 7 ++++++- drivers/clk/sifive/fu740-prci.h | 22 ---------------------- drivers/clk/sifive/sifive-prci.c | 3 +-- drivers/clk/sifive/sifive-prci.h | 4 ++++ 6 files changed, 17 insertions(+), 48 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.h delete mode 100644 drivers/clk/sifive/fu740-prci.h diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index ceb2c6fab0d..e55a26ab8fd 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { +static struct __prci_clock __prci_init_clocks_fu540[] = { [PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = { .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, }; + +const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h deleted file mode 100644 index 113301107da..00000000000 --- a/drivers/clk/sifive/fu540-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU540_PRCI_H -#define __SIFIVE_CLK_FU540_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU540 4 - -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; - -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - -#endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 5edc864e4bd..4274b215d2f 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { +static struct __prci_clock __prci_init_clocks_fu740[] = { [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .pwd = &__prci_pcieaux_data, } }; + +const struct prci_clk_desc prci_clk_fu740 = { + .clks = __prci_init_clocks_fu740, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), +}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h deleted file mode 100644 index b74f0789061..00000000000 --- a/drivers/clk/sifive/fu740-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU740_PRCI_H -#define __SIFIVE_CLK_FU740_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU740 9 - -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; - -static const struct prci_clk_desc prci_clk_fu740 = { - .clks = __prci_init_clocks_fu740, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), -}; - -#endif /* __SIFIVE_CLK_FU740_PRCI_H */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index c8fb6002907..603a176d06a 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -34,8 +34,7 @@ #include <linux/math64.h> #include <dt-bindings/clock/sifive-fu740-prci.h> -#include "fu540-prci.h" -#include "fu740-prci.h" +#include "sifive-prci.h" /* * Private functions diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 5ce33d61846..b391698081d 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); +/* Clock driver data */ +extern const struct prci_clk_desc prci_clk_fu540; +extern const struct prci_clk_desc prci_clk_fu740; + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ -- 2.43.0

3 2

[PATCH] video: Add parentheses around VNBYTES() macro
by Dan Carpenter 06 Sep '24

06 Sep '24

The VNBYTES() macro needs to have parentheses to prevent some (harmless) macro expansion bugs. The VNBYTES() macro is used like this: VID_TO_PIXEL(x) * VNBYTES(vid_priv->bpix) The * operation is done before the / operation. It still ends up with the same results, but it's not ideal. Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- include/video.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/video.h b/include/video.h index 9729fa348aa5..b364bf91825f 100644 --- a/include/video.h +++ b/include/video.h @@ -58,7 +58,7 @@ enum video_log2_bpp { * Convert enum video_log2_bpp to bytes and bits. Note we omit the outer * brackets to allow multiplication by fractional pixels. */ -#define VNBYTES(bpix) (1 << (bpix)) / 8 +#define VNBYTES(bpix) ((1 << (bpix)) / 8) #define VNBITS(bpix) (1 << (bpix)) -- 2.39.2

4 6

[PATCH v5] mmc: Poll CD in case cyclic framework is enabled
by Marek Vasut 06 Sep '24

06 Sep '24

In case the cyclic framework is enabled, poll the card detect of already initialized cards and deinitialize them in case they are removed. Since the card initialization is a longer process and card initialization is done on first access to an uninitialized card anyway, avoid initializing newly detected uninitialized cards in the cyclic callback. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> --- V2: Move the cyclic registration/unregistration into mmc init/deinit V3: Replace if (CONFIG_IS_ENABLED(CYCLIC)...) with #if as the former does not work with structure members V4: Stuff the code with CONFIG_IS_ENABLED() variants to avoid #ifdefs V5: Rebase on u-boot/next --- drivers/mmc/mmc.c | 32 ++++++++++++++++++++++++++++++++ include/mmc.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b18dc331f78..7cf64535b68 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3005,6 +3005,20 @@ static int mmc_complete_init(struct mmc *mmc) return err; } +static void __maybe_unused mmc_cyclic_cd_poll(void *ctx) +{ + struct mmc *m = ctx; + + if (!m->has_init) + return; + + if (mmc_getcd(m)) + return; + + mmc_deinit(m); + m->has_init = 0; +} + int mmc_init(struct mmc *mmc) { int err = 0; @@ -3027,6 +3041,19 @@ int mmc_init(struct mmc *mmc) if (err) pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic), (NULL))) { + /* Register cyclic function for card detect polling */ + CONFIG_IS_ENABLED(CYCLIC, + (mmc->cyclic = cyclic_register(mmc_cyclic_cd_poll, + 100 * 1000, + mmc->cfg->name, mmc))); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic), (NULL))) { + printf("Failed to register %s CD poll function\n", + mmc->cfg->name); + err = -EINVAL; + } + } + return err; } @@ -3034,6 +3061,11 @@ int mmc_deinit(struct mmc *mmc) { u32 caps_filtered; + if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic), (NULL))) { + cyclic_unregister(CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic), NULL)); + CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic = NULL)); + } + if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) diff --git a/include/mmc.h b/include/mmc.h index 7f1900363b9..7c98ace5346 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -14,6 +14,7 @@ #include <linux/sizes.h> #include <linux/compiler.h> #include <linux/dma-direction.h> +#include <cyclic.h> #include <part.h> struct bd_info; @@ -733,6 +734,8 @@ struct mmc { bool hs400_tuning:1; enum bus_mode user_speed_mode; /* input speed mode from user */ + + CONFIG_IS_ENABLED(CYCLIC, (struct cyclic_info *cyclic)); }; #if CONFIG_IS_ENABLED(DM_MMC) -- 2.43.0

3 2

[PATCH] power: regulator: tps6287x: Add driver for TPS6287x step down convertors
by Keerthy 06 Sep '24

06 Sep '24

Add driver for TPS6287x step down convertors Data sheet: https://www.ti.com/lit/ds/slvsgc5a/slvsgc5a.pdf Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- drivers/power/regulator/Kconfig | 18 ++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/tps6287x_regulator.c | 172 +++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 drivers/power/regulator/tps6287x_regulator.c diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 102ec7bc5f..db4b40c35e 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -375,6 +375,15 @@ config DM_REGULATOR_TPS80031 features for TPS80031/TPS80032 PMICs. The driver implements get/set api for: value and enable. +config DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 @@ -394,6 +403,15 @@ config DM_REGULATOR_ANATOP regulators. It is recommended that this option be enabled on i.MX6 platform. +config SPL_DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on SPL_DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" depends on SPL_DM_REGULATOR && PMIC_STPMIC1 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index f79932d833..6335e5566d 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c new file mode 100644 index 0000000000..6d18571919 --- /dev/null +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy <j-keerthy(a)ti.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <dm/device_compat.h> +#include <power/regulator.h> + +#define TPS6287X_REG_VSET 0x0 +#define TPS6287X_REG_CONTROL1 0x1 +#define TPS6287X_REG_CONTROL2 0x2 +#define TPS6287X_REG_CONTROL3 0x3 +#define TPS6287X_REG_STATUS 0x4 +#define TPS6287X_REG_VSET_VSET_MASK 0xff +#define TPS6287X_REG_CONTROL2_VRANGE_MASK 0xc + +struct tps6287x_regulator_config { + u32 vmin; + u32 vmax; +}; + +struct tps6287x_regulator_pdata { + u8 vsel_offset; + struct udevice *i2c; + struct tps6287x_regulator_config *config; +}; + +static struct tps6287x_regulator_config tps6287x_data = { + .vmin = 400000, + .vmax = 3350000, +}; + +static int tps6287x_regulator_set_value(struct udevice *dev, int uV) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + u8 regval, vset; + int ret; + + if (uV < pdata->config->vmin || uV > pdata->config->vmax) + return -EINVAL; + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, &regval, 1); + if (ret) { + dev_err(dev, "CTRL2 reg read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + vset = (uV - 400000) / 1250; + break; + case 1: + vset = (uV - 400000) / 2500; + break; + case 2: + vset = (uV - 400000) / 5000; + break; + case 3: + vset = (uV - 800000) / 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return dm_i2c_write(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); +} + +static int tps6287x_regulator_get_value(struct udevice *dev) +{ + u8 regval, vset; + int uV; + int ret; + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, &regval, 1); + if (ret) { + dev_err(dev, "i2c read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); + if (ret) { + dev_err(dev, "i2c VSET read failed: %d\n", ret); + return ret; + } + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + uV = 400000 + vset * 1250; + break; + case 1: + uV = 400000 + vset * 2500; + break; + case 2: + uV = 400000 + vset * 5000; + break; + case 3: + uV = 800000 + vset * 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return uV; +} + +static int tps6287x_regulator_probe(struct udevice *dev) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + int ret, slave_id; + + pdata->config = (void *)dev_get_driver_data(dev); + + slave_id = devfdt_get_addr_index(dev, 0); + + ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); + if (ret) { + dev_err(dev, "i2c dev get failed.\n"); + return ret; + } + + return 0; +} + +static const struct dm_regulator_ops tps6287x_regulator_ops = { + .get_value = tps6287x_regulator_get_value, + .set_value = tps6287x_regulator_set_value, +}; + +static const struct udevice_id tps6287x_regulator_ids[] = { + { .compatible = "ti,tps62873", .data = (ulong)&tps6287x_data }, + { }, +}; + +U_BOOT_DRIVER(tps6287x_regulator) = { + .name = "tps6287x_regulator", + .id = UCLASS_REGULATOR, + .ops = &tps6287x_regulator_ops, + .of_match = tps6287x_regulator_ids, + .plat_auto = sizeof(struct tps6287x_regulator_pdata), + .probe = tps6287x_regulator_probe, +}; -- 2.17.1

2 1

[PATCH] power: regulator: Fix error code in regulator_list_autoset()
by Dan Carpenter 06 Sep '24

06 Sep '24

This condition has a bitwise & vs logical && typo so it only preserves odd number error codes. Fixes: 3b880757abca ("dm: regulator: uclass driver code cleanup") Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- drivers/power/regulator/regulator-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 77d101f262e2..de2bb3b1cd88 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -390,7 +390,7 @@ int regulator_list_autoset(const char *list_platname[], ret = regulator_autoset_by_name(list_platname[i], &dev); if (ret != -EMEDIUMTYPE && verbose) regulator_show(dev, ret); - if (ret & !error) + if (ret && !error) error = ret; if (list_devp) -- 2.43.0

3 2

[PATCH v2] mmc: sdhci-cadence: Add support for Cadence sdmmc v6
by Kuan Lim Lee 06 Sep '24

06 Sep '24

Cadence SDMMC v6 controller has a lot of changes on initialize compared to v4 controller. PHY is needed by v6 controller. Signed-off-by: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> Co-developed-by: Alex Soo <yuklin.soo(a)starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim(a)starfivetech.com> --- Changes in v2 - Rename file sdhci-cadence6-phy.c to sdhci-cadence6.c - Remove CONFIG_MMC_SDHCI_CADENCE_V6 - Rewrite code of v6 configuration part - Add sdhci_cdns6_phy_init() function --- drivers/mmc/Makefile | 1 + drivers/mmc/sdhci-cadence.c | 63 ++------ drivers/mmc/sdhci-cadence.h | 69 ++++++++ drivers/mmc/sdhci-cadence6.c | 294 +++++++++++++++++++++++++++++++++++ 4 files changed, 376 insertions(+), 51 deletions(-) create mode 100644 drivers/mmc/sdhci-cadence.h create mode 100644 drivers/mmc/sdhci-cadence6.c diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 2c65c4765a..136f06600a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence6.o obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 327a05ad11..a5533af045 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -17,56 +17,7 @@ #include <linux/libfdt.h> #include <mmc.h> #include <sdhci.h> - -/* HRS - Host Register Set (specific to Cadence) */ -#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ -#define SDHCI_CDNS_HRS04_ACK BIT(26) -#define SDHCI_CDNS_HRS04_RD BIT(25) -#define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) -#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) -#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) - -#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ -#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) -#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) -#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) -#define SDHCI_CDNS_HRS06_MODE_SD 0x0 -#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 -#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 - -/* SRS - Slot Register Set (SDHCI-compatible) */ -#define SDHCI_CDNS_SRS_BASE 0x200 - -/* PHY */ -#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 -#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 -#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 -#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 -#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 -#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 -#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b -#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c -#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d - -/* - * The tuned val register is 6 bit-wide, but not the whole of the range is - * available. The range 0-42 seems to be available (then 43 wraps around to 0) - * but I am not quite sure if it is official. Use only 0 to 39 for safety. - */ -#define SDHCI_CDNS_MAX_TUNING_LOOP 40 - -struct sdhci_cdns_plat { - struct mmc_config cfg; - struct mmc mmc; - void __iomem *hrs_addr; -}; +#include "sdhci-cadence.h" struct sdhci_cdns_phy_cfg { const char *property; @@ -163,6 +114,9 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); + + if (device_is_compatible(mmc->dev, "cdns,sd6hc")) + sdhci_cdns6_phy_adj(mmc->dev, plat, mode); } static const struct sdhci_ops sdhci_cdns_ops = { @@ -176,6 +130,9 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, u32 tmp; int i, ret; + if (device_is_compatible(plat->mmc.dev, "cdns,sd6hc")) + return sdhci_cdns6_set_tune_val(plat, val); + if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) return -EINVAL; @@ -282,7 +239,10 @@ static int sdhci_cdns_probe(struct udevice *dev) if (ret) return ret; - ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); + if (device_is_compatible(dev, "cdns,sd6hc")) + ret = sdhci_cdns6_phy_init(dev, plat); + else + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); if (ret) return ret; @@ -301,6 +261,7 @@ static int sdhci_cdns_probe(struct udevice *dev) static const struct udevice_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc" }, { .compatible = "cdns,sd4hc" }, + { .compatible = "cdns,sd6hc" }, { /* sentinel */ } }; diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h new file mode 100644 index 0000000000..c20efd899a --- /dev/null +++ b/drivers/mmc/sdhci-cadence.h @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + */ + +#ifndef SDHCI_CADENCE_H_ +#define SDHCI_CADENCE_H_ + +/* HRS - Host Register Set (specific to Cadence) */ +/* PHY access port */ +#define SDHCI_CDNS_HRS04 0x10 +/* Cadence V4 HRS04 Description*/ +#define SDHCI_CDNS_HRS04_ACK BIT(26) +#define SDHCI_CDNS_HRS04_RD BIT(25) +#define SDHCI_CDNS_HRS04_WR BIT(24) +#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) +#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) +#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) + +#define SDHCI_CDNS_HRS05 0x14 + +/* eMMC control */ +#define SDHCI_CDNS_HRS06 0x18 +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) +#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 + +/* Cadence V4 PHY Setting*/ +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c +#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d + +/* + * The tuned val register is 6 bit-wide, but not the whole of the range is + * available. The range 0-42 seems to be available (then 43 wraps around to 0) + * but I am not quite sure if it is official. Use only 0 to 39 for safety. + */ +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 + +struct sdhci_cdns_plat { + struct mmc_config cfg; + struct mmc mmc; + void __iomem *hrs_addr; +}; + +int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode); +int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat); +int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val); + +#endif diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c new file mode 100644 index 0000000000..ea0857e655 --- /dev/null +++ b/drivers/mmc/sdhci-cadence6.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-or-platform_driver +/* + * Copyright (C) 2023 Starfive. + * Author: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/global_data.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <linux/libfdt.h> +#include <mmc.h> +#include <sdhci.h> +#include "sdhci-cadence.h" + +/* IO Delay Information */ +#define SDHCI_CDNS_HRS07 0X1C +#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16) +#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0) + +/* PHY Control and Status */ +#define SDHCI_CDNS_HRS09 0x24 +#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16) +#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15) +#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3) +#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2) +#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1) +#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0) + +/* SDCLK adjustment */ +#define SDHCI_CDNS_HRS10 0x28 +#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16) + +/* CMD/DAT output delay */ +#define SDHCI_CDNS_HRS16 0x40 + +/* PHY Special Function Registers */ +/* register to control the DQ related timing */ +#define PHY_DQ_TIMING_REG_ADDR 0x2000 + +/* register to control the DQS related timing */ +#define PHY_DQS_TIMING_REG_ADDR 0x2004 + +/* register to control the gate and loopback control related timing */ +#define PHY_GATE_LPBK_CTRL_REG_ADDR 0x2008 + +/* register to control the Master DLL logic */ +#define PHY_DLL_MASTER_CTRL_REG_ADDR 0x200C + +/* register to control the Slave DLL logic */ +#define PHY_DLL_SLAVE_CTRL_REG_ADDR 0x2010 +#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY GENMASK(31, 24) +#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY GENMASK(7, 0) + +#define SDHCI_CDNS6_PHY_CFG_NUM 4 +#define SDHCI_CDNS6_CTRL_CFG_NUM 4 + +struct sdhci_cdns6_phy_cfg { + const char *property; + u32 val; +}; + +struct sdhci_cdns6_ctrl_cfg { + const char *property; + u32 val; +}; + +static struct sdhci_cdns6_phy_cfg sd_ds_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-sd-ds", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-sd-ds", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-sd-ds", 0x00000000, }, + { "cdns,phy-dq-timing-delay-sd-ds", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_sdr_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-semmc-sdr", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-sdr", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-sdr", 0x00000000, }, + { "cdns,phy-dq-timing-delay-emmc-sdr", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_ddr_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-ddr", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-ddr", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-ddr", 0x00000000, }, + { "cdns,phy-dq-timing-delay-emmc-ddr", 0x10000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_hs200_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-hs200", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs200", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-hs200", 0x00DADA00, }, + { "cdns,phy-dq-timing-delay-emmc-hs200", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_hs400_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-hs400", 0x00280004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs400", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-hs400", 0x00DAD800, }, + { "cdns,phy-dq-timing-delay-emmc-hs400", 0x00000001, }, +}; + +static struct sdhci_cdns6_ctrl_cfg sd_ds_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-sd-ds", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-sd-ds", 0x00020000, }, + { "cdns,ctrl-hrs16-slave-ctrl-sd-ds", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-sd-ds", 0x00080000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_sdr_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-sdr", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-sdr", 0x00030000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-sdr", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-sdr", 0x00080000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_ddr_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-ddr", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-ddr", 0x00020000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-ddr", 0x11000001, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-ddr", 0x00090001, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_hs200_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-hs200", 0x00018000, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs200", 0x00080000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs200", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-hs200", 0x00090000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_hs400_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-hs400", 0x00018000, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs400", 0x00080000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs400", 0x11000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-hs400", 0x00080000, }, +}; + +static u32 sdhci_cdns6_read_phy_reg(struct sdhci_cdns_plat *plat, u32 addr) +{ + writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04); + return readl(plat->hrs_addr + SDHCI_CDNS_HRS05); +} + +static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u32 val) +{ + writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04); + writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05); +} + +static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset) +{ + void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09; + u32 tmp; + int ret; + + tmp = readl(reg); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + + /* Switch On DLL Reset */ + if (reset) + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 0); + else + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 1); + + writel(tmp, reg); + + /* After reset, wait until HRS09.PHY_INIT_COMPLETE is set to 1 within 3000us*/ + if (!reset) { + ret = readl_poll_timeout(reg, tmp, (tmp & SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE), + 3000); + } + + return ret; +} + +int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode) +{ + DECLARE_GLOBAL_DATA_PTR; + struct sdhci_cdns6_phy_cfg *sdhci_cdns6_phy_cfgs; + struct sdhci_cdns6_ctrl_cfg *sdhci_cdns6_ctrl_cfgs; + const fdt32_t *prop; + u32 tmp; + int i, ret; + + switch (mode) { + case SDHCI_CDNS_HRS06_MODE_SD: + sdhci_cdns6_phy_cfgs = sd_ds_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = sd_ds_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_SDR: + sdhci_cdns6_phy_cfgs = emmc_sdr_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_sdr_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_DDR: + sdhci_cdns6_phy_cfgs = emmc_ddr_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_ddr_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_HS200: + sdhci_cdns6_phy_cfgs = emmc_hs200_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_hs200_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_HS400: + sdhci_cdns6_phy_cfgs = emmc_hs400_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_hs400_ctrl_cfgs; + break; + default: + return -EINVAL; + } + + for (i = 0; i < SDHCI_CDNS6_PHY_CFG_NUM; i++) { + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + sdhci_cdns6_phy_cfgs[i].property, NULL); + if (prop) + sdhci_cdns6_phy_cfgs[i].val = *prop; + } + + for (i = 0; i < SDHCI_CDNS6_CTRL_CFG_NUM; i++) { + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + sdhci_cdns6_ctrl_cfgs[i].property, NULL); + if (prop) + sdhci_cdns6_ctrl_cfgs[i].val = *prop; + } + + /* Switch On the DLL Reset */ + sdhci_cdns6_reset_phy_dll(plat, true); + + sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val); + sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val); + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val); + + /* Switch Off the DLL Reset */ + ret = sdhci_cdns6_reset_phy_dll(plat, false); + if (ret) { + printf("sdhci_cdns6_reset_phy is not completed\n"); + return ret; + } + + /* Set PHY DQ TIMING control register */ + sdhci_cdns6_write_phy_reg(plat, PHY_DQ_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[3].val); + + /* Set HRS09 register */ + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~(SDHCI_CDNS_HRS09_EXTENDED_WR_MODE | + SDHCI_CDNS_HRS09_EXTENDED_RD_MODE | + SDHCI_CDNS_HRS09_RDDATA_EN | + SDHCI_CDNS_HRS09_RDCMD_EN); + tmp |= sdhci_cdns6_ctrl_cfgs[0].val; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS09); + + /* Set HRS10 register */ + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS10); + tmp &= ~SDHCI_CDNS_HRS10_HCSDCLKADJ; + tmp |= sdhci_cdns6_ctrl_cfgs[1].val; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS10); + + /* Set HRS16 register */ + writel(sdhci_cdns6_ctrl_cfgs[2].val, plat->hrs_addr + SDHCI_CDNS_HRS16); + + /* Set HRS07 register */ + writel(sdhci_cdns6_ctrl_cfgs[3].val, plat->hrs_addr + SDHCI_CDNS_HRS07); + + return 0; +} + +int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat) +{ + return sdhci_cdns6_phy_adj(dev, plat, SDHCI_CDNS_HRS06_MODE_SD); +} + +int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) +{ + u32 tmp, tuneval; + + tuneval = (val * 256) / SDHCI_CDNS_MAX_TUNING_LOOP; + + tmp = sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR); + tmp &= ~(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY | + PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY); + tmp |= FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY, tuneval) | + FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY, tuneval); + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp); + + return 0; +} -- 2.34.1

3 2

[PATCH] mmc: msm_sdhci: program core_vendor_spec
by Caleb Connolly 06 Sep '24

06 Sep '24

After resetting the host controller, program in the POR val for this register just like the Linux driver does. This seems to help with initialization when running U-Boot as the primary bootloader on some boards. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- drivers/mmc/msm_sdhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 4ce0de6c47d8..8b3188fa20d4 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -31,8 +31,10 @@ #define SDCC_MCI_STATUS2 0x6C #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 +#define CORE_VENDOR_SPEC_POR_VAL 0xa9c + struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; }; @@ -45,21 +47,25 @@ struct msm_sdhc { struct msm_sdhc_variant_info { bool mci_removed; + u32 core_vendor_spec; u32 core_vendor_spec_capabilities0; }; DECLARE_GLOBAL_DATA_PTR; static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; ofnode node = dev_ofnode(dev); ulong clk_rate; int ret, i = 0, n_clks; const char *clk_name; + var_info = (void *)dev_get_driver_data(dev); + ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) clk_rate = 201500000; @@ -104,8 +110,11 @@ static int msm_sdc_clk_init(struct udevice *dev) log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate ? (int)PTR_ERR((void *)clk_rate) : 0); return -EINVAL; } + writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, + prv->host.ioaddr + var_info->core_vendor_spec); + return 0; } static int msm_sdc_mci_init(struct msm_sdhc *prv) @@ -254,14 +263,16 @@ static int msm_sdc_bind(struct udevice *dev) static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + .core_vendor_spec = 0x10c, .core_vendor_spec_capabilities0 = 0x11c, }; static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + .core_vendor_spec = 0x20c, .core_vendor_spec_capabilities0 = 0x21c, }; static const struct udevice_id msm_mmc_ids[] = { -- 2.45.0

2 1

[PATCH] mmc: Change the frequency to MMC_HS_52 when selecting hs400
by Venkatesh Yadav Abbarapu 06 Sep '24

06 Sep '24

Per JESD84-B51 P47, host need to change frequency to <=52MHz after setting HS_TIMING to 0x1, and host need to set the 8-bit DDR buswidth. Currently setting the frequency to 26MHz and trying to switch 8-bit DDR buswidth resulting timeouts. mmc dev 1 0 Select HS400 failed -110 switch to partitions #0, OK mmc1(part 0) is current device Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mmc/mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 7b068c71ff..a2ed99aefe 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -962,8 +962,8 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, * Extended CSD. Reconfigure the controller to run at HS mode. */ if (hsdowngrade) { - mmc_select_mode(mmc, MMC_HS); - mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + mmc_select_mode(mmc, MMC_HS_52); + mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS_52), false); } #endif @@ -2043,7 +2043,7 @@ static int mmc_select_hs400(struct mmc *mmc) } /* Set back to HS */ - mmc_set_card_speed(mmc, MMC_HS, true); + mmc_set_card_speed(mmc, MMC_HS_52, true); err = mmc_hs400_prepare_ddr(mmc); if (err) -- 2.17.1

3 2

[RESEND PATCH v4 0/3] provide names for emmc hardware partitions
by Tim Harvey 05 Sep '24

05 Sep '24

Modern eMMC v4+ devices have multiple hardware partitions per the JEDEC specification described as: Boot Area Partition 1 Boot Area Partition 2 RPMB Partition General Purpose Partition 1 General Purpose Partition 2 General Purpose Partition 3 General Purpose Partition 4 User Data Area These are referenced by fields in the PARTITION_CONFIG register (Extended CSD Register 179) which is defined as: bit 7: reserved bit 6: BOOT_ACK 0x0: No boot acknowledge sent (default 0x1: Boot acknowledge sent during boot operation Bit bit 5:3: BOOT_PARTITION_ENABLE 0x0: Device not boot enabled (default) 0x1: Boot Area partition 1 enabled for boot 0x2: Boot Area partition 2 enabled for boot 0x3-0x6: Reserved 0x7: User area enabled for boot bit 2:0 PARTITION_ACCESS 0x0: No access to boot partition (default) 0x1: Boot Area partition 1 0x2: Boot Area partition 2 0x3: Replay Protected Memory Block (RPMB) 0x4: Access to General Purpose partition 1 0x5: Access to General Purpose partition 2 0x6: Access to General Purpose partition 3 0x7: Access to General Purpose partition 4 Note that setting PARTITION_ACCESS to 0x0 results in selecting the User Data Area partition. You can see above that the two fields BOOT_PARTITION_ENABLE and PARTITION_ACCESS do not use the same enumerated values. U-Boot uses a set of macros to access fields of the PARTITION_CONFIG register: EXT_CSD_BOOT_ACK_ENABLE (1 << 6) EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) EXT_CSD_BOOT_ACK(x) (x << 6) EXT_CSD_BOOT_PART_NUM(x) (x << 3) EXT_CSD_PARTITION_ACCESS(x) (x << 0) EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) There are various places in U-Boot where the BOOT_PARTITION_ENABLE field is accessed via EXT_CSD_EXTRACT_PARTITION_ACCESS and converted to a hardware partition consistent with the definition of the PARTITION_ACCESS field used by the various mmc_switch incarnations. To add some sanity to the distinction between BOOT_PARTITION_ENABLE (used to specify the active device on power-cycle) and PARTITION_ACCESS (used to switch between hardware partitions) create two enumerated types and use them wherever struct mmc * part_config is used or the above macros are used. Additionally provide arrays of the field names and allow those to be used in the 'mmc partconf' command and in board support files. The first patch adds enumerated types and makes use of them which represents no compiled code change. The 2nd patch adds the array of names and uses them in the 'mmc partconf' command. The 3rd patch uses the array of hardware partition names in a board support file to show what emmc hardware partition U-Boot is being loaded from. I'm sending this as a series this time around as previously it was repsented as two different patches. Tim Harvey (3): mmc: use an enumerated type to represent PARTITION_CONFIG fields mmc: allow use of hardware partition names for mmc partconf venice: show emmc boot hardware partition arch/arm/mach-imx/image-container.c | 10 ++++----- arch/arm/mach-sunxi/board.c | 2 +- board/gateworks/venice/spl.c | 20 ++++++++++++----- board/gateworks/venice/venice.c | 22 +++++++++--------- board/purism/librem5/librem5.c | 4 ++-- board/storopack/smegw01/smegw01.c | 4 ++-- cmd/mmc.c | 27 ++++++++++++++++++---- cmd/mvebu/bubt.c | 4 ++-- common/spl/spl_mmc.c | 4 ++-- drivers/mmc/mmc.c | 35 +++++++++++++++++++++++++++++ include/mmc.h | 26 +++++++++++++++++++++ 11 files changed, 123 insertions(+), 35 deletions(-) -- 2.25.1

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[PATCH v4] mmc: Poll CD in case cyclic framework is enabled
by Marek Vasut 05 Sep '24

05 Sep '24

In case the cyclic framework is enabled, poll the card detect of already initialized cards and deinitialize them in case they are removed. Since the card initialization is a longer process and card initialization is done on first access to an uninitialized card anyway, avoid initializing newly detected uninitialized cards in the cyclic callback. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> --- V2: Move the cyclic registration/unregistration into mmc init/deinit V3: Replace if (CONFIG_IS_ENABLED(CYCLIC)...) with #if as the former does not work with structure members V4: Stuff the code with CONFIG_IS_ENABLED() variants to avoid #ifdefs --- drivers/mmc/mmc.c | 32 ++++++++++++++++++++++++++++++++ include/mmc.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index eb5010c1465..e90ffd5dcd1 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2985,6 +2985,20 @@ static int mmc_complete_init(struct mmc *mmc) return err; } +static void __maybe_unused mmc_cyclic_cd_poll(void *ctx) +{ + struct mmc *m = ctx; + + if (!m->has_init) + return; + + if (mmc_getcd(m)) + return; + + mmc_deinit(m); + m->has_init = 0; +} + int mmc_init(struct mmc *mmc) { int err = 0; @@ -3007,6 +3021,19 @@ int mmc_init(struct mmc *mmc) if (err) pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic), (NULL))) { + /* Register cyclic function for card detect polling */ + CONFIG_IS_ENABLED(CYCLIC, + (mmc->cyclic = cyclic_register(mmc_cyclic_cd_poll, + 100 * 1000, + mmc->cfg->name, mmc))); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic), (NULL))) { + printf("Failed to register %s CD poll function\n", + mmc->cfg->name); + err = -EINVAL; + } + } + return err; } @@ -3014,6 +3041,11 @@ int mmc_deinit(struct mmc *mmc) { u32 caps_filtered; + if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic), (NULL))) { + cyclic_unregister(CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic), NULL)); + CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic = NULL)); + } + if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) diff --git a/include/mmc.h b/include/mmc.h index 1022db3ffa7..706566fa1ad 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -14,6 +14,7 @@ #include <linux/sizes.h> #include <linux/compiler.h> #include <linux/dma-direction.h> +#include <cyclic.h> #include <part.h> struct bd_info; @@ -739,6 +740,8 @@ struct mmc { u8 hs400_tuning; enum bus_mode user_speed_mode; /* input speed mode from user */ + + CONFIG_IS_ENABLED(CYCLIC, (struct cyclic_info *cyclic)); }; #if CONFIG_IS_ENABLED(DM_MMC) -- 2.43.0

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[PATCH 1/2] net: phy: add PSGMII (Penta SGMII) mode
by Robert Marko 05 Sep '24

05 Sep '24

The PSGMII interface is similar to QSGMII. The main difference is that the PSGMII interface combines five SGMII lines into a single link while in QSGMII only four lines are combined. Similarly to the QSGMII, this interface mode might also needs special handling within the MAC driver. It is commonly used by Qualcomm with their QCA807x PHY series and modern WiSoC-s. Add definitions for the PHY layer to allow to express this type of connection between the MAC and PHY. This is basically a direct port from Linux which already supports this mode. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- include/phy_interface.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/phy_interface.h b/include/phy_interface.h index 31be3228c7..04826bc65d 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -31,6 +31,7 @@ typedef enum { PHY_INTERFACE_MODE_XGMII, PHY_INTERFACE_MODE_XLGMII, PHY_INTERFACE_MODE_MOCA, + PHY_INTERFACE_MODE_PSGMII, PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TRGMII, PHY_INTERFACE_MODE_100BASEX, @@ -79,6 +80,7 @@ static const char * const phy_interface_strings[] = { [PHY_INTERFACE_MODE_XGMII] = "xgmii", [PHY_INTERFACE_MODE_XLGMII] = "xlgmii", [PHY_INTERFACE_MODE_MOCA] = "moca", + [PHY_INTERFACE_MODE_PSGMII] = "psgmii", [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TRGMII] = "trgmii", [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x", -- 2.45.1

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[PATCH 0/7] Add the USB5744 hub driver as per new DT binding
by Venkatesh Yadav Abbarapu 02 Sep '24

02 Sep '24

Add the usb5744/usb2744 hub driver which does the reset gpio toggling and the i2c initialization sequence. Tested the USB5744/USB2744 usb hub for usb0, usb1 with the DT nodes on KR260 board. Venkatesh Yadav Abbarapu (7): usb: onboard-hub: Add reset-gpio support usb: onboard-hub: Fix the return values of regulator APIs usb: onboard-hub: add support for Microchip USB5744 usb: onboard-hub: Add i2c initialization for usb5744 hub usb: onboard-hub: Bail out if peer hub is already probed configs: zynqmp_kria: Enable the USB onboard hub arm64: zynqmp: Update the usb5744 hub node as per binding arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 48 +++++++ arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 48 +++++++ arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 18 +++ arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 25 +++- common/usb_onboard_hub.c | 176 +++++++++++++++++++++++-- configs/xilinx_zynqmp_kria_defconfig | 1 + 6 files changed, 304 insertions(+), 12 deletions(-) -- 2.17.1

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