May 2024 - U-Boot

[PATCH v4] test/py: net_boot: Add test cases for net boot
by Love Kumar 07 May '24

07 May '24

Add tests for booting image using tftpboot/pxe boot commands, tftpboot boot case loads the FIT image into DDR and boots using bootm command whereas pxe boot cases downloads the pxe configuration file from the TFTP server and interprets it to boot the images mentioned in the pxe configurations file. This test relies on boardenv_* containing configuration values including the parameter 'pattern'. tftpboot/pxe boot cases boots the Linux till the boot log pattern value is matched. For example, if the parameter 'pattern' is defined as 'login:', it will boot till login prompt. Signed-off-by: Love Kumar <love.kumar(a)amd.com> --- Changes in v2: - Expand commit message Changes in v3: - Add the config option to skip the test - Remove imi command to check FIT image config - Configure static networking only if DHCP fails Changes in v4: - Use configured timeout for tftpboot --- test/py/tests/test_net_boot.py | 394 +++++++++++++++++++++++++++++++++ 1 file changed, 394 insertions(+) create mode 100644 test/py/tests/test_net_boot.py diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py new file mode 100644 index 000000000000..fb0fb7e80414 --- /dev/null +++ b/test/py/tests/test_net_boot.py @@ -0,0 +1,394 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +import pytest +import u_boot_utils +import test_net + +""" +Note: This test relies on boardenv_* containing configuration values to define +which the network environment available for testing. Without this, this test +will be automatically skipped. + +For example: + +# Details regarding a boot image file that may be read from a TFTP server. This +# variable may be omitted or set to None if TFTP boot testing is not possible +# or desired. +env__net_tftp_bootable_file = { + 'fn': 'image.ub', + 'addr': 0x10000000, + 'size': 5058624, + 'crc32': 'c2244b26', + 'pattern': 'Linux', + 'config': 'config@2', + 'timeout': 50000, +} + +# False or omitted if a TFTP boot test should be tested. +# If TFTP boot testing is not possible or desired, set this variable to True. +# For example: If FIT image is not proper to boot +env__tftp_boot_test_skip = False + +# Here is the example of FIT image configurations: +configurations { + default = "config@1"; + config@1 { + description = "Boot Linux kernel with config@1"; + kernel = "kernel@0"; + fdt = "fdt@0"; + ramdisk = "ramdisk@0"; + hash@1 { + algo = "sha1"; + }; + }; + config@2 { + description = "Boot Linux kernel with config@2"; + kernel = "kernel@1"; + fdt = "fdt@1"; + ramdisk = "ramdisk@1"; + hash@1 { + algo = "sha1"; + }; + }; +}; + +# Details regarding a file that may be read from a TFTP server. This variable +# may be omitted or set to None if PXE testing is not possible or desired. +env__net_pxe_bootable_file = { + 'fn': 'default', + 'addr': 0x10000000, + 'size': 74, + 'timeout': 50000, + 'pattern': 'Linux', + 'valid_label': '1', + 'invalid_label': '2', + 'exp_str_invalid': 'Skipping install for failure retrieving', + 'local_label': '3', + 'exp_str_local': 'missing environment variable: localcmd', + 'empty_label': '4', + 'exp_str_empty': 'No kernel given, skipping boot', +} + +# False or omitted if a PXE boot test should be tested. +# If PXE boot testing is not possible or desired, set this variable to True. +# For example: If pxe configuration file is not proper to boot +env__pxe_boot_test_skip = False + +# Here is the example of pxe configuration file ordered based on the execution +# flow: +1) /tftpboot/pxelinux.cfg/default-arm-zynqmp + + menu include pxelinux.cfg/default-arm + timeout 50 + + default Linux + +2) /tftpboot/pxelinux.cfg/default-arm + + menu title Linux boot selections + menu include pxelinux.cfg/default + + label install + menu label Invalid boot + kernel kernels/install.bin + append console=ttyAMA0,38400 debug earlyprintk + initrd initrds/uzInitrdDebInstall + + label local + menu label Local boot + append root=/dev/sdb1 + localboot 1 + + label boot + menu label Empty boot + +3) /tftpboot/pxelinux.cfg/default + + label Linux + menu label Boot kernel + kernel Image + fdt system.dtb + initrd rootfs.cpio.gz.u-boot +""" + +def setup_tftpboot_boot(u_boot_console): + f = u_boot_console.config.env.get('env__net_tftp_bootable_file', None) + if not f: + pytest.skip('No TFTP bootable file to read') + + test_net.test_net_dhcp(u_boot_console) + if not test_net.net_set_up: + test_net.test_net_setup_static(u_boot_console) + + addr = f.get('addr', None) + if not addr: + addr = u_boot_utils.find_ram_base(u_boot_console) + + fn = f['fn'] + timeout = f.get('timeout', 50000) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert expected_text in output + + expected_crc = f.get('crc32', None) + output = u_boot_console.run_command('crc32 %x $filesize' % addr) + if expected_crc: + assert expected_crc in output + + pattern = f.get('pattern') + config = f.get('config', None) + + return addr, pattern, timeout, config + +(a)pytest.mark.buildconfigspec('cmd_net') +def test_net_tftpboot_boot(u_boot_console): + """Boot the loaded image + + A boot file (fit image) is downloaded from the TFTP server and booted using + bootm command with the default fit configuration, its boot log pattern are + validated. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__tftp_boot_test_skip', True): + pytest.skip('TFTP boot test is not enabled!') + + addr, pattern, timeout, imcfg = setup_tftpboot_boot(u_boot_console) + with u_boot_console.temporary_timeout(timeout): + try: + # wait_for_prompt=False makes the core code not wait for the U-Boot + # prompt code to be seen, since it won't be on a successful kernel + # boot + u_boot_console.run_command('bootm %x'% addr, wait_for_prompt=False) + # You might want to expand wait_for() with options to add extra bad + # patterns which immediately indicate a failed boot, or add a new + # "with object" function u_boot_console.enable_check() that can + # cause extra patterns like the U-Boot console prompt, U-Boot boot + # error messages, kernel boot error messages, etc. to fail the + # wait_for(). + + # Wait for boot log pattern + u_boot_console.wait_for(pattern) + finally: + # This forces the console object to be shutdown, so any subsequent + # test will reset the board back into U-Boot. We want to force this + # no matter whether the kernel boot passed or failed. + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +(a)pytest.mark.buildconfigspec('cmd_net') +def test_net_tftpboot_boot_config(u_boot_console): + """Boot the loaded image from FIT image configuration + + A boot file (fit image) is downloaded from the TFTP server and booted using + bootm command with the custom fit configuration, its boot log pattern are + validated. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__tftp_boot_test_skip', True): + pytest.skip('TFTP boot test is not enabled!') + + addr, pattern, timeout, imcfg = setup_tftpboot_boot(u_boot_console) + + with u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command( + 'bootm %x#%s' % (addr, imcfg), wait_for_prompt=False + ) + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +def setup_pxe_boot(u_boot_console): + f = u_boot_console.config.env.get('env__net_pxe_bootable_file', None) + if not f: + pytest.skip('No PXE bootable file to read') + + test_net.test_net_dhcp(u_boot_console) + test_net.test_net_setup_static(u_boot_console) + return f + +(a)pytest.mark.buildconfigspec('cmd_net') +(a)pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot(u_boot_console): + """Test the pxe boot command. + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert "Config file 'default.boot' found" in output + + pattern = f.get('pattern') + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +(a)pytest.mark.buildconfigspec('cmd_net') +(a)pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot_config(u_boot_console): + """Test the pxe boot command by selecting different combination of labels + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + local_label = f['local_label'] + empty_label = f['empty_label'] + exp_str_local = f['exp_str_local'] + exp_str_empty = f['exp_str_empty'] + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert "Config file 'default.boot' found" in output + + pattern = f.get('pattern') + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + + # pxe config is loaded where multiple labels are there and need to + # select particular label to boot and check for expected string + # In this case, local label is selected and it should look for + # localcmd env variable and if that variable is not defined it + # should not boot it and come out to u-boot prompt + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(local_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_local]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_local} did not match!' + + # In this case, empty label is selected and it should look for + # kernel image path and if it is not set it should fail it and load + # default label to boot + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(empty_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_empty]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_empty} did not match!' + + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +(a)pytest.mark.buildconfigspec('cmd_net') +(a)pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot_config_invalid(u_boot_console): + """Test the pxe boot command by selecting invalid label + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + invalid_label = f['invalid_label'] + exp_str_invalid = f['exp_str_invalid'] + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert "Config file 'default.boot' found" in output + + pattern = f.get('pattern') + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + + # pxe config is loaded where multiple labels are there and need to + # select particular label to boot and check for expected string + # In this case invalid label is selected, it should load invalid + # label and if it fails it should load the default label to boot + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(invalid_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_invalid]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_invalid} did not match!' + + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() -- 2.25.1

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[PATCH 00/18] Remove <common.h> from a number of places
by Tom Rini 07 May '24

07 May '24

Hey all, This series is the next step in winding down usage of <common.h> in order to be able to then remove it. This covers not quite 25% of the remaining users of the file. Of what is left, it's either arch/arm/, board/ or drivers/ code. I am likely to start tackling arch/arm/ next, and depending on how exactly I break that down I may try and cover some board/ code as well (for example, tackle arch/arm/mach-omap/ and arch/arm/mach-k3 and board/ti/ (and then the other vendors too..) in one commit. -- Tom

1 19

[RFC PATCH 0/5] Implement exiting 4-byte adressing mode before reset
by Robert Marko 07 May '24

07 May '24

This fixes the issue with 4-byte adressing mode being left enabled on board reset. That is an issue on Qualcomm IPQ4019 boards since the CPU expects flash to be in 3-byte adressing mode and will just hang otherwise. Note that this does not fix a case where you remove the power while U-Boot is still running and in that case it will still be stuck in 4-byte mode. Robert Marko (5): dm: core: add on_reset method dm: core: introduce uclass_id_on_reset() mtd: spi-nor: rename and export 4-byte adressing mode function mtd: spi: sf: implement .on_reset method sysreset: call .on_reset for UCLASS_SPI_FLASH before reset request drivers/core/uclass.c | 13 +++++++++++++ drivers/mtd/spi/sf_probe.c | 10 ++++++++++ drivers/mtd/spi/spi-nor-core.c | 7 +++---- drivers/sysreset/sysreset-uclass.c | 7 +++++++ include/dm/device.h | 2 ++ include/dm/uclass.h | 8 ++++++++ include/linux/mtd/spi-nor.h | 10 ++++++++++ 7 files changed, 53 insertions(+), 4 deletions(-) -- 2.45.0

1 5

[PATCH] usb: dwc2: Add in version 4xx compatibility
by Greg Malysa 07 May '24

07 May '24

From: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> This adds the Synopsys device id for version 4xx of the designware IP block and extends the version check to include it to permit new hardware to run. It does not add any 4xx-specific features. Signed-off-by: Ian Roberts <ian.roberts(a)timesys.com> Signed-off-by: Greg Malysa <greg.malysa(a)timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> --- --- drivers/usb/host/dwc2.c | 3 ++- drivers/usb/host/dwc2.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 637eb2dd06..6fdde6a9a7 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -1180,7 +1180,8 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) snpsid >> 12 & 0xf, snpsid & 0xfff); if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && - (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx && + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) { dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); return -ENODEV; diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 6f022e33a1..f202d55eb2 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -739,6 +739,7 @@ struct dwc2_core_regs { #define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7 #define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12) #define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12) +#define DWC2_SNPSID_DEVID_VER_4xx (0x4f544 << 12) #define DWC2_SNPSID_DEVID_MASK (0xfffff << 12) #define DWC2_SNPSID_DEVID_OFFSET 12 -- 2.43.2

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[PATCH 00/16] rockchip: Migrate RK3308, RK3328, RK356x and RK3588 to OF_UPSTREAM
by Jonas Karlman 07 May '24

07 May '24

This series migrate RK3308, RK3328, RK356x and RK3588 boards that exists in Linux kernel v6.8 to use OF_UPSTREAM. The usbdp phy driver is also updated to work with the DT binding that is targeted for v6.10. And the usb3 related nodes currently part of the SoC u-boot.dtsi is updated to match the soc/board DT that is targeted for v6.10 in order to avoid breaking changes in future when dts/upstream gets updated. Following targets has not been migrated to use OF_UPSTREAM: - anbernic-rgxx3-rk3566: Multi device target - generic-rk3568: Generic target only meant for U-Boot use - generic-rk3588: Generic target only meant for U-Boot use - nanopi-m4-2gb-rk3399: DDR3 variant of nanopi-m4-rk3399 (LPDDR3) - pinetab2-rk3566: Merged in v6.9-rc1 - toybrick-rk3588: Merged in v6.9-rc1 This series depends on the following series: - rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC [1] - rockchip: rk3399: Sync DT with v6.8 and update defconfigs [2] A copy of this series and its depends can also be found at [3]. [1] https://patchwork.ozlabs.org/cover/1929673/ [2] https://patchwork.ozlabs.org/cover/1930271/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3xxx-of-upstream-v1 Jonas Karlman (16): rockchip: rk3308: Migrate to OF_UPSTREAM rockchip: rk3308: Remove redundant device tree files rockchip: rk3328: Migrate to OF_UPSTREAM rockchip: rk3328: Remove redundant device tree files rockchip: rk3399: Migrate to OF_UPSTREAM rockchip: rk3399: Remove redundant device tree files rockchip: rk356x: Add rk3568-u-boot.dtsi rockchip: rk356x: Migrate to OF_UPSTREAM rockchip: rk356x: Remove redundant device tree files phy: rockchip: usbdp: Find phy-id from the io address phy: rockchip: usbdp: Drop rockchip_u3phy_uboot_init() phy: rockchip: usbdp: Adopt driver to work with upstream DT rockchip: rk3588-rock-5b: Drop usb-typec node from u-boot.dtsi rockchip: rk3588: Update USB3 related nodes in u-boot.dtsi rockchip: rk3588: Migrate to OF_UPSTREAM rockchip: rk3588: Remove redundant device tree files arch/arm/dts/Makefile | 84 - arch/arm/dts/rk3308-evb.dts | 230 -- arch/arm/dts/rk3308-roc-cc.dts | 190 - arch/arm/dts/rk3308-rock-pi-s.dts | 314 -- arch/arm/dts/rk3308.dtsi | 1888 --------- arch/arm/dts/rk3328-evb.dts | 289 -- arch/arm/dts/rk3328-nanopi-r2c-plus.dts | 33 - arch/arm/dts/rk3328-nanopi-r2c.dts | 40 - arch/arm/dts/rk3328-nanopi-r2s.dts | 410 -- arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 42 - arch/arm/dts/rk3328-orangepi-r1-plus.dts | 374 -- arch/arm/dts/rk3328-roc-cc.dts | 384 -- arch/arm/dts/rk3328-rock-pi-e.dts | 445 --- arch/arm/dts/rk3328-rock64.dts | 394 -- arch/arm/dts/rk3328.dtsi | 1944 ---------- arch/arm/dts/rk3399-eaidk-610.dts | 940 ----- arch/arm/dts/rk3399-evb.dts | 485 --- arch/arm/dts/rk3399-ficus.dts | 174 - arch/arm/dts/rk3399-firefly.dts | 944 ----- arch/arm/dts/rk3399-gru-bob.dts | 95 - arch/arm/dts/rk3399-gru-chromebook.dtsi | 590 --- arch/arm/dts/rk3399-gru-kevin.dts | 328 -- arch/arm/dts/rk3399-gru.dtsi | 865 ----- arch/arm/dts/rk3399-khadas-edge-captain.dts | 31 - arch/arm/dts/rk3399-khadas-edge-v.dts | 31 - arch/arm/dts/rk3399-khadas-edge.dts | 13 - arch/arm/dts/rk3399-khadas-edge.dtsi | 837 ---- arch/arm/dts/rk3399-leez-p710.dts | 653 ---- arch/arm/dts/rk3399-nanopc-t4.dts | 137 - arch/arm/dts/rk3399-nanopi-m4.dts | 66 - arch/arm/dts/rk3399-nanopi-m4b.dts | 52 - arch/arm/dts/rk3399-nanopi-neo4.dts | 50 - arch/arm/dts/rk3399-nanopi-r4s.dts | 133 - arch/arm/dts/rk3399-nanopi4.dtsi | 762 ---- arch/arm/dts/rk3399-op1-opp.dtsi | 166 - arch/arm/dts/rk3399-opp.dtsi | 133 - arch/arm/dts/rk3399-orangepi.dts | 896 ----- arch/arm/dts/rk3399-pinebook-pro.dts | 1111 ------ arch/arm/dts/rk3399-pinephone-pro.dts | 621 --- arch/arm/dts/rk3399-puma-haikou.dts | 306 -- arch/arm/dts/rk3399-puma.dtsi | 532 --- arch/arm/dts/rk3399-roc-pc-mezzanine.dts | 111 - arch/arm/dts/rk3399-roc-pc.dts | 12 - arch/arm/dts/rk3399-roc-pc.dtsi | 844 ---- arch/arm/dts/rk3399-rock-4c-plus.dts | 709 ---- arch/arm/dts/rk3399-rock-4se.dts | 65 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 792 ---- arch/arm/dts/rk3399-rock-pi-4a.dts | 24 - arch/arm/dts/rk3399-rock-pi-4c.dts | 80 - arch/arm/dts/rk3399-rock960.dts | 156 - arch/arm/dts/rk3399-rock960.dtsi | 673 ---- arch/arm/dts/rk3399-rockpro64.dts | 30 - arch/arm/dts/rk3399-rockpro64.dtsi | 956 ----- arch/arm/dts/rk3399-t-opp.dtsi | 114 - arch/arm/dts/rk3399.dtsi | 2945 -------------- arch/arm/dts/rk3399pro-rock-pi-n10.dts | 22 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 477 --- arch/arm/dts/rk3399pro.dtsi | 22 - arch/arm/dts/rk3566-anbernic-rgxx3.dtsi | 788 ---- arch/arm/dts/rk3566-quartz64-a.dts | 838 ---- arch/arm/dts/rk3566-quartz64-b.dts | 737 ---- arch/arm/dts/rk3566-radxa-cm3-io.dts | 281 -- arch/arm/dts/rk3566-radxa-cm3.dtsi | 425 -- arch/arm/dts/rk3566-soquartz-blade.dts | 198 - arch/arm/dts/rk3566-soquartz-cm4.dts | 196 - arch/arm/dts/rk3566-soquartz-model-a.dts | 236 -- arch/arm/dts/rk3566-soquartz.dtsi | 684 ---- arch/arm/dts/rk3566.dtsi | 35 - arch/arm/dts/rk3568-bpi-r2-pro.dts | 852 ---- arch/arm/dts/rk3568-evb.dts | 689 ---- arch/arm/dts/rk3568-lubancat-2.dts | 730 ---- arch/arm/dts/rk3568-nanopi-r5c.dts | 112 - arch/arm/dts/rk3568-nanopi-r5s.dts | 136 - arch/arm/dts/rk3568-nanopi-r5s.dtsi | 587 --- arch/arm/dts/rk3568-odroid-m1.dts | 741 ---- arch/arm/dts/rk3568-pinctrl.dtsi | 3214 --------------- arch/arm/dts/rk3568-radxa-cm3i.dtsi | 412 -- arch/arm/dts/rk3568-radxa-e25.dts | 236 -- arch/arm/dts/rk3568-rock-3a.dts | 859 ---- arch/arm/dts/rk3568-u-boot.dtsi | 3 + arch/arm/dts/rk3568.dtsi | 267 -- arch/arm/dts/rk356x.dtsi | 1886 --------- arch/arm/dts/rk3588-coolpi-cm5-evb.dts | 216 -- arch/arm/dts/rk3588-coolpi-cm5.dtsi | 649 ---- arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 23 - arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 31 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 89 - arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 389 -- arch/arm/dts/rk3588-evb1-v10.dts | 1080 ------ arch/arm/dts/rk3588-generic-u-boot.dtsi | 4 - arch/arm/dts/rk3588-jaguar.dts | 803 ---- arch/arm/dts/rk3588-nanopc-t6.dts | 916 ----- arch/arm/dts/rk3588-orangepi-5-plus.dts | 847 ---- arch/arm/dts/rk3588-pinctrl.dtsi | 516 --- arch/arm/dts/rk3588-quartzpro64.dts | 1137 ------ arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 115 +- arch/arm/dts/rk3588-rock-5b.dts | 776 ---- arch/arm/dts/rk3588-turing-rk1.dts | 21 - arch/arm/dts/rk3588-turing-rk1.dtsi | 612 --- arch/arm/dts/rk3588-u-boot.dtsi | 36 +- arch/arm/dts/rk3588.dtsi | 341 -- arch/arm/dts/rk3588j.dtsi | 7 - arch/arm/dts/rk3588s-coolpi-4b.dts | 812 ---- arch/arm/dts/rk3588s-orangepi-5.dts | 667 ---- arch/arm/dts/rk3588s-pinctrl.dtsi | 3447 ----------------- arch/arm/dts/rk3588s-rock-5a.dts | 744 ---- arch/arm/dts/rk3588s-u-boot.dtsi | 34 +- arch/arm/dts/rk3588s.dtsi | 2485 ------------ arch/arm/mach-rockchip/Kconfig | 5 + configs/anbernic-rgxx3-rk3566_defconfig | 1 + configs/bpi-r2-pro-rk3568_defconfig | 2 +- configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- configs/coolpi-4b-rk3588s_defconfig | 2 +- configs/coolpi-cm5-evb-rk3588_defconfig | 2 +- configs/eaidk-610-rk3399_defconfig | 2 +- configs/evb-rk3308_defconfig | 2 +- configs/evb-rk3328_defconfig | 2 +- configs/evb-rk3399_defconfig | 2 +- configs/evb-rk3568_defconfig | 4 +- configs/evb-rk3588_defconfig | 2 +- configs/ficus-rk3399_defconfig | 2 +- configs/firefly-rk3399_defconfig | 2 +- configs/generic-rk3568_defconfig | 1 + configs/generic-rk3588_defconfig | 1 + configs/jaguar-rk3588_defconfig | 2 +- configs/khadas-edge-captain-rk3399_defconfig | 2 +- configs/khadas-edge-rk3399_defconfig | 2 +- configs/khadas-edge-v-rk3399_defconfig | 2 +- configs/leez-rk3399_defconfig | 2 +- configs/lubancat-2-rk3568_defconfig | 2 +- configs/nanopc-t4-rk3399_defconfig | 2 +- configs/nanopc-t6-rk3588_defconfig | 2 +- configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 2 +- configs/nanopi-m4b-rk3399_defconfig | 2 +- configs/nanopi-neo4-rk3399_defconfig | 2 +- configs/nanopi-r2c-plus-rk3328_defconfig | 2 +- configs/nanopi-r2c-rk3328_defconfig | 2 +- configs/nanopi-r2s-rk3328_defconfig | 2 +- configs/nanopi-r4s-rk3399_defconfig | 2 +- configs/nanopi-r5c-rk3568_defconfig | 2 +- configs/nanopi-r5s-rk3568_defconfig | 2 +- configs/neu6a-io-rk3588_defconfig | 2 +- configs/neu6b-io-rk3588_defconfig | 2 +- configs/odroid-m1-rk3568_defconfig | 2 +- configs/orangepi-5-plus-rk3588_defconfig | 2 +- configs/orangepi-5-rk3588s_defconfig | 2 +- configs/orangepi-r1-plus-lts-rk3328_defconfig | 2 +- configs/orangepi-r1-plus-rk3328_defconfig | 2 +- configs/orangepi-rk3399_defconfig | 2 +- configs/pinebook-pro-rk3399_defconfig | 2 +- configs/pinephone-pro-rk3399_defconfig | 2 +- configs/pinetab2-rk3566_defconfig | 1 + configs/puma-rk3399_defconfig | 2 +- configs/quartz64-a-rk3566_defconfig | 2 +- configs/quartz64-b-rk3566_defconfig | 2 +- configs/quartzpro64-rk3588_defconfig | 2 +- configs/radxa-cm3-io-rk3566_defconfig | 2 +- configs/radxa-e25-rk3568_defconfig | 2 +- configs/roc-cc-rk3308_defconfig | 2 +- configs/roc-cc-rk3328_defconfig | 2 +- configs/roc-pc-mezzanine-rk3399_defconfig | 2 +- configs/roc-pc-rk3399_defconfig | 2 +- configs/rock-3a-rk3568_defconfig | 2 +- configs/rock-4c-plus-rk3399_defconfig | 2 +- configs/rock-4se-rk3399_defconfig | 2 +- configs/rock-pi-4-rk3399_defconfig | 2 +- configs/rock-pi-4c-rk3399_defconfig | 2 +- configs/rock-pi-e-rk3328_defconfig | 2 +- configs/rock-pi-n10-rk3399pro_defconfig | 2 +- configs/rock-pi-s-rk3308_defconfig | 2 +- configs/rock5a-rk3588s_defconfig | 2 +- configs/rock5b-rk3588_defconfig | 2 +- configs/rock64-rk3328_defconfig | 2 +- configs/rock960-rk3399_defconfig | 2 +- configs/rockpro64-rk3399_defconfig | 2 +- configs/soquartz-blade-rk3566_defconfig | 2 +- configs/soquartz-cm4-rk3566_defconfig | 2 +- configs/soquartz-model-a-rk3566_defconfig | 2 +- configs/toybrick-rk3588_defconfig | 1 + configs/turing-rk1-rk3588_defconfig | 2 +- .../clock/rockchip,rk3399-dmc.txt | 42 - drivers/phy/rockchip/phy-rockchip-usbdp.c | 126 +- include/dt-bindings/clock/rk3308-cru.h | 387 -- include/dt-bindings/clock/rk3328-cru.h | 393 -- include/dt-bindings/clock/rk3399-cru.h | 751 ---- include/dt-bindings/clock/rk3568-cru.h | 926 ----- .../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ---- include/dt-bindings/power/rk3328-power.h | 19 - include/dt-bindings/power/rk3399-power.h | 53 - include/dt-bindings/power/rk3568-power.h | 32 - include/dt-bindings/power/rk3588-power.h | 69 - .../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ---- 194 files changed, 161 insertions(+), 62287 deletions(-) delete mode 100644 arch/arm/dts/rk3308-evb.dts delete mode 100644 arch/arm/dts/rk3308-roc-cc.dts delete mode 100644 arch/arm/dts/rk3308-rock-pi-s.dts delete mode 100644 arch/arm/dts/rk3308.dtsi delete mode 100644 arch/arm/dts/rk3328-evb.dts delete mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts delete mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts delete mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts delete mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts delete mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts delete mode 100644 arch/arm/dts/rk3328-roc-cc.dts delete mode 100644 arch/arm/dts/rk3328-rock-pi-e.dts delete mode 100644 arch/arm/dts/rk3328-rock64.dts delete mode 100644 arch/arm/dts/rk3328.dtsi delete mode 100644 arch/arm/dts/rk3399-eaidk-610.dts delete mode 100644 arch/arm/dts/rk3399-evb.dts delete mode 100644 arch/arm/dts/rk3399-ficus.dts delete mode 100644 arch/arm/dts/rk3399-firefly.dts delete mode 100644 arch/arm/dts/rk3399-gru-bob.dts delete mode 100644 arch/arm/dts/rk3399-gru-chromebook.dtsi delete mode 100644 arch/arm/dts/rk3399-gru-kevin.dts delete mode 100644 arch/arm/dts/rk3399-gru.dtsi delete mode 100644 arch/arm/dts/rk3399-khadas-edge-captain.dts delete mode 100644 arch/arm/dts/rk3399-khadas-edge-v.dts delete mode 100644 arch/arm/dts/rk3399-khadas-edge.dts delete mode 100644 arch/arm/dts/rk3399-khadas-edge.dtsi delete mode 100644 arch/arm/dts/rk3399-leez-p710.dts delete mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts delete mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts delete mode 100644 arch/arm/dts/rk3399-nanopi-m4b.dts delete mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts delete mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts delete mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi delete mode 100644 arch/arm/dts/rk3399-op1-opp.dtsi delete mode 100644 arch/arm/dts/rk3399-opp.dtsi delete mode 100644 arch/arm/dts/rk3399-orangepi.dts delete mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts delete mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts delete mode 100644 arch/arm/dts/rk3399-puma-haikou.dts delete mode 100644 arch/arm/dts/rk3399-puma.dtsi delete mode 100644 arch/arm/dts/rk3399-roc-pc-mezzanine.dts delete mode 100644 arch/arm/dts/rk3399-roc-pc.dts delete mode 100644 arch/arm/dts/rk3399-roc-pc.dtsi delete mode 100644 arch/arm/dts/rk3399-rock-4c-plus.dts delete mode 100644 arch/arm/dts/rk3399-rock-4se.dts delete mode 100644 arch/arm/dts/rk3399-rock-pi-4.dtsi delete mode 100644 arch/arm/dts/rk3399-rock-pi-4a.dts delete mode 100644 arch/arm/dts/rk3399-rock-pi-4c.dts delete mode 100644 arch/arm/dts/rk3399-rock960.dts delete mode 100644 arch/arm/dts/rk3399-rock960.dtsi delete mode 100644 arch/arm/dts/rk3399-rockpro64.dts delete mode 100644 arch/arm/dts/rk3399-rockpro64.dtsi delete mode 100644 arch/arm/dts/rk3399-t-opp.dtsi delete mode 100644 arch/arm/dts/rk3399.dtsi delete mode 100644 arch/arm/dts/rk3399pro-rock-pi-n10.dts delete mode 100644 arch/arm/dts/rk3399pro-vmarc-som.dtsi delete mode 100644 arch/arm/dts/rk3399pro.dtsi delete mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3.dtsi delete mode 100644 arch/arm/dts/rk3566-quartz64-a.dts delete mode 100644 arch/arm/dts/rk3566-quartz64-b.dts delete mode 100644 arch/arm/dts/rk3566-radxa-cm3-io.dts delete mode 100644 arch/arm/dts/rk3566-radxa-cm3.dtsi delete mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts delete mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts delete mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts delete mode 100644 arch/arm/dts/rk3566-soquartz.dtsi delete mode 100644 arch/arm/dts/rk3566.dtsi delete mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts delete mode 100644 arch/arm/dts/rk3568-evb.dts delete mode 100644 arch/arm/dts/rk3568-lubancat-2.dts delete mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts delete mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts delete mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi delete mode 100644 arch/arm/dts/rk3568-odroid-m1.dts delete mode 100644 arch/arm/dts/rk3568-pinctrl.dtsi delete mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi delete mode 100644 arch/arm/dts/rk3568-radxa-e25.dts delete mode 100644 arch/arm/dts/rk3568-rock-3a.dts create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi delete mode 100644 arch/arm/dts/rk3568.dtsi delete mode 100644 arch/arm/dts/rk356x.dtsi delete mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts delete mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi delete mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io.dts delete mode 100644 arch/arm/dts/rk3588-edgeble-neu6a.dtsi delete mode 100644 arch/arm/dts/rk3588-edgeble-neu6b-io.dts delete mode 100644 arch/arm/dts/rk3588-edgeble-neu6b.dtsi delete mode 100644 arch/arm/dts/rk3588-evb1-v10.dts delete mode 100644 arch/arm/dts/rk3588-jaguar.dts delete mode 100644 arch/arm/dts/rk3588-nanopc-t6.dts delete mode 100644 arch/arm/dts/rk3588-orangepi-5-plus.dts delete mode 100644 arch/arm/dts/rk3588-pinctrl.dtsi delete mode 100644 arch/arm/dts/rk3588-quartzpro64.dts delete mode 100644 arch/arm/dts/rk3588-rock-5b.dts delete mode 100644 arch/arm/dts/rk3588-turing-rk1.dts delete mode 100644 arch/arm/dts/rk3588-turing-rk1.dtsi delete mode 100644 arch/arm/dts/rk3588.dtsi delete mode 100644 arch/arm/dts/rk3588j.dtsi delete mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts delete mode 100644 arch/arm/dts/rk3588s-orangepi-5.dts delete mode 100644 arch/arm/dts/rk3588s-pinctrl.dtsi delete mode 100644 arch/arm/dts/rk3588s-rock-5a.dts delete mode 100644 arch/arm/dts/rk3588s.dtsi delete mode 100644 doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt delete mode 100644 include/dt-bindings/clock/rk3308-cru.h delete mode 100644 include/dt-bindings/clock/rk3328-cru.h delete mode 100644 include/dt-bindings/clock/rk3399-cru.h delete mode 100644 include/dt-bindings/clock/rk3568-cru.h delete mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h delete mode 100644 include/dt-bindings/power/rk3328-power.h delete mode 100644 include/dt-bindings/power/rk3399-power.h delete mode 100644 include/dt-bindings/power/rk3568-power.h delete mode 100644 include/dt-bindings/power/rk3588-power.h delete mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h -- 2.43.2

4 35

[PATCH v3] rockchip: rv1108: Convert to OF_UPSTREAM
by Fabio Estevam 07 May '24

07 May '24

Instead of using the local rv1108 devicetree copies from U-Boot, let's convert the rv1108 boards to OF_UPSTREAM so that the upstream kernel devicetrees can be used instead. Tested on a rv1108-elgin-r1 board. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- Changes since v2: - Also removed the arch/arm/dts/Makefile entries. arch/arm/dts/Makefile | 4 - arch/arm/dts/rv1108-elgin-r1.dts | 59 ---- arch/arm/dts/rv1108-evb.dts | 79 ----- arch/arm/dts/rv1108.dtsi | 581 ------------------------------- arch/arm/mach-rockchip/Kconfig | 1 + configs/elgin-rv1108_defconfig | 2 +- configs/evb-rv1108_defconfig | 2 +- 7 files changed, 3 insertions(+), 725 deletions(-) delete mode 100644 arch/arm/dts/rv1108-elgin-r1.dts delete mode 100644 arch/arm/dts/rv1108-evb.dts delete mode 100644 arch/arm/dts/rv1108.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b1c9c6222e5d..e600f9c6ed25 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -182,10 +182,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-rock-5b.dtb \ rk3588-turing-rk1.dtb -dtb-$(CONFIG_ROCKCHIP_RV1108) += \ - rv1108-elgin-r1.dtb \ - rv1108-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RV1126) += \ rv1126-edgeble-neu2-io.dtb diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts deleted file mode 100644 index 83e8b3183847..000000000000 --- a/arch/arm/dts/rv1108-elgin-r1.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Elgin RV1108 R1 board"; - compatible = "elgin,rv1108-elgin", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&emmc { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer_pullup>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&pinctrl { - uart2m0 { - uart2m0_xfer_pullup: uart2m0-xfer-pullup { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - }; -}; diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts deleted file mode 100644 index c91776bc106e..000000000000 --- a/arch/arm/dts/rv1108-evb.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RV1108 Evaluation board"; - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&gmac { - status = "okay"; - clock_in_out = <0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; -}; - -&saradc { - status = "okay"; -}; - -&sfc { - status = "okay"; - flash@0 { - compatible = "gd25q256","jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <96000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi deleted file mode 100644 index 215d88522587..000000000000 --- a/arch/arm/dts/rv1108.dtsi +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/rv1108-cru.h> -#include <dt-bindings/pinctrl/rockchip.h> -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &sfc; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; - reg = <0x10300000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rv1108-usb2phy"; - reg = <0x100 0x0c>; - clocks = <&cru SCLK_USBPHY>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usbphy"; - rockchip,usbgrf = <&usbgrf>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-mux"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - saradc: saradc@1038c000 { - compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; - reg = <0x1038c000 0x100>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clock-frequency = <1000000>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rv1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - usbgrf: syscon@202a0000 { - compatible = "rockchip,rv1108-usbgrf", "syscon"; - reg = <0x202a0000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - usb_host_ehci: usb@30140000 { - compatible = "generic-ehci"; - reg = <0x30140000 0x20000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usb_host_ohci: usb@30160000 { - compatible = "generic-ohci"; - reg = <0x30160000 0x20000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usb20_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30180000 0x40000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - sfc: sfc@301c0000 { - compatible = "rockchip,sfc"; - reg = <0x301c0000 0x200>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rv1108-gmac"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - max-speed = <100>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sfc { - sfc_pins: sfc-pins { - rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart01rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4f22d9bde9f9..b4a10be00249 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -343,6 +343,7 @@ config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A imply ROCKCHIP_COMMON_BOARD + imply OF_UPSTREAM help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 446c9c9b7aca..140429f84d29 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-elgin-r1" CONFIG_ROCKCHIP_RV1108=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_TARGET_ELGIN_RV1108=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 1c62149a9b57..afc0ce4a0929 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -5,7 +5,7 @@ CONFIG_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-evb" CONFIG_ROCKCHIP_RV1108=y CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 -- 2.34.1

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[PATCH v3] configs: rk3588-turing-rk1: disable SPI flash by default
by Sam Edwards 07 May '24

07 May '24

While the Turing RK1 board has a pad on the PCB for SPI flash, it is not populated at the factory: supporting SPI flash boot is a user modification, not an out-of-the-box feature. The defconfig for this board should therefore not be enabling the SPI flash image nor SPI support in the SPL, as it causes confusion among downstream users as to whether the SPI image needs to be distributed. Fixes: 153ac950a599 ("board: rockchip: Add the Turing RK1 SoM") Suggested-by: Florian Klink <flokli(a)flokli.de> Signed-off-by: Sam Edwards <CFSworks(a)gmail.com> Acked-by: Joshua Riek <jjriek(a)verizon.net> Reviewed-by: Jonas Karlman <jonas(a)kwiboo.se> --- Changes v1->v2 (both requested by Jonas): - Added back (i.e. made unremoved by patch) CONFIG_USB_GADGET_PRODUCT_NUM value previously automatically removed by savedefconfig. - Also disable SPI/SFC driver entirely until SPI/SFC lands in the DT (if ever). Changes v2->v3: - Rebased onto latest master for clean apply --- configs/turing-rk1-rk3588_defconfig | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 038b14769e..39ef05477a 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -3,17 +3,12 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1" CONFIG_ROCKCHIP_RK3588=y -CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_TURINGRK1_RK3588=y CONFIG_DEBUG_UART_BASE=0xFEBC0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_PCI=y CONFIG_DEBUG_UART=y @@ -29,8 +24,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -64,11 +57,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_SF_DEFAULT_BUS=5 -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_XMC=y -CONFIG_SPI_FLASH_XTX=y +# CONFIG_SPI_FLASH is not set CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y @@ -84,7 +73,6 @@ CONFIG_SPL_RAM=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y -CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -- 2.43.2

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[PATCH] clk: rockchip: rk3328: Add SCLK_USB3OTG_REF support
by Jonas Karlman 07 May '24

07 May '24

The SCLK_USB3OTG_REF clocks is used as reference clock for USB3 block. Add simple support to get rate of SCLK_USB3OTG_REF clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- This has been runtime tested on a Rock64 and NanoPi R2S Plus. --- drivers/clk/rockchip/clk_rk3328.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 87075ec71340..314b903eaa03 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -706,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case PCLK_HDMIPHY: rate = rk3328_hdmiphy_get_clk(priv->cru); break; + case SCLK_USB3OTG_REF: + rate = OSC_HZ; + break; default: return -ENOENT; } @@ -780,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case PCLK_DDR: case ACLK_GMAC: case PCLK_GMAC: + case SCLK_USB3OTG_REF: case SCLK_USB3OTG_SUSPEND: case USB480M: return 0; -- 2.43.2

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[PATCH] rockchip: rk3328: Add missing bootph-some-ram props
by Jonas Karlman 07 May '24

07 May '24

Add bootph-some-ram props to pinctrl nodes related to eMMC, SD-card and SPI flash to match e.g. RK3308 and RK3399. Also adjust bootph props for sdio_vcc_pin, pinctrl and uart2m1_xfer. Fixes: 1e21f5693045 ("rockchip: rk3328: Fix loading FIT from SD-card when booting from eMMC") Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- This has been runtime tested on a Rock64 and NanoPi R2S Plus. The uart2m1_xfer change help speed up boot by around 100 ms. --- arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 2 +- .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 7 ++++--- .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 7 ++++--- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 7 ++++--- arch/arm/dts/rk3328-u-boot.dtsi | 20 +++++++++++++++---- 5 files changed, 29 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 4fa170eeaf8d..d8c79600b659 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -12,7 +12,7 @@ }; &sdio_vcc_pin { - bootph-all; + bootph-pre-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index 0a9423cd9c7e..b50c1332b836 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -8,9 +8,6 @@ #include "rk3328-sdram-lpddr3-666.dtsi" &spi0 { - bootph-pre-ram; - bootph-some-ram; - flash@0 { bootph-pre-ram; bootph-some-ram; @@ -19,18 +16,22 @@ &spi0m2_clk { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_cs0 { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_rx { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_tx { bootph-pre-ram; + bootph-some-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 1096821fc5d3..8ae003bbefd1 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -8,9 +8,6 @@ #include "rk3328-sdram-ddr4-666.dtsi" &spi0 { - bootph-pre-ram; - bootph-some-ram; - flash@0 { bootph-pre-ram; bootph-some-ram; @@ -19,18 +16,22 @@ &spi0m2_clk { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_cs0 { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_rx { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_tx { bootph-pre-ram; + bootph-some-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 551cff6f24f6..22f128090f84 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -30,9 +30,6 @@ }; &spi0 { - bootph-pre-ram; - bootph-some-ram; - flash@0 { bootph-pre-ram; bootph-some-ram; @@ -41,18 +38,22 @@ &spi0m2_clk { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_cs0 { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_rx { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_tx { bootph-pre-ram; + bootph-some-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index d3608bd0e2b2..0135bc08d491 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -17,7 +17,6 @@ }; dmc: dmc { - bootph-all; compatible = "rockchip,rk3328-dmc"; reg = <0x0 0xff400000 0x0 0x1000 0x0 0xff780000 0x0 0x3000 @@ -25,6 +24,7 @@ 0x0 0xff440000 0x0 0x1000 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; + bootph-all; }; }; @@ -42,14 +42,17 @@ &emmc_bus8 { bootph-pre-ram; + bootph-some-ram; }; &emmc_clk { bootph-pre-ram; + bootph-some-ram; }; &emmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &gpio0 { @@ -66,10 +69,12 @@ &pcfg_pull_none_8ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_none_12ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up { @@ -78,19 +83,21 @@ &pcfg_pull_up_4ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up_8ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up_12ma { bootph-pre-ram; + bootph-some-ram; }; &pinctrl { - bootph-pre-ram; - bootph-some-ram; + bootph-all; }; &sdmmc { @@ -103,18 +110,22 @@ &sdmmc0_bus4 { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_cmd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_dectn { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0m1_pin { @@ -127,7 +138,8 @@ }; &uart2m1_xfer { - bootph-all; + bootph-pre-sram; + bootph-pre-ram; }; &vop { -- 2.43.2

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[PATCH 0/4] board: starfive: add Milk-V Mars CM support
by Heinrich Schuchardt 07 May '24

07 May '24

With this series the Milk-V Mars CM board can be booted. NVMe, SD-card, Ethernet, UART are working but not USB. The first series Milk-V Mars CM Lite board (the version without eMMC) uses incorrect series numbers indicating eMMC presence. For these CONFIG_STARFIVE_NO_EMMC=y must be set to indicate that eMMC is not present. Thanks to E. Shattow for all the helpful discussions. He figured out what needed to be patched in the device-tree. Heinrich Schuchardt (4): board: starfive: function to read eMMC size board: add support for MARS CM SD doc: Milk-V Mars CM and Milk-V Mars CM Lite configs: visionfive2: enable SPL_YMODEM_SUPPORT arch/riscv/include/asm/arch-jh7110/eeprom.h | 7 + board/starfive/visionfive2/Kconfig | 9 ++ board/starfive/visionfive2/spl.c | 27 +++- .../visionfive2/starfive_visionfive2.c | 11 +- .../visionfive2/visionfive2-i2c-eeprom.c | 18 +++ configs/starfive_visionfive2_defconfig | 1 + doc/board/starfive/index.rst | 1 + doc/board/starfive/milk-v_mars_cm.rst | 125 ++++++++++++++++++ 8 files changed, 197 insertions(+), 2 deletions(-) create mode 100644 doc/board/starfive/milk-v_mars_cm.rst -- 2.43.0

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