December 2024 - U-Boot

[PATCH 0/1] doc: fix the "sb" command name
by Olivier L'Heureux 05 Dec '24

05 Dec '24

Hello! I have found a trivial typo in U-Boot's documentation: the "sb" command was documented and indexed as "sbi". Patch follows. Regards, Olivier Olivier L'Heureux (1): doc: sandbox: Fix the "sb" command name doc/usage/cmd/sb.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) base-commit: c498b6cace9e0de45ea12146312f5a6f43a03a9b -- 2.45.2

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[GIT PULL] Please pull u-boot-pmic master
by Jaehoon Chung 05 Dec '24

05 Dec '24

Dear Tom, Please pull u-boot-pmic master into u-boot master branch. If there is any problem, let me know, plz Best Regards, Jaehoon Chung CI: https://source.denx.de/u-boot/custodians/u-boot-pmic/-/pipelines/23718 The following changes since commit f96e5133184aac377b54bd61f8abf78710f2ee56: Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung (2024-12-03 12:37:20 -0600) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-pmic.git master for you to fetch changes up to 74cd1af1124fbe3cd16c58bc3ad9ff1f9c6ecf3e: power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind() (2024-12-05 07:31:31 +0900) ---------------------------------------------------------------- Patrice Chotard (2): power: regulator: replace some debug() by dev_dbg() power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind() drivers/power/regulator/regulator-uclass.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)

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Pull request for efi-master-05122024
by Ilias Apalodimas 05 Dec '24

05 Dec '24

Hi Tom The following changes since commit f96e5133184aac377b54bd61f8abf78710f2ee56: Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung (2024-12-03 12:37:20 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-tpm/ tags/efi-master-05122024 for you to fetch changes up to 1d9aa4a283daa1e609130b5457c9857d62f1d1cb: lmb: Fix the allocation of overlapping memory areas with !LMB_NONE (2024-12-05 09:01:44 +0200) The lmb patches are soaking in the mailing list for more than a week and unfortunately haven't been reviewed. All the our sefltests pass though and the SCT is fixed so hopefully I haven't missed anything. The change should be harmless apart from some extra delay when someone is trying to allocate an already allocate area with identical flags. The CI at https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/23719 looks fine. Please pull! /Ilias ---------------------------------------------------------------- Two fixes for the EFI subsystem coming via the TPM tree as agreed by Heinrich The LMB patch fixes a failure in SystemReady testing. Nothing bad happens without the patch in the device operation, but the return values are wrong and SCT tests fail for MemoryAllocationServicesTest category. The second is a shielding the device against mistakes in the definition of struct members needed by the capsule update mechanism. Instead of crashing, print a human readable message of what's wrong. ---------------------------------------------------------------- Ilias Apalodimas (2): efi_loader: Check for a valid fw_name before auto generating GUIDs lmb: Fix the allocation of overlapping memory areas with !LMB_NONE lib/efi_loader/efi_firmware.c | 4 ++++ lib/lmb.c | 9 --------- test/lib/lmb.c | 22 +++++++++++++++++++++- 3 files changed, 25 insertions(+), 10 deletions(-)

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[PATCH v2] arm64: zynqmp: Update the usb5744 hub node as per binding
by Venkatesh Yadav Abbarapu 05 Dec '24

05 Dec '24

Updating the usb5744 hub node as per the latest upstream DT binding https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ tree/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml?h=v6.8.8 Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> Acked-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: - Updated the hub node for KD board. - Removed the #if code. --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 37 +++++++++----- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 67 ++++++++++++++++++------- arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 68 ++++++++++++++++++-------- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 24 ++++++--- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 33 +++++++++---- 5 files changed, 162 insertions(+), 67 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 4de29d5d3f..d56e863ce1 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -80,7 +80,10 @@ "", ""; }; - /* usb5744@2d */ + hub: usb-hub@2d { /* u36 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* USB 3.0 */ @@ -99,18 +102,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u36 */ - i2c-bus = <&i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u41 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -118,6 +109,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &gem1 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 6349a0e108..9d0c0c2885 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -105,11 +105,19 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; usbhub_i2c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* Bus 2/3 are not connected */ }; @@ -145,18 +153,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u43 */ - i2c-bus = <&usbhub_i2c0>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u38 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -164,6 +160,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &usb1 { /* mio64 - mio75 */ @@ -174,13 +190,6 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub1: usb-hub { /* u84 */ - i2c-bus = <&usbhub_i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_1 { @@ -188,6 +197,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &gem0 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index b0d737d3ca..0d915d496c 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -117,11 +117,19 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; usbhub_i2c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* Bus 2/3 are not connected */ }; @@ -165,18 +173,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u43 */ - i2c-bus = <&usbhub_i2c0>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u38 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -184,6 +180,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &usb1 { /* mio64 - mio75 */ @@ -194,14 +210,6 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - -#if 0 - usbhub1: usb-hub { /* u84 */ - i2c-bus = <&usbhub_i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_1 { @@ -209,6 +217,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &gem0 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 561b546e37..a98a888d13 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -129,12 +129,6 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; -#if 0 - usbhub: usb5744 { /* u43 */ - compatible = "microchip,usb5744"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -142,6 +136,24 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 64683e0ccb..7490efea98 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -92,7 +92,10 @@ label = "ina260-u14"; reg = <0x40>; }; - /* u43 - 0x2d - USB hub */ + hub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -131,14 +134,6 @@ phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usb5744: usb-hub { /* u43 */ - status = "okay"; - compatible = "microchip,usb5744"; - i2c-bus = <&i2c1>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -146,6 +141,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ -- 2.34.1

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[PATCH] arm64: zynqmp: Sync with v6.12 kernel
by Michal Simek 05 Dec '24

05 Dec '24

Sync zynqmp* DTS files with v6.12 Linux kernel. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Hope that we get soon to be able to enable OF_UPSTREAM instead. --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 ++++++++++ arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 1 + arch/arm/dts/zynqmp-zcu1275-revA.dts | 3 +- arch/arm/dts/zynqmp.dtsi | 44 +++++++++++++++++++++++----- 6 files changed, 57 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index dd4569e7bd95..60d1b1acf9a0 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -70,6 +70,22 @@ clocks = <&zynqmp_clk ACPU>; }; +&cpu0_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu1_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu2_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu3_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 8c43ade94053..620f5185cc46 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek(a)amd.com> */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index 719a4e49b574..b804abe89d1d 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek(a)amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 3132fa533b8e..dd63d22f45e7 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -960,6 +960,7 @@ &pcie { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; }; &psgtr { diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 095c972f1322..b75b2a796eb3 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -15,8 +15,7 @@ / { model = "ZynqMP ZCU1275 RevA"; - compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", - "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6a29f6101534..70ca5e6379fc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -168,8 +168,8 @@ bootph-all; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; + pmu { + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, @@ -441,6 +441,34 @@ }; }; + cpu0_debug: debug@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfec10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu1_debug: debug@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu2_debug: debug@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfee10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu3_debug: debug@fef10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfef10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; @@ -885,7 +913,6 @@ power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ - /* dma-coherent; */ }; sdhci0: mmc@ff160000 { @@ -1065,9 +1092,9 @@ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; - clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1097,9 +1124,9 @@ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; - clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1176,11 +1203,14 @@ "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; - dma-names = "vid0", "vid1", "vid2", "gfx0"; + dma-names = "vid0", "vid1", "vid2", "gfx0", + "aud0", "aud1"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, - <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>; ports { #address-cells = <1>; -- 2.43.0

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[PATCH] efi_loader: Check for a valid fw_name before auto generating GUIDs
by Ilias Apalodimas 05 Dec '24

05 Dec '24

The gen_v5_guid() is a void and does no error checking with pointers being available etc. Instead it expects all things to be in place to generate GUIDs. If a board capsule definition is buggy and does not define the firmware names when enabling capsule updates, the board will crash trying to bring up the EFI subsystem. Check for a valid firmware name before generating GUIDs. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- lib/efi_loader/efi_firmware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 6650c2b8071d..112775daf4c3 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -281,6 +281,10 @@ static efi_status_t efi_gen_capsule_guids(void) } for (i = 0; i < update_info.num_images; i++) { + if (!fw_array[i].fw_name) { + log_err("fw_name is not defined. Not generating capsule GUIDs\n"); + return EFI_INVALID_PARAMETER; + } gen_v5_guid(&namespace, &fw_array[i].image_type_id, compatible, strlen(compatible), - 2.45.2

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[PATCH] board: st: stm32mp1: Clean env_get_location()
by Patrice Chotard 05 Dec '24

05 Dec '24

ENV_IS_IN_EXT4 flag is no more used in any STM32 defconfig, remove the related code. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- board/st/stm32mp1/stm32mp1.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index d5e5e776d2a..15fb9e4b062 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -751,8 +751,6 @@ enum env_location env_get_location(enum env_operation op, int prio) case BOOT_FLASH_EMMC: if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) return ENVL_MMC; - else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) - return ENVL_EXT4; else return ENVL_NOWHERE; -- 2.25.1

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[PATCH v2] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes
by Venkatesh Yadav Abbarapu 05 Dec '24

05 Dec '24

Add SPI_NOR_OCTAL_DTR_READ flags to micron flashes mt35xu01g and mt35xu02g. Also move them under CONFIG_SPI_FLASH_MT35XU config, so that in driver mt35xu512aba_fixups will be applied. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- Changes in v2: - Add the OCTAL_DTR_READ flags for mt35xu01g and mt35xu02g. - Removed the return after nor->fixups. --- drivers/mtd/spi/spi-nor-core.c | 5 ++++- drivers/mtd/spi/spi-nor-ids.c | 6 ++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ec841fb13bd..700593f7739 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4404,7 +4404,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) #endif #ifdef CONFIG_SPI_FLASH_MT35XU - if (!strcmp(nor->info->name, "mt35xu512aba")) + if (!strcmp(nor->info->name, "mt35xu512aba") || + !strcmp(nor->info->name, "mt35xl512aba") || + !strcmp(nor->info->name, "mt35xu01g") || + !strcmp(nor->info->name, "mt35xu02g")) nor->fixups = &mt35xu512aba_fixups; #endif diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 91ae49c9484..9a69e210eb4 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -359,9 +359,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, + { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ - { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, - { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ /* Spansion/Cypress -- single (large) sector size only, at least -- 2.34.1

3 2

[PATCH v2 0/2] AM62A DWC3: Add support for USB DFU boot in OTG mode
by Siddharth Vadapalli 04 Dec '24

04 Dec '24

Hello, This series adds support for USB DFU boot on TI's AM62A SoC which has two instances of DWC3 USB Controllers namely USB0 and USB1. The USB0 instance of the USB Controller supports USB DFU boot: ROM => tiboot3.bin => tispl.bin => u-boot.img USB DFU Boot requires the USB Controller to be configured for Gadget mode of operation. Since the USB0 instance of the DWC3 USB Controller supports both Host and Gadget modes of operation via the Type-C interface on the AM62A7-SK board, the device-tree specifies the "dr_mode" as "OTG". The function dwc3_generic_probe() is invoked by either of: 1. dwc3_generic_peripheral_probe() 2. dwc3_generic_host_probe() on the basis of the command executed by the user for either device or host mode of operation respectively. Currently, dwc3_generic_probe() sets the mode based on the device-tree rather than setting it on the basis of the caller. While this might be correct when the mode is "host" or "peripheral" in the device-tree, it is wrong when the mode is "otg" in the device-tree. It is wrong because of two reasons: 1. There is no OTG state machine in U-Boot. Hence the role will never switch to the correct one eventually among host or peripheral. 2. dr_mode = "otg" results in the "PRTCAPDIR" field of the "GCTL" register of the USB Controller being set to 11b. According to the datasheet of the Designware USB Dual Role Controller, "PRTCAPDIR" should never be set to any value other than 01b (Host) and 10b (Device). Quoting the datasheet: "Programming this field with random data causes the controller to keep toggling between the host mode and the device mode." Therefore, in order to avoid programming 11b in "PRTCAPDIR", and, given that the caller specifies the intended role, rather than simply using the "dr_mode" property to set the role, set the role on the basis of the caller (intended role) and the device-tree (platform support). This could be extended further to utilize the USB ID pin to determine the expected role, but that can be implemented as an incremental feature. v1: https://patchwork.ozlabs.org/project/uboot/list/?series=434253&state=%2A&ar… Changes since v1: - Rebased series on commit acab6e78aca common: relocate fdt_blob in global_data for FDTSRC_EMBED case of the master branch of U-Boot. - Based on the feedback received on the v1 series, the device-tree specified role is also taken into account in dwc3_generic_probe(), in addition to the caller of dwc3_generic_probe(). In addition to the patches in this series, the following device-tree changes will be required to test USB DFU on AM62A (bootph-all property to be added to ensure that USB Controller is present at all stages for DFU Boot): https://gist.github.com/Siddharth-Vadapalli-at-TI/53ba02cb0ff4a09c47e920d08… The above device-tree changes will be made to the Linux device-tree, which shall ensure that the same shall be a part of U-Boot device-tree eventually. The USB DFU config fragments for AM62x have been used for enabling USB DFU boot on AM62a as follows: R5 => am62ax_evm_r5_defconfig + am62x_r5_usbdfu.config A53 => am62ax_evm_a53_defconfig + am62x_a53_usbdfu.config Logs validating USB DFU boot with this series on AM62A7-SK: https://gist.github.com/Siddharth-Vadapalli-at-TI/13f9a539ef3297ab2822bc1bc… Regards, Siddharth. Siddharth Vadapalli (2): usb: dwc3-generic: set "mode" based on caller of dwc3_generic_probe() board: ti: am62ax: env: include environment for DFU board/ti/am62ax/am62ax.env | 1 + drivers/usb/dwc3/dwc3-generic.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) -- 2.43.0

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[PATCH v1] gpio: npcm: Add persist feature to sgpio module
by Jim Liu 04 Dec '24

04 Dec '24

Base on GPIO hog to support sgpio persist enable feature. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/gpio/npcm_sgpio.c | 152 +++++++++++++++++++++++++++++++++----- 1 file changed, 135 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/npcm_sgpio.c b/drivers/gpio/npcm_sgpio.c index 6d73287c0a..539bf3e133 100644 --- a/drivers/gpio/npcm_sgpio.c +++ b/drivers/gpio/npcm_sgpio.c @@ -3,32 +3,49 @@ * Copyright (c) 2024 Nuvoton Technology Corp. */ +#include <common.h> #include <dm.h> +#include <regmap.h> +#include <syscon.h> #include <asm/gpio.h> +#include <linux/err.h> #include <linux/io.h> +#include <asm/arch/rst.h> #define MAX_NR_HW_SGPIO 64 -#define NPCM_CLK_MHZ 8000000 +#define NPCM_SIOX1 24 +#define NPCM_SIOX2 25 -#define NPCM_IOXCFG1 0x2A - -#define NPCM_IOXCTS 0x28 -#define NPCM_IOXCTS_IOXIF_EN BIT(7) -#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) +#define NPCM_IOXCTS 0x28 +#define NPCM_IOXCTS_IOXIF_EN BIT(7) +#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) #define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2) +#define NPCM_IOXCFG1 0x2A #define NPCM_IOXCFG2 0x2B #define NPCM_IOXCFG2_PORT GENMASK(3, 0) #define GPIO_BANK(x) ((x) / 8) #define GPIO_BIT(x) ((x) % 8) +#define WD0RCR 0x38 +#define WD1RCR 0x3c +#define WD2RCR 0x40 +#define SWRSTC1 0x44 +#define SWRSTC2 0x48 +#define SWRSTC3 0x4c +#define TIPRSTC 0x50 +#define CORSTC 0x5c + struct npcm_sgpio_priv { void __iomem *base; + struct regmap *rst_regmap; u32 nin_sgpio; u32 nout_sgpio; u32 in_port; u32 out_port; + u8 persist[8]; + u8 siox_num; }; struct npcm_sgpio_bank { @@ -185,7 +202,13 @@ static int npcm_sgpio_get_value(struct udevice *dev, unsigned int offset) static int npcm_sgpio_set_value(struct udevice *dev, unsigned int offset, int value) { - return npcm_sgpio_direction_output(dev, offset, value); + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 check = priv->persist[GPIO_BANK(offset)]; + + if (!!(check & BIT(GPIO_BIT(offset))) == 0) + return npcm_sgpio_direction_output(dev, offset, value); + else + return -EINVAL; } static int npcm_sgpio_get_function(struct udevice *dev, unsigned int offset) @@ -213,12 +236,10 @@ static void npcm_sgpio_setup_enable(struct npcm_sgpio_priv *gpio, bool enable) iowrite8(reg, gpio->base + NPCM_IOXCTS); } -static int npcm_sgpio_init_port(struct udevice *dev) +static void npcm_sgpio_set_port(struct udevice *dev) { struct npcm_sgpio_priv *priv = dev_get_priv(dev); - u8 in_port, out_port, set_port, reg, set_clk; - - npcm_sgpio_setup_enable(priv, false); + u8 in_port, out_port; in_port = GPIO_BANK(priv->nin_sgpio); if (GPIO_BIT(priv->nin_sgpio) > 0) @@ -230,8 +251,16 @@ static int npcm_sgpio_init_port(struct udevice *dev) priv->in_port = in_port; priv->out_port = out_port; +} - set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 | (in_port & NPCM_IOXCFG2_PORT); +static int npcm_sgpio_init_port(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 set_port, reg, set_clk; + + npcm_sgpio_setup_enable(priv, false); + + set_port = (priv->out_port & NPCM_IOXCFG2_PORT) << 4 | (priv->in_port & NPCM_IOXCFG2_PORT); set_clk = 0x07; iowrite8(set_port, priv->base + NPCM_IOXCFG2); @@ -242,6 +271,61 @@ static int npcm_sgpio_init_port(struct udevice *dev) return reg == set_port ? 0 : -EINVAL; } +static void npcm_sgpio_reset_persist(struct udevice *dev, uint enable) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 num; + + if (priv->siox_num == 1) + num = NPCM_SIOX2; + else + num = NPCM_SIOX1; + + if (enable) { + regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, CORSTC, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(num), 0); + } +} + +static bool is_gpio_persist(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u32 val; + int status; + + status = npcm_get_reset_status(); + + if (status & PORST) + return false; + if (status & CORST) + regmap_read(priv->rst_regmap, CORSTC, &val); + else if (status & WD0RST) + regmap_read(priv->rst_regmap, WD0RCR, &val); + else if (status & WD1RST) + regmap_read(priv->rst_regmap, WD1RCR, &val); + else if (status & WD2RST) + regmap_read(priv->rst_regmap, WD2RCR, &val); + else if (status & SW1RST) + regmap_read(priv->rst_regmap, SWRSTC1, &val); + else if (status & SW2RST) + regmap_read(priv->rst_regmap, SWRSTC2, &val); + else if (status & SW3RST) + regmap_read(priv->rst_regmap, SWRSTC3, &val); + else if (status & TIPRST) + regmap_read(priv->rst_regmap, TIPRSTC, &val); + + if (priv->siox_num == 1) + return (val && BIT(NPCM_SIOX2)); + else + return (val && BIT(NPCM_SIOX1)); +} + static const struct dm_gpio_ops npcm_sgpio_ops = { .direction_input = npcm_sgpio_direction_input, .direction_output = npcm_sgpio_direction_output, @@ -254,23 +338,57 @@ static int npcm_sgpio_probe(struct udevice *dev) { struct npcm_sgpio_priv *priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - int rc; + int rc, i; + ofnode node; + u32 val[2]; priv->base = dev_read_addr_ptr(dev); + priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst"); + if (IS_ERR(priv->rst_regmap)) + return -EINVAL; + ofnode_read_u32(dev_ofnode(dev), "nuvoton,input-ngpios", &priv->nin_sgpio); ofnode_read_u32(dev_ofnode(dev), "nuvoton,output-ngpios", &priv->nout_sgpio); if (priv->nin_sgpio > MAX_NR_HW_SGPIO || priv->nout_sgpio > MAX_NR_HW_SGPIO) return -EINVAL; - rc = npcm_sgpio_init_port(dev); - if (rc < 0) - return rc; + if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio2@102000")) + priv->siox_num = 1; + else if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio1@101000")) + priv->siox_num = 0; + else + return -EINVAL; + npcm_sgpio_set_port(dev); uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio; uc_priv->bank_name = dev->name; - npcm_sgpio_setup_enable(priv, true); + if (is_gpio_persist(dev)) { + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (ofnode_read_bool(node, "persist-enable")) { + rc = ofnode_read_u32_array(node, "gpios", val, 2); + if (rc == 0) + priv->persist[GPIO_BANK(val[0])] = priv->persist[GPIO_BANK(val[0])] | BIT(GPIO_BIT(val[0])); + } + } + for (i = 0; i < priv->nout_sgpio; i++) + npcm_sgpio_set_value(dev, i, 0); + } else { + rc = npcm_sgpio_init_port(dev); + if (rc < 0) + return rc; + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (ofnode_read_bool(node, "persist-enable")) + npcm_sgpio_reset_persist(dev, 1); + } + + for (i = 0; i < priv->nout_sgpio; i++) + npcm_sgpio_set_value(dev, i, 0); + + npcm_sgpio_setup_enable(priv, true); + } return 0; } -- 2.34.1

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