November 2024 - U-Boot

[PATCH 0/4] Enable EFI capsule updates for PHYTEC K3 SoMs
by Wadim Egorov 14 Dec '24

14 Dec '24

This implements capsule updates for all our K3 SoMs for eMMC, OSPI NOR and uSD cards. We can use capsule updates to update the bootloader on all our supported flash devices. Wadim Egorov (4): arm: dts: k3-am625-phycore-som-binman: Provide capsule nodes arm: dts: k3-am642-phycore-som-binman: Provide capsule nodes board: phytec: k3: Add EFI capsule update support configs: phycore_am6*_a53_defconfig: Enable capsule update arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 39 +++++++++ arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 38 +++++++++ board/phytec/common/k3/board.c | 80 +++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 10 +++ configs/phycore_am64x_a53_defconfig | 8 ++ include/configs/phycore_am62x.h | 4 + include/configs/phycore_am64x.h | 4 + 7 files changed, 183 insertions(+) -- 2.34.1

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[PATCH 0/2] AM62A DWC3: Add support for USB DFU boot in OTG mode
by Siddharth Vadapalli 14 Dec '24

14 Dec '24

Hello, This series adds support for USB DFU boot on TI's AM62A SoC which has two instances of DWC3 USB Controllers namely USB0 and USB1. The USB0 instance of the USB Controller supports USB DFU boot: ROM => tiboot3.bin => tispl.bin => u-boot.img USB DFU Boot requires the USB Controller to be configured for Gadget mode of operation. Since the USB0 instance of the DWC3 USB Controller supports both Host and Gadget modes of operation via the Type-C interface on the AM62A7-SK board, the device-tree specifies the "dr_mode" as "OTG". However, there is currently no support for dynamically switching the "mode" from Host to Gadget and vice-versa with the help of a state-machine. The OTG mode is treated as a separate mode in itself rather than being treated as an intermediate stage before assuming the Host/Gadget mode. Due to this, USB DFU boot via the Type-C interface doesn't work as the USB Controller hasn't been appropriately configured for Device/Gadget mode of operation. One option is to change the device-tree to specify "dr_mode" as "peripheral" and force the controller to assume the Device role. This will imply that the U-Boot device-tree for AM62A diverges from its Linux counterpart. Therefore, with the intent of keeping the device-tree uniform across Linux and U-Boot, and at the same time, in order to enable USB DFU boot in "OTG" mode with the DWC3 Controller, the first patch in this series sets the "mode" on the basis of the caller function, rather than using the "dr_mode" property in the device-tree. There are only two callers of "dwc3_generic_probe()", each of which clearly specify the expected mode of configuration. This will enable both Host and Device mode of operation based on the command executed by the user, thereby truly supporting "OTG" functionality when the USB Controller supports it. The second patch in this series adds USB DFU environment for AM62A, enabling USB DFU Boot and USB DFU flash on AM62A. In addition to the patches in this series, the following device-tree changes will be required to test USB DFU on AM62A (bootph-all property to be added to ensure that USB Controller is present at all stages for DFU Boot): https://gist.github.com/Siddharth-Vadapalli-at-TI/53ba02cb0ff4a09c47e920d08… The above device-tree changes will be made to the Linux device-tree, which shall ensure that the same shall be a part of U-Boot device-tree eventually. The USB DFU config fragments for AM62x have been used for enabling USB DFU boot on AM62a as follows: R5 => am62ax_evm_r5_defconfig + am62x_r5_usbdfu.config A53 => am62ax_evm_a53_defconfig + am62x_a53_usbdfu.config Logs validating USB DFU boot with this series: https://gist.github.com/Siddharth-Vadapalli-at-TI/daa71da1b0e478a51afea4260… Series is based on commit 3073246d1be Prepare v2025.01-rc3 of the master branch of U-Boot. Regards, Siddharth. Siddharth Vadapalli (2): usb: dwc3-generic: set "mode" based on caller of dwc3_generic_probe() board: ti: am62ax: env: include environment for DFU board/ti/am62ax/am62ax.env | 1 + drivers/usb/dwc3/dwc3-generic.c | 9 +++++---- 2 files changed, 6 insertions(+), 4 deletions(-) -- 2.43.0

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[PATCH 0/3] J721S2: Enable ESMs and related PMIC
by Udit Kumar 14 Dec '24

14 Dec '24

This enables the ESMs and the associated PMIC. Programming these bits is a requirement to make the watchdog actually reset the board. Logs WDT reset J721S2 https://gist.github.com/uditkumarti/93cfe863d1f3fe3abb82b1821105f274#file-j… AM68 boot (this does not support WDT) https://gist.github.com/uditkumarti/93cfe863d1f3fe3abb82b1821105f274#file-a… Keerthy (1): board: ti: j721s2: Initialize the ESM & PMIC ESM Manorit Chawdhry (2): arch: arm: dts: k3-j721s2-r5-common-proc-board: Add esm node configs: j721s2_evm_r5_defconfig: Add ESM configs .../dts/k3-j721s2-r5-common-proc-board.dts | 4 ++++ board/ti/j721s2/evm.c | 23 +++++++++++++++++++ configs/am68_sk_r5_defconfig | 2 ++ configs/j721s2_evm_r5_defconfig | 2 ++ 4 files changed, 31 insertions(+) -- 2.34.1

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[PATCH v2 0/4] Add QOS support for J722S and AM62P
by Jayesh Choudhary 14 Dec '24

14 Dec '24

Add QOS support for DSS in TI K3 SoC to route the DSS traffic through RT queue by setting orderID as 15: - J722S - AM62P Changelog v1->v2: - Rebased on the tip of next branch - Corrected the commit message in patch 2/4 v1: <https://lore.kernel.org/all/20241106063930.59870-1-j-choudhary@ti.com/> Jayesh Choudhary (4): arm: mach-k3: j722s: Add QoS support for DSS arm: mach-k3: am62p: Add QoS support for DSS configs: j722s_evm_r5_defconfig: Enable CONFIG_K3_QOS configs: am62p_evm_r5_defconfig: Enable CONFIG_K3_QOS arch/arm/mach-k3/am62px/am62p5_init.c | 2 + arch/arm/mach-k3/j722s/j722s_init.c | 1 + arch/arm/mach-k3/r5/am62px/Makefile | 1 + arch/arm/mach-k3/r5/am62px/am62p_qos.h | 42 ++++++++++++++ arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c | 58 ++++++++++++++++++++ arch/arm/mach-k3/r5/j722s/Makefile | 1 + arch/arm/mach-k3/r5/j722s/j722s_qos.h | 51 +++++++++++++++++ arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c | 58 ++++++++++++++++++++ configs/am62px_evm_r5_defconfig | 1 + configs/j722s_evm_r5_defconfig | 1 + 10 files changed, 216 insertions(+) create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos.h create mode 100644 arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos.h create mode 100644 arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c -- 2.34.1

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[PATCH v4 0/4] Select CONFIG_64BIT for sandbox64 and x86_64
by Andrew Goodbody 13 Dec '24

13 Dec '24

Picking up a series from Dan Carpenter and applying requested changes for v2. I had previously set CONFIG_64BIT for arm64. This patchset does the same thing for sandbox and x86_64. (Mips and riscv were already doing it). This CONFIG option is used in the Makefile to determine if it's a 32 or 64 bit system for the CHECKER. Makefile 1052 # the checker needs the correct machine size 1053 CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32) Changes in v4: - Add help text to describe new symbol CONFIG_SPL_64BIT - Split the statement in bloblist.c to be more readable Changes in v3: Added a new patch 1/4 to make fixes to the source needed by the sandbox patch 2/4. Updated 3/4 to account for x86 being built with a 64 bit U-Boot proper but a 32 bit SPL. Added another patch 4/4 to fix an incorrect use of CONFIG_PHYS_64BIT which should be CONFIG_64BIT at the request of Tom Rini. Changes in v2: Resubmitted by Andrew Goodbody with changes requested by reviewer Andrew Goodbody (4): sandbox: Correct guard around readq/writeq sandbox: select CONFIG_64BIT for sandbox x86: select CONFIG_64BIT for X86_64 test: lib: Use CONFIG_64BIT to detect 64 bit compile arch/Kconfig | 8 ++++++++ arch/arm/Kconfig | 1 + arch/mips/Kconfig | 4 ++++ arch/riscv/Kconfig | 1 + arch/sandbox/Kconfig | 2 ++ arch/sandbox/include/asm/io.h | 4 ++-- arch/x86/Kconfig | 1 + common/bloblist.c | 11 +++++++---- include/limits.h | 3 ++- test/lib/str.c | 8 ++++---- 10 files changed, 32 insertions(+), 11 deletions(-) -- 2.39.5

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[PATCH] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
by Sam Protsenko 13 Dec '24

13 Dec '24

Sometimes clocks provided to a consumer might not have .set_rate operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag set. In that case it's usually possible to find a parent up the tree which is capable of setting the rate (div, pll, etc). Implement a simple lookup procedure for such cases, to traverse the clock tree until .set_rate capable parent is found, and use that parent to actually change the rate. The search will stop once the first .set_rate capable clock is found, which is usually enough to handle most cases. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- drivers/clk/clk-uclass.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc4841..755f05f34669 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -571,8 +571,20 @@ ulong clk_set_rate(struct clk *clk, ulong rate) return 0; ops = clk_dev_ops(clk->dev); - if (!ops->set_rate) - return -ENOSYS; + /* Try to find parents which can set rate */ + while (!ops->set_rate) { + struct clk *parent; + + if (!(clk->flags & CLK_SET_RATE_PARENT)) + return -ENOSYS; + + parent = clk_get_parent(clk); + if (IS_ERR_OR_NULL(parent) || !clk_valid(parent)) + return -ENODEV; + + clk = parent; + ops = clk_dev_ops(clk->dev); + } /* get private clock struct used for cache */ clk_get_priv(clk, &clkp); -- 2.39.2

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[PATCH v4 0/8] Inline ECC Series
by Santhosh Kumar K 12 Dec '24

12 Dec '24

Hello, This series is to: Add support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX, J721S2 and J784S4 devices. (1/8) Enable ECC priming with BIST engine (2/8) Add a function to store base address and size of RAM's banks in a 64-bit device private data (3/8) Setup the ECC region start and range (4/8) Enable ECC 1-bit error, 2-bit error and multiple-bit error interrupts (5/8) Add CONFIG_K3_INLINE_ECC (6/8) Set NR_DRAM_BANKS to 2 (7/8) Pull Redundant DDR functions to a common location and Fixup DDR size when ECC is enabled (8/8) Add ss_cfg reg entry Changes since v3: Pull redundant DDR functions to arch/arm/mach-k3/* v3: https://lore.kernel.org/all/20240523050430.455201-1-s-k6@ti.com/ Changes since v2: Removed 'default n' in Kconfig as that is default setting v2: https://lore.kernel.org/u-boot/20240510084707.1903133-1-s-k6@ti.com/ Changes since v1: Add support for J7* devices. v1: https://lore.kernel.org/u-boot/20240131060213.1128024-1-s-k6@ti.com/ Test Results: https://gist.github.com/santhosh21/25937355aa2c134a64fa76480ac6a4a2 Thanks and Regards, Santhosh. Georgi Vlaev (1): ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming Neha Malcom Francis (2): drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 Santhosh Kumar K (5): ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue ram: k3-ddrss: Setup ECC region start and range ram: k3-ddrss: Enable ECC interrupts board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled arm: dts: k3-*-ddr: Add ss_cfg reg entry arch/arm/dts/k3-am62a-ddr.dtsi | 7 +- arch/arm/dts/k3-j721s2-ddr.dtsi | 12 +- arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++- arch/arm/mach-k3/Makefile | 2 +- arch/arm/mach-k3/include/mach/k3-ddr.h | 15 ++ arch/arm/mach-k3/k3-ddr.c | 88 ++++++++++ board/ti/am62ax/evm.c | 17 +- board/ti/am62px/evm.c | 17 +- board/ti/am62x/evm.c | 62 +------ board/ti/am64x/evm.c | 73 +-------- board/ti/am65x/evm.c | 29 +--- board/ti/j721e/evm.c | 29 +--- board/ti/j721s2/evm.c | 35 ++-- board/ti/j784s4/evm.c | 17 +- configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + drivers/ram/Kconfig | 10 ++ drivers/ram/k3-ddrss/k3-ddrss.c | 214 +++++++++++++++++++++---- 20 files changed, 387 insertions(+), 268 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/k3-ddr.h create mode 100644 arch/arm/mach-k3/k3-ddr.c -- 2.34.1

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[PATCH] efi_loader: fix pe reloc pointer overrun
by Aleksandar Gerasimovski 12 Dec '24

12 Dec '24

The fix provided by 997fc12ec91 is actually introducing a buffer overrun, and the overrun is effective if the memory after the reloc section is not zeroed. Probably that's why this bug is not always noticeable. The problem is that 8-bytes 'rel' pointer can be 4-bytes aligned according to the PE Format, so the actual relocate function can take values after the reloc section. One example is the following dump from the reloc section: bce26000: 3000 0000 000c 0000 0000 0000 0000 0000 bce26010: 7c00 9340 67e0 f900 1c00 0ea1 a400 0f20 This section has two relocations at offset bce26008 and bce2600a, however the given size (rel_size) for this relocation is 16-bytes and this is coming form the efi image Misc.VirtualSize, so in this case the 'reloc' pointer ends at affset bce2600c and is taken as valid and this is where the overflow is. In our system we see this problem when we are starting the Boot Guard efi image. This patch is fixing the overrun while preserving the fix done by 997fc12ec91. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)belden.com> --- lib/efi_loader/efi_image_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 0ddf69a091..04075d83cb 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -121,7 +121,7 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, return EFI_SUCCESS; end = (const IMAGE_BASE_RELOCATION *)((const char *)rel + rel_size); - while (rel < end && rel->SizeOfBlock) { + while (rel + 1 < end && rel->SizeOfBlock) { const uint16_t *relocs = (const uint16_t *)(rel + 1); i = (rel->SizeOfBlock - sizeof(*rel)) / sizeof(uint16_t); while (i--) { -- 2.34.1 ********************************************************************** DISCLAIMER: Privileged and/or Confidential information may be contained in this message. If you are not the addressee of this message, you may not copy, use or deliver this message to anyone. In such event, you should destroy the message and kindly notify the sender by reply e-mail. It is understood that opinions or conclusions that do not relate to the official business of the company are neither given nor endorsed by the company. Thank You.

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[PATCH v4 0/2] riscv: spacemit: add support for bananapi-f3
by Huan Zhou 12 Dec '24

12 Dec '24

Banana Pi F3 board is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI computing power. 4G DDR and 16G eMMC onboard. 2x GbE Ethernet port, 4x USB 3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera. This patch introduces fundamental support for the Banana Pi F3 board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Changes in v4: - Change uart compatible in k1.dtsi in v3, cause related driver in not implemented in u-boot. - Update doc, show how to validate the patch. - Update maintainer, remove kongyang cause he lefted. - Link to v3: https://lore.kernel.org/r/20241114-pickup-bpif3-v3-0-98a45802ab79@gmail.com Changes in v3: - Add base commit - Clear redifinition warning while building in UART_IIR_ID - Change underscore to dash in bananapi*f3 - Update maintainer - link to v2 https://lore.kernel.org/u-boot/20240718043329.1500-1-seashell11234455@gmail… Changes in v2: - Change license to GPL-2.0-or-later - Add memory node for dts - Add ft_board_setup function for kernel memory init - Use default prompt - links to v1 https://lore.kernel.org/u-boot/20240714150828.736-1-seashell11234455@gmail.… Signed-off-by: Huan Zhou <pericycle.cc(a)gmail.com> Signed-off-by: Kongyang Liu <seashell11234455(a)gmail.com> --- Kongyang Liu (2): riscv: spacemit: bananapi_f3: initial support added doc: spacemit: bananapi_f3: document Banana Pi F3 board arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 459 +++++++++++++++++++++++++++++++++ board/spacemit/bananapi-f3/Kconfig | 25 ++ board/spacemit/bananapi-f3/MAINTAINERS | 6 + board/spacemit/bananapi-f3/Makefile | 5 + board/spacemit/bananapi-f3/board.c | 9 + configs/bananapi-f3_defconfig | 20 ++ doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++ doc/board/spacemit/index.rst | 8 + include/configs/bananapi-f3.h | 13 + 17 files changed, 750 insertions(+) --- base-commit: 40c45a57974bdb09fffa31dde65ddf69e5de53eb change-id: 20241112-pickup-bpif3-245ab208b9a4 Best regards, -- Huan Zhou <pericycle.cc(a)gmail.com>

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EFI File renaming
by Traut Manuel LCPF-CH 12 Dec '24

12 Dec '24

Hi, systemd-boot counting logic requires [0] to be implemented. Is anybody already working on this? If not we plan to add the functionality in fs/fs.c and fs/fat - correct? Cheers Manuel [0] https://elixir.bootlin.com/u-boot/v2025.01-rc1/source/lib/efi_loader/efi_fi…

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