November 2024 - U-Boot

[PATCH] button: gpio: handle broken controller
by Caleb Connolly 06 Dec '24

06 Dec '24

Avoid crashing U-Boot when the GPIO controller for a button is disabled or failed to probe. We also need to check the priv data for each button since even if a button fails to probe it will still be polled by the core code. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- drivers/button/button-gpio.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c index 43b82d98aeb7..31b85c8150e8 100644 --- a/drivers/button/button-gpio.c +++ b/drivers/button/button-gpio.c @@ -19,8 +19,11 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) { struct button_gpio_priv *priv = dev_get_priv(dev); int ret; + if (!priv) + return -ENODATA; + if (!dm_gpio_is_valid(&priv->gpio)) return -EREMOTEIO; ret = dm_gpio_get_value(&priv->gpio); if (ret < 0) @@ -31,8 +34,10 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) static int button_gpio_get_code(struct udevice *dev) { struct button_gpio_priv *priv = dev_get_priv(dev); + if (!priv) + return -ENODATA; int code = priv->linux_code; if (!code) return -ENODATA; @@ -50,9 +55,9 @@ static int button_gpio_probe(struct udevice *dev) if (!uc_plat->label) return 0; ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_IN); - if (ret) + if (ret || !dm_gpio_is_valid(&priv->gpio)) return ret; ret = dev_read_u32(dev, "linux,code", &priv->linux_code); @@ -97,8 +102,10 @@ static int button_gpio_bind(struct udevice *parent) if (ret) return ret; uc_plat = dev_get_uclass_plat(dev); uc_plat->label = label; + debug("Button '%s' bound to driver '%s'\n", label, + dev->driver->name); } return 0; } -- 2.47.0

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[PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
by Garrett Giordano 06 Dec '24

06 Dec '24

Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code optional for PHYTEC K3 boards. This allows better control over which boards receive DDR timing patches, rather than compiling the code for all boards with K3_DDRSS enabled. Also enable the feature by default for PHYCORE_AM62X_R5. Signed-off-by: Garrett Giordano <ggiordano(a)phytec.com> Reviewed-by: Wadim Egorov <w.egorov(a)phytec.de> --- arch/arm/mach-k3/am62x/Kconfig | 1 + board/phytec/common/k3/Kconfig | 5 +++++ board/phytec/common/k3/Makefile | 2 +- board/phytec/phycore_am62x/Kconfig | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 board/phytec/common/k3/Kconfig diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig index 8b0cdd74f4f..81199ada3a1 100644 --- a/arch/arm/mach-k3/am62x/Kconfig +++ b/arch/arm/mach-k3/am62x/Kconfig @@ -42,6 +42,7 @@ config TARGET_PHYCORE_AM62X_R5 select SPL_RAM select K3_DDRSS select BINMAN + select PHYTEC_K3_DDR_PATCH imply SYS_K3_SPL_ATF config TARGET_VERDIN_AM62_A53 diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig new file mode 100644 index 00000000000..282f4b79742 --- /dev/null +++ b/board/phytec/common/k3/Kconfig @@ -0,0 +1,5 @@ +config PHYTEC_K3_DDR_PATCH + bool "Patch DDR timings on PHYTEC K3 SoMs" + help + Allow to override default DDR timings prior to + DDRSS driver probing. diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index 40e91a43e99..6861c70e17e 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o -obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o +obj-$(CONFIG_PHYTEC_K3_DDR_PATCH) += k3_ddrss_patch.o diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index 7c179ef0078..ecee5873c0c 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -33,6 +33,7 @@ config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" source "board/phytec/common/Kconfig" +source "board/phytec/common/k3/Kconfig" endif -- 2.25.1

2 1

[PATCH] eeprom: at24: add ST M24256E Additional Write lockable page support
by Marek Vasut 06 Dec '24

06 Dec '24

The ST M24256E behaves as a regular M24C256, except for the E variant which uses up another I2C address for Additional Write lockable page. This page is 64 Bytes long and can contain additional data. Add entry for it, so users can describe that page in DT. Note that users still have to describe the main M24C256 area separately as that is on separate I2C address from this page. Unlike M24C32-D and M24C64-D, this part is specifically ST and does not have any comparable M24* counterparts from other vendors, hence the st, vendor prefix. Furthermore, the part name is M24256E without C between the 24 and 256, this is not a typo. Finally, there is M24C256-D part, which does contain 32 Bytes long Additional Write lockable page, which is a different part and not supported by this patch. Datasheet: https://www.st.com/resource/en/datasheet/m24256e-f.pdf >From Linux kernel commit: 339cb28b9ee6 ("eeprom: at24: add ST M24256E Additional Write lockable page support") Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de --- drivers/misc/i2c_eeprom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 10f0173d805..3cb38aa28ad 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -264,6 +264,13 @@ static const struct i2c_eeprom_drv_data atmel24c256_data = { .offset_len = 2, }; +static const struct i2c_eeprom_drv_data st24256e_wlp_data = { + .size = 64, + .pagesize = 64, + .addr_offset_mask = 0, + .offset_len = 2, +}; + static const struct i2c_eeprom_drv_data atmel24c512_data = { .size = 65536, .pagesize = 64, @@ -287,6 +294,7 @@ static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "atmel,24c128", (ulong)&atmel24c128_data }, { .compatible = "atmel,24c256", (ulong)&atmel24c256_data }, { .compatible = "atmel,24c512", (ulong)&atmel24c512_data }, + { .compatible = "st,24256e-wl", (ulong)&st24256e_wlp_data }, { } }; -- 2.45.2

2 1

[PATCH 1/3] aspeed: Fix Kconfig logic on "DM_REGULATOR" and ASPEED_AST2500
by Tom Rini 06 Dec '24

06 Dec '24

It is not the case that we can only pick ASPEED_AST2500 if DM_REGULATOR is enabled, but rather choosing ASPEED_AST2500 means we must select DM_REGULATOR. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Cc: Maxim Sloyko <maxims(a)google.com> --- arch/arm/mach-aspeed/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 1e7dc10e170f..9cf60378c118 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -16,8 +16,8 @@ choice config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" - depends on DM_RESET select CPU_ARM1176 + select DM_RESET help The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. It is used as Board Management Controller on many server boards, -- 2.43.0

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[PATCH v2 0/6] imx8(m): add optee node to binman FIT image
by Yannic Moog 06 Dec '24

06 Dec '24

There have been attempts to get op-tee node integrated upstream in the past [1][2]. The challenge is on how to handle the load and entry addresses where the op-tee image should be loaded to. Different SoC families and architectures have different RAM base addresses. Further the final addresses can vary from board to board (e.g. depending on populated RAM size). This approach follows the TI k3 kconfig solution. To be able to define a sensible default for the new config option, put it in the imx8m kconfig. For other imx families, the RAM start addresses are different and thus finding a common sensible default is not possible. I do not have a working Nano board so I was not able to test imx8mn. I included usage for PHYTEC boards for examples (with documentation). [1] https://patchwork.ozlabs.org/project/uboot/patch/20230622173006.3921891-1-t… [2] https://patchwork.ozlabs.org/project/uboot/patch/ZeHDVr-Bzm935-5N@mecka.net/ --- Changes in v2 (from RFC): - Use kconfig instead of trying pure dt approach. - Add load addresses in defconfigs instead of <board>-u-boot dts. --- Yannic Moog (6): arm: imx8m: add OP-TEE node phycore-imx8mp_defconfig: add optee load address imx8mm-phygate-tauri-l_defconfig: add optee load address phycore-imx8mm_defconfig: add optee load address doc: phytec: imx8mp: add OP-TEE documentation doc: phytec: imx8mm: add OP-TEE integration instructions arch/arm/dts/imx8mm-u-boot.dtsi | 17 ++++++++++++++++- arch/arm/dts/imx8mn-u-boot.dtsi | 17 ++++++++++++++++- arch/arm/dts/imx8mp-u-boot.dtsi | 17 ++++++++++++++++- arch/arm/mach-imx/imx8m/Kconfig | 8 ++++++++ configs/imx8mm-phygate-tauri-l_defconfig | 1 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + doc/board/phytec/imx8mm-phygate-tauri-l.rst | 26 +++++++++++++++++++++++++- doc/board/phytec/phycore-imx8mm.rst | 25 ++++++++++++++++++++++++- doc/board/phytec/phycore-imx8mp.rst | 26 +++++++++++++++++++++++++- 10 files changed, 133 insertions(+), 6 deletions(-) --- base-commit: d88bcd6d247a2b5d1683e393d8c9dc0259cd29f0 change-id: 20240903-phytec_imx8m_optee-8674ef012a36 Best regards, -- Yannic Moog <y.moog(a)phytec.de>

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[PATCH 0/6] ufs: core: initial cleanup and defines sync with Linux v6.12
by Neil Armstrong 06 Dec '24

06 Dec '24

This serie fixes the build and checkpatch warnings, and does a split of the ufs.h into a separate ufshci.h which helps syndhronizing the defines from Linux v6.12. No functional changes intended, tests on hardware are welcome. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Neil Armstrong (6): ufs: core: include missing include/ufs.h ufs: core: mark unexported functions as static ufs: core: cosmetic fixups ufs: core: move ufshci defines in a separate header ufs: core: sync unipro.h with Linux v6.12 ufs: core: sync ufshci.h with Linux v6.12 drivers/ufs/ufs.c | 43 +++-- drivers/ufs/ufs.h | 335 +----------------------------------- drivers/ufs/ufshci.h | 469 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/ufs/unipro.h | 128 ++++++++------ 4 files changed, 571 insertions(+), 404 deletions(-) --- base-commit: dc1859f8d2ac3faaa5e2e1d465ec4bd8980520a5 change-id: 20241120-topic-ufs-cleanup-23671e3fc9e9 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

3 17

[PATCH v2 1/3] pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
by Paul Barker 05 Dec '24

05 Dec '24

The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V. rzg2l_pinconf_set() is extended to support the 2.5V setting, with a check to ensure this is only used on Ethernet interfaces as it is not supported on the SD & QSPI interfaces. While we're modifying rzg2l_pinconf_set(), drop the unnecessary default value for pwr_reg as it is set in every branch of the following if condition. Signed-off-by: Paul Barker <paul.barker.ct(a)bp.renesas.com> --- Changes v1->v2: - Split out of series adding RZ/G2L Ethernet support [1] [1]: https://lore.kernel.org/all/20241024152448.102-1-paul.barker.ct@bp.renesas.… drivers/pinctrl/renesas/rzg2l-pfc.c | 49 ++++++++++++++++++++--------- include/renesas/rzg2l-pfc.h | 2 ++ 2 files changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index e88ec1c18373..0098e2d52d57 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -394,18 +394,10 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, } case PIN_CONFIG_POWER_SOURCE: { - u32 pwr_reg = 0x0; + bool support_2500 = false; + u32 pwr_reg; + u32 value; - /* argument is in mV */ - if (argument != 1800 && argument != 3300) { - dev_err(dev, "Invalid mV %u\n", argument); - return -EINVAL; - } - - /* - * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be - * handled when the RZ/G2L Ethernet driver is added. - */ if (cfg & PIN_CFG_IO_VMC_SD0) { dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n", port_offset, pin, argument); @@ -418,13 +410,42 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n", port_offset, pin, argument); pwr_reg = QSPI; + } else if (cfg & PIN_CFG_IO_VMC_ETH0) { + dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = ETH_POC(0); + support_2500 = true; + } else if (cfg & PIN_CFG_IO_VMC_ETH1) { + dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = ETH_POC(1); + support_2500 = true; } else { - dev_dbg(dev, "pin power source is not selectable\n"); + dev_dbg(dev, "port off %u:%u PVDD is not selectable\n", + port_offset, pin); + return -EINVAL; + } + + /* argument is in mV */ + switch (argument) { + case 1800: + value = PVDD_1800; + break; + case 3300: + value = PVDD_3300; + break; + case 2500: + if (support_2500) { + value = PVDD_2500; + break; + } + fallthrough; + default: + dev_err(dev, "Invalid mV %u\n", argument); return -EINVAL; } - writel((argument == 1800) ? PVDD_1800 : PVDD_3300, - data->base + pwr_reg); + writel(value, data->base + pwr_reg); break; } diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index 2df17ece2a31..d1015b1d2ac1 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -77,9 +77,11 @@ #define IEN(n) (0x1800 + (n) * 8) #define PWPR 0x3014 #define SD_CH(n) (0x3000 + (n) * 4) +#define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ -- 2.43.0

2 5

[PATCH v2] net: ravb: Simplify max-speed handling in ravb_of_to_plat
by Paul Barker 05 Dec '24

05 Dec '24

We can call dev_read_u32_default() instead of calling fdt_getprop() then fdt32_to_cpu(). Signed-off-by: Paul Barker <paul.barker.ct(a)bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Changes v1->v2: - Split out of series adding RZ/G2L Ethernet support [1] - Added Marek's Reviewed-by tag [1]: https://lore.kernel.org/all/20241024152448.102-1-paul.barker.ct@bp.renesas.… drivers/net/ravb.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index f1401d2f6ed2..6393c3a7c3fe 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -657,10 +657,7 @@ int ravb_of_to_plat(struct udevice *dev) if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) return -EINVAL; - pdata->max_speed = 1000; - cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); - if (cell) - pdata->max_speed = fdt32_to_cpu(*cell); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000); sprintf(bb_miiphy_buses[0].name, dev->name); -- 2.43.0

2 3

[PATCH v2] arm64: zynqmp: Update the usb5744 hub node as per binding
by Venkatesh Yadav Abbarapu 05 Dec '24

05 Dec '24

Updating the usb5744 hub node as per the latest upstream DT binding https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ tree/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml?h=v6.8.8 Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> Acked-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: - Updated the hub node for KD board. - Removed the #if code. --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 37 +++++++++----- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 67 ++++++++++++++++++------- arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 68 ++++++++++++++++++-------- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 24 ++++++--- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 33 +++++++++---- 5 files changed, 162 insertions(+), 67 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 4de29d5d3f..d56e863ce1 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -80,7 +80,10 @@ "", ""; }; - /* usb5744@2d */ + hub: usb-hub@2d { /* u36 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* USB 3.0 */ @@ -99,18 +102,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u36 */ - i2c-bus = <&i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u41 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -118,6 +109,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &gem1 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 6349a0e108..9d0c0c2885 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -105,11 +105,19 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; usbhub_i2c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* Bus 2/3 are not connected */ }; @@ -145,18 +153,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u43 */ - i2c-bus = <&usbhub_i2c0>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u38 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -164,6 +160,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &usb1 { /* mio64 - mio75 */ @@ -174,13 +190,6 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub1: usb-hub { /* u84 */ - i2c-bus = <&usbhub_i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_1 { @@ -188,6 +197,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &gem0 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index b0d737d3ca..0d915d496c 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -117,11 +117,19 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; usbhub_i2c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* Bus 2/3 are not connected */ }; @@ -165,18 +173,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u43 */ - i2c-bus = <&usbhub_i2c0>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u38 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -184,6 +180,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &usb1 { /* mio64 - mio75 */ @@ -194,14 +210,6 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - -#if 0 - usbhub1: usb-hub { /* u84 */ - i2c-bus = <&usbhub_i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_1 { @@ -209,6 +217,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &gem0 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 561b546e37..a98a888d13 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -129,12 +129,6 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; -#if 0 - usbhub: usb5744 { /* u43 */ - compatible = "microchip,usb5744"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -142,6 +136,24 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 64683e0ccb..7490efea98 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -92,7 +92,10 @@ label = "ina260-u14"; reg = <0x40>; }; - /* u43 - 0x2d - USB hub */ + hub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -131,14 +134,6 @@ phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usb5744: usb-hub { /* u43 */ - status = "okay"; - compatible = "microchip,usb5744"; - i2c-bus = <&i2c1>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -146,6 +141,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ -- 2.34.1

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[PATCH] arm64: zynqmp: Sync with v6.12 kernel
by Michal Simek 05 Dec '24

05 Dec '24

Sync zynqmp* DTS files with v6.12 Linux kernel. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Hope that we get soon to be able to enable OF_UPSTREAM instead. --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 ++++++++++ arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 1 + arch/arm/dts/zynqmp-zcu1275-revA.dts | 3 +- arch/arm/dts/zynqmp.dtsi | 44 +++++++++++++++++++++++----- 6 files changed, 57 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index dd4569e7bd95..60d1b1acf9a0 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -70,6 +70,22 @@ clocks = <&zynqmp_clk ACPU>; }; +&cpu0_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu1_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu2_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu3_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 8c43ade94053..620f5185cc46 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek(a)amd.com> */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index 719a4e49b574..b804abe89d1d 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek(a)amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 3132fa533b8e..dd63d22f45e7 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -960,6 +960,7 @@ &pcie { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; }; &psgtr { diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 095c972f1322..b75b2a796eb3 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -15,8 +15,7 @@ / { model = "ZynqMP ZCU1275 RevA"; - compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", - "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6a29f6101534..70ca5e6379fc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -168,8 +168,8 @@ bootph-all; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; + pmu { + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, @@ -441,6 +441,34 @@ }; }; + cpu0_debug: debug@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfec10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu1_debug: debug@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu2_debug: debug@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfee10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu3_debug: debug@fef10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfef10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; @@ -885,7 +913,6 @@ power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ - /* dma-coherent; */ }; sdhci0: mmc@ff160000 { @@ -1065,9 +1092,9 @@ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; - clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1097,9 +1124,9 @@ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; - clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1176,11 +1203,14 @@ "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; - dma-names = "vid0", "vid1", "vid2", "gfx0"; + dma-names = "vid0", "vid1", "vid2", "gfx0", + "aud0", "aud1"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, - <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>; ports { #address-cells = <1>; -- 2.43.0

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