July 2023 - U-Boot

v2023.07-rc5 regression: Image overlaps SPL
by Francesco Dolcini 06 Jul '23

06 Jul '23

Hello Marek, as briefly discussed off-list it looks like commit 77aed22b48ab ("spl: spl_legacy: Add extra address checks") introduces a regression on some board/arch, at least colibri and apalis imx6 fails to boot now ``` Trying to boot from MMC1 SPL: Image overlaps SPL resetting ... ``` >From a quick check verdin imx8mm and imx8mp are not affected. I also noticed something weird on a colibri imx7s, this is not using SPL, likely something completly different, however given this is new also from rc5 I thought it's valuable to report: ``` U-Boot 2023.07-rc5-0.0.0-devel+git.580eb31199be (Jun 27 2023 - 13:39:58 +0000) CPU: Freescale i.MX7S rev1.2 800 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 30C Reset cause: POR DRAM: initcall sequence 8786eafc failed at call 8781b351 (err=-3) ### ERROR ### Please RESET the board ### ``` Currently at the EOSS in Prague, so no way to do more testing/debugging, but I tought it was better to start reporting this on the list since we are getting close to the actual release. Francesco

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[PULL] u-boot-usb/master
by Marek Vasut 06 Jul '23

06 Jul '23

The following changes since commit ac29400f1f4ae5df2542bacfe4c142db7824bd6c: Merge tag 'efi-2023-07-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-01 16:11:51 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to d266d4b63873c2176677a79d48faeb9db7d4acdd: usb: dwc3-generic: Ensure reset GPIO is configured as an output (2023-07-03 10:46:34 +0200) ---------------------------------------------------------------- Peter Korsgaard (1): usb: dwc3-generic: Ensure reset GPIO is configured as an output drivers/usb/dwc3/dwc3-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

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[PULL] u-boot-riscv/riscv-for-next
by Leo Liang 06 Jul '23

06 Jul '23

Hi Tom, The following changes since commit e80f4079b3a3db0961b73fa7a96e6c90242d8d25: Merge tag 'v2023.07-rc6' into next (2023-07-05 11:28:55 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git riscv-for-next for you to fetch changes up to 12f66e2197c59e500d1e2ee359bb2ce22d748290: board: ae350: Add missing env variables for booti (2023-07-06 17:28:08 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16799 ---------------------------------------------------------------- - RISC-V CI OpenSBI version update - Andes ae350 board modification - Sync PolarFire SoC dts with Linux - Support building ubifs ---------------------------------------------------------------- Ben Dooks (4): riscv: add generic link for <asm/atomic.h> riscv: implement local_irq_{save,restore} macros riscv: define test_and_{set,clear}_bit in asm/bitops.h clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI Bin Meng (1): ci: riscv: Update OpenSBI to v1.2 Conor Dooley (3): riscv: dts: drop microchip from dts filenames riscv: dts: sync mpfs-icicle devicetree with linux board: microchip: set mac address for ethernet1 on icicle Heinrich Schuchardt (2): cmd/sbi: display new extensions RISC-V: CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS description Hoegeun Kwon (1): clk: starfive: pll: Fix to use postdiv1_mask Yu Chien Peter Lin (2): riscv: andes_plicsw: Fix IPI during OpenSBI invocation board: ae350: Add missing env variables for booti .azure-pipelines.yml | 8 +-- .gitlab-ci.yml | 8 +-- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 136 ------------------------------------------- arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi | 71 +++++++++++++++++++++++ arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} | 0 arch/riscv/dts/mpfs-icicle-kit.dts | 208 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} | 434 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------------------------------------------ arch/riscv/include/asm/atomic.h | 14 +++++ arch/riscv/include/asm/bitops.h | 3 + arch/riscv/include/asm/sbi.h | 9 +++ arch/riscv/include/asm/system.h | 17 ++++-- arch/riscv/lib/andes_plicsw.c | 25 +++++++- board/microchip/mpfs_icicle/mpfs_icicle.c | 15 ++++- cmd/riscv/sbi.c | 3 + common/spl/Kconfig | 6 +- configs/microchip_mpfs_icicle_defconfig | 2 +- doc/board/microchip/mpfs_icicle.rst | 6 +- drivers/clk/sifive/Makefile | 4 +- drivers/clk/starfive/clk-jh7110-pll.c | 2 +- include/configs/ae350.h | 14 +++-- include/dt-bindings/clock/microchip-mpfs-clock.h | 29 +++++++++- include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h | 196 -------------------------------------------------------------- include/dt-bindings/interrupt-controller/riscv-hart.h | 17 ------ 24 files changed, 597 insertions(+), 632 deletions(-) delete mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi rename arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} (100%) create mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts rename arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} (57%) create mode 100644 arch/riscv/include/asm/atomic.h delete mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h Best regards, Leo

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EFI Secure boot default keys
by Neil Jones 06 Jul '23

06 Jul '23

Please can someone describe the format of the file needed for the default / built-in EFI secure boot keys (ubootefi.var) The only docs I have found suggest its best to enroll the keys from within u-boot onto some removable media, then copy this off and use this as the default, this is not very helpful and doesn't work for me: => fatload mmc 0:1 ${loadaddr} PK.aut 2053 bytes read in 18 ms (111.3 KiB/s) => setenv -e -nv -bs -rt -at -i ${loadaddr}:$filesize PK setenv - set environment variables Usage: setenv setenv [-f] name value ... - [forcibly] set environment variable 'name' to 'value ...' setenv [-f] name - [forcibly] delete environment variable 'name' my setenv doesn't support all the extra switches ? This is with 2022.04, all other EFI options seem to be in this release and I can boot unsigned EFI images ok. Cheers, Neil

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[PATCHv3 0/3] net/lwip: add lwip library for the network stack
by Maxim Uvarov 06 Jul '23

06 Jul '23

changelog: v3: - use lwip commands for ping,tftp,wget,dhcp if this patch applied. Drop CONFIG_LIB_LWIP_REPLACE_<COMMAND> option. - docs: use rst variant and drop references to RFC. build: git submodule init git submodule update make I tested with qemu and ubuntu host for the server. If we have more advance CI testing for networking it will be good to get results. Maxim Uvarov (3): net/lwip: add lwip-external submodule net/lwip: add lwip library for the network stack net/lwip: add doc/develop/net_lwip.rst .gitignore | 9 + .gitmodules | 3 + boot/bootmeth_pxe.c | 2 +- cmd/net.c | 48 +---- cmd/pxe.c | 2 +- doc/develop/index.rst | 1 + doc/develop/net_lwip.rst | 59 ++++++ include/net.h | 8 +- lib/Kconfig | 2 + lib/Makefile | 2 + lib/lwip/Kconfig | 63 ++++++ lib/lwip/Makefile | 98 ++++++++++ lib/lwip/apps/dhcp/lwip-dhcp.c | 52 +++++ lib/lwip/apps/http/lwip-wget.c | 71 +++++++ lib/lwip/apps/ping/lwip_ping.c | 37 ++++ lib/lwip/apps/ping/lwip_ping.h | 24 +++ lib/lwip/apps/ping/ping.h | 35 ++++ lib/lwip/apps/tftp/lwip-tftp.c | 121 ++++++++++++ lib/lwip/cmd-lwip.c | 269 ++++++++++++++++++++++++++ lib/lwip/lwip-external | 1 + lib/lwip/lwipopts.h | 203 +++++++++++++++++++ lib/lwip/port/if.c | 260 +++++++++++++++++++++++++ lib/lwip/port/include/arch/cc.h | 46 +++++ lib/lwip/port/include/arch/sys_arch.h | 59 ++++++ lib/lwip/port/include/limits.h | 0 lib/lwip/port/sys-arch.c | 20 ++ lib/lwip/ulwip.h | 9 + net/Kconfig | 1 + net/net.c | 24 +++ 29 files changed, 1485 insertions(+), 44 deletions(-) create mode 100644 .gitmodules create mode 100644 doc/develop/net_lwip.rst create mode 100644 lib/lwip/Kconfig create mode 100644 lib/lwip/Makefile create mode 100644 lib/lwip/apps/dhcp/lwip-dhcp.c create mode 100644 lib/lwip/apps/http/lwip-wget.c create mode 100644 lib/lwip/apps/ping/lwip_ping.c create mode 100644 lib/lwip/apps/ping/lwip_ping.h create mode 100644 lib/lwip/apps/ping/ping.h create mode 100644 lib/lwip/apps/tftp/lwip-tftp.c create mode 100644 lib/lwip/cmd-lwip.c create mode 160000 lib/lwip/lwip-external create mode 100644 lib/lwip/lwipopts.h create mode 100644 lib/lwip/port/if.c create mode 100644 lib/lwip/port/include/arch/cc.h create mode 100644 lib/lwip/port/include/arch/sys_arch.h create mode 100644 lib/lwip/port/include/limits.h create mode 100644 lib/lwip/port/sys-arch.c create mode 100644 lib/lwip/ulwip.h -- 2.30.2

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[PATCH v2] fpga: add inline stub for fpga_load
by Eugen Hristev 06 Jul '23

06 Jul '23

In case CC_OPTIMIZE_FOR_DEBUG is set, unused code will not be optimized out, hence the reference to fpga_load will be compiled. if DM_FPGA and SPL_FPGA are not set, the build will fail with : aarch64-none-linux-gnu-ld.bfd: common/spl/spl_fit.o: in function `spl_fit_upload_fpga': u-boot/common/spl/spl_fit.c:595: undefined reference to `fpga_load' To solve this, added an inline empty stub in the header if CC_OPTIMIZE_FOR_DEBUG is set such that the build will succeed. Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- Changes in v2: - this is a rework as suggested by Simon of this previous patch : https://patchwork.ozlabs.org/project/uboot/patch/20230619102839.277902-1-eu… include/fpga.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/fpga.h b/include/fpga.h index ed688cc0fa3b..50ab03af06bb 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -60,8 +60,17 @@ int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); const fpga_desc *const fpga_get_desc(int devnum); int fpga_is_partial_data(int devnum, size_t img_len); +#if defined(CONFIG_CC_OPTIMIZE_FOR_DEBUG) +static inline int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype, int flags) +{ + return 0; +} +#else int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int flags); +#endif + int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); int fpga_loads(int devnum, const void *buf, size_t size, -- 2.34.1

2 1

[PATCH 0/6] ti: k3-am642: Add daughtercard support
by Roger Quadros 06 Jul '23

06 Jul '23

Hi, This series adds daughtercard detection support for am642-evm. NAND card support is added. cheers, -roger Roger Quadros (6): board: ti: am64x: Recognize AM64-HSEVM board: ti: am64x: Add HSE NAND card detection support arm: dts: k3-am642: Sync main_i2c0 with kernel arm: dts: k3-am642-r5-evm: Add I2C0 and Card detect GPIOs arm: dts: k3-am642: Add I2C GPIO Expander configs: am64x_evm_a53_defconfig: Enable I2C GPIO drivers arch/arm/dts/k3-am642-evm-u-boot.dtsi | 15 +- arch/arm/dts/k3-am642-evm.dts | 28 ++++ arch/arm/dts/k3-am642-r5-evm.dts | 19 +++ board/ti/am64x/evm.c | 188 +++++++++++++++++++++++++- configs/am64x_evm_a53_defconfig | 4 + 5 files changed, 238 insertions(+), 16 deletions(-) -- 2.34.1

2 11

[GIT PULL] Please pull u-boot-mmc master
by Jaehoon Chung 06 Jul '23

06 Jul '23

Dear Tom, Please pull u-boot-mmc master into u-boot master branch. If there is any problem, let me know, plz. Sorry for too late. Those patches are the fixing reensas-sdhi tuning command error and improve the comment. (I have also tested with this patchset on my board.) Best Regards, Jaehoon Chung CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/16765 The following changes since commit e1bebc16e1d9aa0ddd56c53c0b781f7186dce557: Prepare v2023.07-rc6 (2023-07-03 13:48:58 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-mmc.git master for you to fetch changes up to 40825dbac96542e914df4baa3aa0252a503b6b88: mmc: Set clock when reverting to safe bus mode (2023-07-04 08:14:18 +0900) ---------------------------------------------------------------- Hai Pham (2): mmc: Introduce mmc_send_stop_transmission() mmc: renesas-sdhi: Send stop when MMC tuning command fails Marek Vasut (1): mmc: Fix MMC_CMD_STOP_TRANSMISSION response type and add comment Pali Rohár (1): mmc: spl: Add comments for default_spl_mmc_emmc_boot_partition() Valentine Barshak (1): mmc: Set clock when reverting to safe bus mode common/spl/spl_mmc.c | 42 +++++++++++++++++++++++++++++++++++++++--- drivers/mmc/mmc.c | 26 ++++++++++++++++++++++---- drivers/mmc/renesas-sdhi.c | 11 +++++++++++ include/mmc.h | 2 ++ 4 files changed, 74 insertions(+), 7 deletions(-)

1 1

[PATCH v2 0/2] Fix 'no USB device found' error.
by Julien Panis 06 Jul '23

06 Jul '23

This series fixes usb0 dr_mode for am335x-icev2 and am335x-evmsk. It must be set to 'peripheral' in order to avoid 'no USB device found' error, in usb_ether_init() function. Signed-off-by: Julien Panis <jpanis(a)baylibre.com> --- Changes in v2: - Drop the modification made in arch/arm/mach-omap2/am33xx/board.c - Configure usb0 dr_mode as peripheral in 'am335x-icev2-u-boot.dtsi' and 'am335x-evmsk-u-boot.dtsi' device trees. - Link to v1: https://lore.kernel.org/r/20230621-fix_usb_ether_init-v1-1-2156923994a9@bay… --- Julien Panis (2): arm: dts: am335x-icev2-u-boot: Configure peripheral mode for usb0 arm: dts: am335x-evmsk-u-boot: Configure peripheral mode for usb0 arch/arm/dts/am335x-evmsk-u-boot.dtsi | 4 ++++ arch/arm/dts/am335x-icev2-u-boot.dtsi | 4 ++++ 2 files changed, 8 insertions(+) --- base-commit: 19b77d3d23966a0d6dbb3c86187765f11100fb6f change-id: 20230621-fix_usb_ether_init-4bf4f1135113 Best regards, -- Julien Panis <jpanis(a)baylibre.com>

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[PATCH v5] dt-bindings: riscv: deprecate riscv,isa
by Conor Dooley 06 Jul '23

06 Jul '23

From: Conor Dooley <conor.dooley(a)microchip.com> intro ===== When the RISC-V dt-bindings were accepted upstream in Linux, the base ISA etc had yet to be ratified. By the ratification of the base ISA, incompatible changes had snuck into the specifications - for example the Zicsr and Zifencei extensions were spun out of the base ISA. Fast forward to today, and the reason for this patch. Currently the riscv,isa dt property permits only a specific subset of the ISA string - in particular it excludes version numbering. With the current constraints, it is not possible to discern whether "rv64i" means that the hart supports the fence.i instruction, for example. Future systems may choose to implement their own instruction fencing, perhaps using a vendor extension, or they may not implement the optional counter extensions. Software needs a way to determine this. versioning schemes ================== "Use the extension versions that are described in the ISA manual" you may say, and it's not like this has not been considered. Firstly, software that parses the riscv,isa property at runtime will need to contain a lookup table of some sort that maps arbitrary versions to versions it understands. There is not a consistent application of version number applied to extensions, with a higgledy-piggledy collection of tags, "bare" and versioned documents awaiting the reader on the "recently ratified extensions" page: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions As an aside, and this is reflected in the patch too, since many extensions have yet to appear in a release of the ISA specs, they are defined by commits in their respective "working draft" repositories. Secondly, there is an issue of backwards compatibility, whereby allowing numbers in the ISA string, some parsers may be broken. This would require an additional property to be created to even use the versions in this manner. ~boolean properties~ string array property ========================================== If a new property is needed, the whole approach may as well be looked at from the bottom up. A string with limited character choices etc is hardly the best approach for communicating extension information to software. Switching to using properties that are defined on a per extension basis, allows us to define explicit meanings for the DT representation of each extension - rather than the current situation where different operating systems or other bits of software may impart different meanings to characters in the string. Clearly the best source of meanings is the specifications themselves, this just provides us the ability to choose at what point in time the meaning is set. If an extension changes incompatibility in the future, a new property will be required. Off-list, some of the RVI folks have committed to shoring up the wording in either the ISA specifications, the riscv-isa-manual or so that in the future, modifications to and additions or removals of features will require a new extension. Codifying that assertion somewhere would make it quite unlikely that compatibility would be broken, but we have the tools required to deal with it, if & when it crops up. It is in our collective interest, as consumers of extension meanings, to define a scheme that enforces compatibility. The use of individual elements, rather than a single string, will also permit validation that the properties have a meaning, as well as potentially reject mutually exclusive combinations, or enforce dependencies between extensions. That would not have be possible with the current dt-schema infrastructure for arbitrary strings, as we would need to add a riscv,isa parser to dt-validate! That's not implemented in this patch, but rather left as future work (for the brave, or the foolish). parser simplicity ================= Many systems that parse DT at runtime already implement an function that can check for the presence of a string in an array of string, as it is similar to the process for parsing a list of compatible strings, so a bunch of new, custom, DT parsing should not be needed. Getting rid of "riscv,isa" parsing would be a nice simplification, but unfortunately for backwards compatibility with old dtbs, existing parsers may not be removable - which may greatly simplify dt parsing code. In Linux, for example, checking for whether a hart supports an extension becomes as simple as: of_property_match_string(node, "riscv,isa-extensions", "zicbom") vendor extensions ================= Compared to riscv,isa, this proposed scheme promotes vendor extensions, oft touted as the strength of RISC-V, to first-class citizens. At present, extensions are defined as meaning what the RISC-V ISA specifications say they do. There is no realistic way of using that interface to provide cross-platform definitions for what vendor extensions mean. Vendor extensions may also have even less consistency than RVI do in terms of versioning, or no care about backwards compatibility. The new property allows us to assign explicit meanings on a per vendor extension basis, backed up by a description of their meanings. fin === Create a new file to store the extension meanings and a new riscv,isa-base property to replace the aspect of riscv,isa that is not represented by the new property - the base ISA implemented by a hart. As a starting point, add properties for extensions currently used in Linux. Finally, mark riscv,isa as deprecated, as removing support for it in existing programs would be an ABI break. CC: Palmer Dabbelt <palmer(a)dabbelt.com> CC: Paul Walmsley <paul.walmsley(a)sifive.com> CC: Rob Herring <robh+dt(a)kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt(a)linaro.org> CC: Alistair Francis <alistair.francis(a)wdc.com> CC: Andrew Jones <ajones(a)ventanamicro.com> CC: Anup Patel <apatel(a)ventanamicro.com> CC: Atish Patra <atishp(a)atishpatra.org> CC: Jessica Clarke <jrtc27(a)jrtc27.com> CC: Rick Chen <rick(a)andestech.com> CC: Leo <ycliang(a)andestech.com> CC: Oleksii <oleksii.kurochko(a)gmail.com> CC: linux-riscv(a)lists.infradead.org CC: qemu-riscv(a)nongnu.org CC: u-boot(a)lists.denx.de CC: devicetree(a)vger.kernel.org CC: linux-kernel(a)vger.kernel.org Reviewed-by: Palmer Dabbelt <palmer(a)rivosinc.com> Acked-by: Palmer Dabbelt <palmer(a)rivosinc.com> Reviewed-by: Rob Herring <robh(a)kernel.org> Signed-off-by: Conor Dooley <conor.dooley(a)microchip.com> --- Changes in v5: - s/oneOf/anyOf/ so that having both new and old properties passes dt-validate. Changes in v4: - Drop the ACPI section at Anup's request. - Pick up tags from Rob. - Reword some counter access clarification bits in I & Zicsr. Changes in v3: - Per Rob's suggestion, switch to an array of strings. Cuts down on the size, compared to booleans. It has a standard mechanism for parsing (you need to parse arrays of strings for compatibles). It still allows for having a limited set of explicitly defined properties - so the advantages over a free-form string still apply. - Pick up Palmer's Ack and Review (although I expect that he will be the one to apply this). --- .../devicetree/bindings/riscv/cpus.yaml | 43 ++- .../devicetree/bindings/riscv/extensions.yaml | 250 ++++++++++++++++++ 2 files changed, 270 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/riscv/extensions.yaml diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 67bd239ead0b..38c0b5213736 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -25,6 +25,7 @@ description: | allOf: - $ref: /schemas/cpu.yaml# + - $ref: extensions.yaml properties: compatible: @@ -82,25 +83,6 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. - riscv,isa: - description: - Identifies the specific RISC-V instruction set architecture - supported by the hart. These are documented in the RISC-V - User-Level ISA document, available from - https://riscv.org/specifications/ - - Due to revisions of the ISA specification, some deviations - have arisen over time. - Notably, riscv,isa was defined prior to the creation of the - Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" - implies "zicntr_zicsr_zifencei_zihpm". - - While the isa strings in ISA specification are case - insensitive, letters in the riscv,isa string must be all - lowercase. - $ref: /schemas/types.yaml#/definitions/string - pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ - # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false @@ -139,8 +121,17 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. +anyOf: + - required: + - riscv,isa + - required: + - riscv,isa-base + +dependencies: + riscv,isa-base: [ "riscv,isa-extensions" ] + riscv,isa-extensions: [ "riscv,isa-base" ] + required: - - riscv,isa - interrupt-controller unevaluatedProperties: false @@ -160,7 +151,9 @@ examples: i-cache-sets = <128>; i-cache-size = <16384>; reg = <0>; - riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c"; + cpu_intc0: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -183,8 +176,10 @@ examples: i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <1>; - riscv,isa = "rv64imafdc"; tlb-split; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + cpu_intc1: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -202,8 +197,10 @@ examples: device_type = "cpu"; reg = <0>; compatible = "riscv"; - riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + interrupt-controller { #interrupt-cells = <1>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml new file mode 100644 index 000000000000..cc1f546fdbdc --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -0,0 +1,250 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/extensions.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V ISA extensions + +maintainers: + - Paul Walmsley <paul.walmsley(a)sifive.com> + - Palmer Dabbelt <palmer(a)sifive.com> + - Conor Dooley <conor(a)kernel.org> + +description: | + RISC-V has a large number of extensions, some of which are "standard" + extensions, meaning they are ratified by RISC-V International, and others + are "vendor" extensions. + This document defines properties that indicate whether a hart supports a + given extension. + + Once a standard extension has been ratified, no changes in behaviour can be + made without the creation of a new extension. + The properties for standard extensions therefore map to their originally + ratified states, with the exception of the I, Zicntr & Zihpm extensions. + See the "i" property for more information. + +select: + properties: + compatible: + contains: + const: riscv + +properties: + riscv,isa: + description: + Identifies the specific RISC-V instruction set architecture + supported by the hart. These are documented in the RISC-V + User-Level ISA document, available from + https://riscv.org/specifications/ + + Due to revisions of the ISA specification, some deviations + have arisen over time. + Notably, riscv,isa was defined prior to the creation of the + Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" + implies "zicntr_zicsr_zifencei_zihpm". + + While the isa strings in ISA specification are case + insensitive, letters in the riscv,isa string must be all + lowercase. + $ref: /schemas/types.yaml#/definitions/string + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + deprecated: true + + riscv,isa-base: + description: + The base ISA implemented by this hart, as described by the 20191213 + version of the unprivileged ISA specification. + enum: + - rv32i + - rv64i + + riscv,isa-extensions: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 1 + description: Extensions supported by the hart. + items: + anyOf: + # single letter extensions, in canonical order + - const: i + description: | + The base integer instruction set, as ratified in the 20191213 + version of the unprivileged ISA specification. + + This does not include Chapter 10, "Counters", which was moved into + the Zicntr and Zihpm extensions after the ratification of the + 20191213 version of the unprivileged specification. + + - const: m + description: + The standard M extension for integer multiplication and division, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: a + description: + The standard A extension for atomic instructions, as ratified in the + 20191213 version of the unprivileged ISA specification. + + - const: f + description: + The standard F extension for single-precision floating point, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: d + description: + The standard D extension for double-precision floating-point, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: q + description: + The standard Q extension for quad-precision floating-point, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: c + description: + The standard C extension for compressed instructions, as ratified in + the 20191213 version of the unprivileged ISA specification. + + - const: v + description: + The standard V extension for vector operations, as ratified + in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f + encoding") of the riscv-v-spec. + + - const: h + description: + The standard H extension for hypervisors as ratified in the 20191213 + version of the privileged ISA specification. + + # multi-letter extensions, sorted alphanumerically + - const: smaia + description: | + The standard Smaia supervisor-level extension for the advanced + interrupt architecture for machine-mode-visible csr and behavioural + changes to interrupts as frozen at commit ccbddab ("Merge pull + request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + + - const: ssaia + description: | + The standard Ssaia supervisor-level extension for the advanced + interrupt architecture for supervisor-mode-visible csr and + behavioural changes to interrupts as frozen at commit ccbddab + ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + + - const: sscofpmf + description: | + The standard Sscofpmf supervisor-level extension for count overflow + and mode-based filtering as ratified at commit 01d1df0 ("Add ability + to manually trigger workflow. (#2)") of riscv-count-overflow. + + - const: sstc + description: | + The standard Sstc supervisor-level extension for time compare as + ratified at commit 3f9ed34 ("Add ability to manually trigger + workflow. (#2)") of riscv-time-compare. + + - const: svinval + description: + The standard Svinval supervisor-level extension for fine-grained + address-translation cache invalidation as ratified in the 20191213 + version of the privileged ISA specification. + + - const: svnapot + description: + The standard Svnapot supervisor-level extensions for napot + translation contiguity as ratified in the 20191213 version of the + privileged ISA specification. + + - const: svpbmt + description: + The standard Svpbmt supervisor-level extensions for page-based + memory types as ratified in the 20191213 version of the privileged + ISA specification. + + - const: zba + description: | + The standard Zba bit-manipulation extension for address generation + acceleration instructions as ratified at commit 6d33919 ("Merge pull + request #158 from hirooih/clmul-fix-loop-end-condition") of + riscv-bitmanip. + + - const: zbb + description: | + The standard Zbb bit-manipulation extension for basic bit-manipulation + as ratified at commit 6d33919 ("Merge pull request #158 from + hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + + - const: zbc + description: | + The standard Zbc bit-manipulation extension for carry-less + multiplication as ratified at commit 6d33919 ("Merge pull request + #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + + - const: zbs + description: | + The standard Zbs bit-manipulation extension for single-bit + instructions as ratified at commit 6d33919 ("Merge pull request #158 + from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + + - const: zicbom + description: + The standard Zicbom extension for base cache management operations as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + + - const: zicbop + description: + The standard Zicbop extension for cache-block prefetch instructions + as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of + riscv-CMOs. + + - const: zicboz + description: + The standard Zicboz extension for cache-block zeroing as ratified + in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + + - const: zicntr + description: + The standard Zicntr extension for base counters and timers, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: zicsr + description: | + The standard Zicsr extension for control and status register + instructions, as ratified in the 20191213 version of the + unprivileged ISA specification. + + This does not include Chapter 10, "Counters", which documents + special case read-only CSRs, that were moved into the Zicntr and + Zihpm extensions after the ratification of the 20191213 version of + the unprivileged specification. + + - const: zifencei + description: + The standard Zifencei extension for instruction-fetch fence, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: zihintpause + description: + The standard Zihintpause extension for pause hints, as ratified in + commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. + + - const: zihpm + description: + The standard Zihpm extension for hardware performance counters, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: ztso + description: + The standard Ztso extension for total store ordering, as ratified + in commit 2e5236 ("Ztso is now ratified.") of the + riscv-isa-manual. + +additionalProperties: true +... -- 2.39.2

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