July 2023 - U-Boot

[PATCH] ci: riscv: Update OpenSBI to v1.2
by Bin Meng 05 Jul '23

05 Jul '23

Use the latest OpenSBI v1.2 release binaries for the RISC-V CI. Signed-off-by: Bin Meng <bmeng(a)tinylab.org> --- .azure-pipelines.yml | 8 ++++---- .gitlab-ci.yml | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 3c1846a5bc..39536e1d93 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -391,12 +391,12 @@ stages: grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensb… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensb… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi # the below corresponds to .gitlab-ci.yml "script" cd ${WORK_DIR} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e6c6ab3586..cfd58513c3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,12 +29,12 @@ stages: - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensb… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensb… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi after_script: -- 2.25.1

2 1

[PATCH 1/2] riscv: andes_plicsw: Fix IPI during OpenSBI invocation
by Yu Chien Peter Lin 05 Jul '23

05 Jul '23

On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin(a)andestech.com> --- arch/riscv/lib/andes_plicsw.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 324eb445aaa..75184080890 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -2,9 +2,10 @@ /* * Copyright (C) 2019, Rick Chen <rick(a)andestech.com> * - * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC). - * The PLIC block holds memory-mapped claim and pending registers - * associated with software interrupt. + * U-Boot syscon driver for Andes' PLICSW + * The PLICSW block is an Andes-specific design for software interrupts, + * contains memory-mapped priority, enable, claim and pending registers + * similar to RISC-V PLIC. */ #include <common.h> @@ -26,9 +27,13 @@ #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) +/* priority register */ +#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) #define ENABLE_HART_IPI (0x01010101) #define SEND_IPI_TO_HART(hart) (0x1 << (hart)) +#define PLICSW_PRIORITY_BASE 0x4 +#define PLICSW_INTERRUPT_PER_HART 0x8 DECLARE_GLOBAL_DATA_PTR; @@ -43,9 +48,21 @@ static int enable_ipi(int hart) return 0; } +static void init_priority_ipi(int hart_num) +{ + uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + + for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { + writel(1, &priority[i]); + } + + return; +} + int riscv_init_ipi(void) { int ret; + int hart_num = 0; long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW); ofnode node; struct udevice *dev; @@ -79,8 +96,10 @@ int riscv_init_ipi(void) ret = ofnode_read_u32(node, "reg", &reg); if (ret == 0) enable_ipi(reg); + hart_num++; } + init_priority_ipi(hart_num); return 0; } -- 2.34.1

2 3

[PATCH v4 1/2] ARM: dts: rockchip: rk3588: Move bootph-all props to common file
by Eugen Hristev 04 Jul '23

04 Jul '23

Move bootph-all prop to common SoC dt file, because they are typically used by multiple boards. Unreferenced nodes are removed from the SPL device tree during a normal build. Suggested-by: Jonas Karlman <jonas(a)kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- Changes in v4: - new patch arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 54 ------------------------ arch/arm/dts/rk3588s-u-boot.dtsi | 56 +++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 54 deletions(-) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index f453aeeaf526..2a80422390e7 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -77,26 +77,6 @@ status = "okay"; }; -&emmc_bus8 { - bootph-all; -}; - -&emmc_clk { - bootph-all; -}; - -&emmc_cmd { - bootph-all; -}; - -&emmc_data_strobe { - bootph-all; -}; - -&emmc_rstnout { - bootph-all; -}; - &fspim2_pins { bootph-all; }; @@ -109,8 +89,6 @@ }; &pinctrl { - bootph-all; - pcie { pcie_reset_h: pcie-reset-h { rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -139,39 +117,11 @@ }; }; -&pcfg_pull_none { - bootph-all; -}; - -&pcfg_pull_up_drv_level_2 { - bootph-all; -}; - -&pcfg_pull_up { - bootph-all; -}; - &sdmmc { bus-width = <4>; status = "okay"; }; -&sdmmc_bus4 { - bootph-all; -}; - -&sdmmc_clk { - bootph-all; -}; - -&sdmmc_cmd { - bootph-all; -}; - -&sdmmc_det { - bootph-all; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; @@ -199,10 +149,6 @@ }; }; -&uart2m0_xfer { - bootph-all; -}; - &usb_host0_ehci { companion = <&usb_host0_ohci>; phys = <&u2phy2_host>; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index acb1cfe20063..2d0b0d8ce2fc 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -302,6 +302,42 @@ }; }; +&emmc_bus8 { + bootph-all; +}; + +&emmc_clk { + bootph-all; +}; + +&emmc_cmd { + bootph-all; +}; + +&emmc_data_strobe { + bootph-all; +}; + +&emmc_rstnout { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + &xin24m { bootph-all; status = "okay"; @@ -335,12 +371,32 @@ u-boot,spl-fifo-mode; }; +&sdmmc_bus4 { + bootph-all; +}; + +&sdmmc_clk { + bootph-all; +}; + +&sdmmc_cmd { + bootph-all; +}; + +&sdmmc_det { + bootph-all; +}; + &uart2 { clock-frequency = <24000000>; bootph-pre-ram; status = "okay"; }; +&uart2m0_xfer { + bootph-all; +}; + &ioc { bootph-pre-ram; }; -- 2.34.1

1 1

[PATCH] colibri-imx7: Call fdt_increase_size()
by Fabio Estevam 04 Jul '23

04 Jul '23

From: Fabio Estevam <festevam(a)denx.de> For changing the USB OTG node status from "okay" to "disabled" more space is needed, so call fdt_increase_size() to avoid the following error: ``` U-Boot 2023.07-rc5-0.0.0-devel+git.580eb31199be (Jun 27 2023 - 13:39:58 +0000) CPU: Freescale i.MX7S rev1.2 800 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 30C Reset cause: POR DRAM: initcall sequence 8786eafc failed at call 8781b351 (err=-3) ### ERROR ### Please RESET the board ### ``` Ideally, fdt_status_disabled() should call fdt_increase_size() internally, so that there would be no need for manually calling it in board code. Do it manually for now to fix the regression. Based on the code from board/CZ.NIC/turris_omnia/turris_omnia.c. Reported-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- board/toradex/colibri_imx7/colibri_imx7.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 3e79ab93a982..78be17c3b550 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -311,10 +311,22 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_USB_EHCI_MX7 int board_fix_fdt(void *rw_fdt_blob) { + int ret; + /* i.MX 7Solo has only one single USB OTG1 but no USB host port */ if (is_cpu_type(MXC_CPU_MX7S)) { int offset = fdt_path_offset(rw_fdt_blob, "/soc/bus@30800000/usb@30b20000"); + /* + * We're changing from status = "okay" to status = "disabled". + * In this case we'll need more space, so increase the size + * a little bit. + */ + ret = fdt_increase_size(rw_fdt_blob, 32); + if (ret < 0) { + printf("Cannot increase FDT size: %d\n", ret); + return ret; + } return fdt_status_disabled(rw_fdt_blob, offset); } -- 2.34.1

2 1

[PATCH 2/2] mxs: Don't enable 4P2 reg if MXS is powered only from DCDC_BATT
by Cody Green 04 Jul '23

04 Jul '23

'mxs_power_enable_4p2()' function call was added to 'mxs_batt_boot()' in 'commit a0f97610757d' to enable DCDC converter when board is powered from 5V and has detected sufficient battery voltage. This involves enabling 4P2 regulator and there is a code in 'mxs_power_enable_4p2()' that disables VDDIO, VDDA, VDDD outputs of the DCDC converter and enables BO for each power rail: setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); There is no issue if the MXS is powered from the 5V source and linear regulators are supplying power to the VDDIO, VDDA, VDDD rails. However, if the MXS is powered only from the DCDC_BATT without 5V, disabling the DCDC converter outputs causes VDDIO, VDDA, VDDD rails to lose power. The proposed solution is not to call the 'mxs_power_enable_4p2()' function if the MXS is powered only by the DCDC_BATT, because there is no reason to enable 4P2 regulator in this case. Also 5V brownout should not be enabled in 'mxs_power_init()' and linear regulator checks should be disabled in 'mxs_power_set_vddx()'. Signed-off-by: Cody Green <cody(a)londelec.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 33b76533e4..72172705f2 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,7 +752,9 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +#ifndef CFG_SPL_MXS_NO_VDD5V_SOURCE mxs_power_enable_4p2(); +#endif } /** @@ -1137,8 +1139,11 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, cur_target += cfg->lowest_mV; adjust_up = new_target > cur_target; + +#ifndef CFG_SPL_MXS_NO_VDD5V_SOURCE if (cfg->powered_by_linreg) powered_by_linreg = cfg->powered_by_linreg(); +#endif if (adjust_up && cfg->bo_irq) { if (powered_by_linreg) { @@ -1269,7 +1274,9 @@ void mxs_power_init(void) POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +#ifndef CFG_SPL_MXS_NO_VDD5V_SOURCE writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); +#endif early_delay(1000); } -- 2.25.1

3 3

[PATCH] board: stm32mp1: add splash screen on dk2
by Dario Binacchi 04 Jul '23

04 Jul '23

Display the STMicroelectronics logo. Signed-off-by: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> --- board/st/stm32mp1/stm32mp1.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 1a1b1844c8c0..c8c2a83b2acf 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -32,7 +32,10 @@ #include <remoteproc.h> #include <reset.h> #include <syscon.h> +#include <splash.h> +#include <st_logo_data.h> #include <usb.h> +#include <video.h> #include <watchdog.h> #include <asm/global_data.h> #include <asm/io.h> @@ -684,6 +687,15 @@ int board_init(void) fw_images[0].fw_name = u"STM32MP-FIP"; fw_images[0].image_index = 1; #endif + + if (IS_ENABLED(CONFIG_CMD_BMP)) { + if (board_is_stm32mp15x_dk2()) { + ulong logo = + (ulong)stmicroelectronics_uboot_logo_8bit_rle; + bmp_display(logo, BMP_ALIGN_CENTER, BMP_ALIGN_CENTER); + } + } + return 0; } -- 2.32.0

2 3

[PATCH v3] board: rockchip: add Radxa ROCK5A Rk3588 board
by Eugen Hristev 04 Jul '23

04 Jul '23

ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa. There are tree variants depending on the DRAM size : 4G, 8G and 16G. Specifications: Rockchip Rk3588S SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 4/8/16GB memory LPDDR4x Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector 4-lane MIPI DSI connector Audio – 3.5mm earphone jack eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60 Gigabit Ethernet RJ45 with optional PoE support 40-pin IO header including UART, SPI, I2C and 5V DC power in USB PD over USB Type-C Size: 85mm x 56mm (Raspberry Pi 4 form factor) Kernel commits: d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board") 991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a") 304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a") cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on rk3588s-rock5a") Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- Changes in v3: - forgot to add defconfig and include file, added now, sorry Changes in v2: -fixed wrong Kconfig text (rk3588s instead of rk3588) -changed doc name (rk3588s instead of rk3588) arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 90 +++++++++++++++++++++ arch/arm/dts/rk3588s-rock-5a.dts | 73 +++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 28 +++++++ board/radxa/rock5a-rk3588s/Kconfig | 15 ++++ board/radxa/rock5a-rk3588s/MAINTAINERS | 6 ++ board/radxa/rock5a-rk3588s/Makefile | 6 ++ board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 +++++++++ configs/rock5a-rk3588s_defconfig | 71 ++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/rock5a-rk3588s.h | 15 ++++ 11 files changed, 345 insertions(+) create mode 100644 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-rock-5a.dts create mode 100644 board/radxa/rock5a-rk3588s/Kconfig create mode 100644 board/radxa/rock5a-rk3588s/MAINTAINERS create mode 100644 board/radxa/rock5a-rk3588s/Makefile create mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c create mode 100644 configs/rock5a-rk3588s_defconfig create mode 100644 include/configs/rock5a-rk3588s.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269fa6065..cd9b96c5ba7c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588s-rock-5a.dtb \ rk3588-rock-5b.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi new file mode 100644 index 000000000000..a546f9e4dcc2 --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include "rk3588s-u-boot.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/usb/pd.h> + +/ { + aliases { + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +}; + +&emmc_bus8 { + bootph-all; +}; + +&emmc_clk { + bootph-all; +}; + +&emmc_cmd { + bootph-all; +}; + +&emmc_data_strobe { + bootph-all; +}; + +&emmc_rstnout { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; +}; + +&sdmmc_bus4 { + bootph-all; +}; + +&sdmmc_clk { + bootph-all; +}; + +&sdmmc_cmd { + bootph-all; +}; + +&sdmmc_det { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; +}; + +&uart2m0_xfer { + bootph-all; +}; + diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts new file mode 100644 index 000000000000..901825514f9d --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5a.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588s.dtsi" + +/ { + model = "Radxa ROCK 5 Model A"; + compatible = "radxa,rock-5a", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x3a>; + rx_delay = <0x3e>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index b7d5f13bebbf..90d389137ade 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -19,6 +19,33 @@ config TARGET_RK3588_NEU6 IO board and Neu6a needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 6(Neu6) IO platform. +config TARGET_ROCK5A_RK3588 + bool "Radxa ROCK5A RK3588 board" + select BOARD_LATE_INIT + help + Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer) + by Radxa. + + There are tree variants depending on the DRAM size : 4G, 8G and 16G. + + Specification: + + Rockchip Rk3588S SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 4/8/16GB memory LPDDR4x + Mali G610MC4 GPU + MIPI CSI 2 multiple lanes connector + 4-lane MIPI DSI connector + Audio – 3.5mm earphone jack + eMMC module connector + uSD slot (up to 128GB) + 2x USB 2.0, 2x USB 3.0 + 2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60 + Gigabit Ethernet RJ45 with optional PoE support + 40-pin IO header including UART, SPI, I2C and 5V DC power in + USB PD over USB Type-C + Size: 85mm x 56mm (Raspberry Pi 4 form factor) + config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" select BOARD_LATE_INIT @@ -58,6 +85,7 @@ config SYS_MALLOC_F_LEN source board/edgeble/neural-compute-module-6/Kconfig source board/rockchip/evb_rk3588/Kconfig +source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig endif diff --git a/board/radxa/rock5a-rk3588s/Kconfig b/board/radxa/rock5a-rk3588s/Kconfig new file mode 100644 index 000000000000..2d7fc85df4fe --- /dev/null +++ b/board/radxa/rock5a-rk3588s/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCK5A_RK3588 + +config SYS_BOARD + default "rock5a-rk3588s" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock5a-rk3588s" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS new file mode 100644 index 000000000000..26e0ed93386b --- /dev/null +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -0,0 +1,6 @@ +ROCK5A-RK3588 +M: Eugen Hristev <eugen.hristev(a)collabora.com> +S: Maintained +F: board/radxa/rock5a-rk3588s +F: include/configs/rock5a-rk3588.h +F: configs/rock5a-rk3588_defconfig diff --git a/board/radxa/rock5a-rk3588s/Makefile b/board/radxa/rock5a-rk3588s/Makefile new file mode 100644 index 000000000000..48dd51245508 --- /dev/null +++ b/board/radxa/rock5a-rk3588s/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Collabora Ltd. +# + +obj-y += rock5a-rk3588s.o diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c new file mode 100644 index 000000000000..5c3b52b94898 --- /dev/null +++ b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +int rock5b_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return rock5b_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig new file mode 100644 index 000000000000..591121673e00 --- /dev/null +++ b/configs/rock5a-rk3588s_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x1000000 +CONFIG_TARGET_ROCK5A_RK3588=y +CONFIG_SPL_STACK=0x1000000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_SPL_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 99376fb54c90..59d69f07018f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: * rk3588 - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588) + - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) * rv1108 diff --git a/include/configs/rock5a-rk3588s.h b/include/configs/rock5a-rk3588s.h new file mode 100644 index 000000000000..9a2d3ee9f536 --- /dev/null +++ b/include/configs/rock5a-rk3588s.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#ifndef __ROCK5A_RK3588_H +#define __ROCK5A_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __ROCK5A_RK3588_H */ -- 2.34.1

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[PATCH 0/3] binman: Add support for externally encrypted blobs
by christian.taedcke-oss＠weidmueller.com 04 Jul '23

04 Jul '23

From: Christian Taedcke <christian.taedcke(a)weidmueller.com> This series adds the functionality to handle externally encrypted blobs to binman. It includes the functionality itself and the corresponding unit tests. The generated device tree structure is similar to the structure used in the already implemented cipher node in boot/image-cipher.c. The following block shows an example on how to use this functionality. In the device tree that is parsed by binman a new node encrypted is used: / { binman { filename = "u-boot.itb"; fit { ... images { some-bitstream { ... image_bitstream: blob-ext { filename = "bitstream.bin"; }; encrypted { content = <&image_bitstream>; algo = "aes256-gcm"; key-name-hint = "keyname"; iv-filename = "bitstream.bin.iv"; key-filename = "bitstream.bin.key"; }; ... This results in an generated fit image containing the following information: \ { cipher { key-aes256-gcm-keyname { key = <0x...>; iv = <0x...>; }; }; images { ... some-bitstream { ... data = [...] cipher { algo = "aes256-gcm"; key-name-hint = "keyname"; }; }; ... Christian Taedcke (3): binman: Add support for externally encrypted blobs binman: Allow cipher node as special section binman: Add tests for etype encrypted tools/binman/etype/encrypted.py | 98 +++++++++++++++++++ tools/binman/etype/section.py | 2 +- tools/binman/ftest.py | 69 +++++++++++++ .../binman/test/282_encrypted_no_content.dts | 15 +++ tools/binman/test/283_encrypted_no_algo.dts | 19 ++++ .../test/284_encrypted_invalid_iv_file.dts | 22 +++++ tools/binman/test/285_encrypted.dts | 29 ++++++ tools/binman/test/286_encrypted_key_file.dts | 30 ++++++ .../test/287_encrypted_iv_name_hint.dts | 30 ++++++ 9 files changed, 313 insertions(+), 1 deletion(-) create mode 100644 tools/binman/etype/encrypted.py create mode 100644 tools/binman/test/282_encrypted_no_content.dts create mode 100644 tools/binman/test/283_encrypted_no_algo.dts create mode 100644 tools/binman/test/284_encrypted_invalid_iv_file.dts create mode 100644 tools/binman/test/285_encrypted.dts create mode 100644 tools/binman/test/286_encrypted_key_file.dts create mode 100644 tools/binman/test/287_encrypted_iv_name_hint.dts -- 2.34.1

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[PATCH v1] spi: npcm_pspi: use ACTIVE_LOW flag for cs gpio and set default max_hz
by Jim Liu 04 Jul '23

04 Jul '23

If cs gpio is requested with ACTIVE_HIGH flag, it will be pulled low(i.e. active). This is not what we expected. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/spi/npcm_pspi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c index bd9ac65411..37bab70967 100644 --- a/drivers/spi/npcm_pspi.c +++ b/drivers/spi/npcm_pspi.c @@ -40,7 +40,7 @@ static inline void spi_cs_activate(struct udevice *dev) struct udevice *bus = dev->parent; struct npcm_pspi_priv *priv = dev_get_priv(bus); - dm_gpio_set_value(&priv->cs_gpio, 0); + dm_gpio_set_value(&priv->cs_gpio, 1); } static inline void spi_cs_deactivate(struct udevice *dev) @@ -48,7 +48,7 @@ static inline void spi_cs_deactivate(struct udevice *dev) struct udevice *bus = dev->parent; struct npcm_pspi_priv *priv = dev_get_priv(bus); - dm_gpio_set_value(&priv->cs_gpio, 1); + dm_gpio_set_value(&priv->cs_gpio, 0); } static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) @@ -122,6 +122,9 @@ static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_END) spi_cs_deactivate(dev); + debug("npcm_pspi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n", + dev->parent->name, dev->name, *(uint *)tx, *(uint *)rx, bitlen); + npcm_pspi_disable(priv); return ret; @@ -183,6 +186,7 @@ static int npcm_pspi_set_mode(struct udevice *bus, uint mode) val |= pspi_mode; writew(val, priv->base + PSPI_CTL1); + debug("%s: mode=%u\n", __func__, mode); return 0; } @@ -197,9 +201,9 @@ static int npcm_pspi_probe(struct udevice *bus) return ret; priv->base = dev_read_addr_ptr(bus); - priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1000000); gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, - &priv->cs_gpio, GPIOD_IS_OUT); + &priv->cs_gpio, GPIOD_IS_OUT| GPIOD_ACTIVE_LOW); return 0; } -- 2.17.1

1 0

sipeed maix bit resets every 90 seconds with watchdog enabled
by Jaap Aart 04 Jul '23

04 Jul '23

Dear sean, and others, I encountered a small problem running linux on the sipeed maix bit from u-boot. Every 90 seconds (exactly) after boot it resets, if booted into linux, unless I disable the watchdog. This has occurred since this feature was enabled (e3282b1bbae4e8558c2b85bf27560d12358ed25f) Although I do not completely understand the watchdog features, it notes it is set to 60 seconds, and I am convinced that the point is not to reset every X seconds. Especially because this is enabled by default. I have not really found a good workaround besides disabling the WDT at runtime which is cumbersome. Is this expected behavior? And if so, how do I disable this feature at compile time? Kind regards, Jaap Aarts

2 1