June 2023 - U-Boot

[PATCH 1/1] test: correct architecture in EFI FIT test
by Heinrich Schuchardt 15 Jun '23

15 Jun '23

On arm64 the its we use to generate the test FIT image has arch = "arm"; We should use "arm64" here which is mapped to IH_ARCH_ARM64 via uimage_arch[]. Fixes: 8391f955494e ("test/py: Create a test for launching UEFI binaries from FIT images") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- test/py/tests/test_efi_fit.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py index 7b7c98fb04..0ad483500f 100644 --- a/test/py/tests/test_efi_fit.py +++ b/test/py/tests/test_efi_fit.py @@ -431,6 +431,11 @@ def test_efi_fit_launch(u_boot_console): cons = u_boot_console # Array slice removes leading/trailing quotes. sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1] + if sys_arch == 'arm': + arm64 = cons.config.buildconfig.get('config_arm64') + if arm64: + sys_arch = 'arm64' + is_sandbox = sys_arch == 'sandbox' if is_sandbox: -- 2.40.1

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[PATCH v3 0/2] sunxi, usb: Clean up SRAM initialization code
by Sam Edwards 15 Jun '23

15 Jun '23

Hello again, The only change from v2 is that `syscon_base` is now a param of `sunxi_musb_claim_sram`, and the TODO comment has been removed. Cheers, Sam Sam Edwards (2): usb: musb-new: sunxi: only perform SRAM initialization when necessary usb: musb-new: sunxi: clarify the purpose of SRAM initialization drivers/usb/musb-new/sunxi.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) -- 2.39.2

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[PATCH v2 0/3] Sync PolarFire SoC dts with Linux
by Conor Dooley 15 Jun '23

15 Jun '23

Hey, Couple of patches here that do a long-overdue sync of the Linux devicetree for PolarFire SoC & the Icicle kit with Linux. This wasn't possible for a while due to an incorrect dts & clock driver that were based on a pre-upstream version of the dt-binding. That's fixed now, so a complete re-sync is possible. To elide complaints about the mac address not being set for the second ethernet, the code which set it for ethernet0 has been changed to set it for whichever (or both) of the macbs that are enabled. Hopefully I'll have a follow-on bit of work soonTM that will rework the mac address setting code as it'll be needed to support another board. Cheers, Conor. Changes in v2: - Fix address in error print in 3/3 Conor Dooley (3): riscv: dts: drop microchip from dts filenames riscv: dts: sync mpfs-icicle devicetree with linux board: microchip: set mac address for ethernet1 on icicle arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 136 ------ arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi | 71 +++ ...-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} | 0 arch/riscv/dts/mpfs-icicle-kit.dts | 208 +++++++++ .../dts/{microchip-mpfs.dtsi => mpfs.dtsi} | 442 ++++++++---------- board/microchip/mpfs_icicle/mpfs_icicle.c | 15 +- configs/microchip_mpfs_icicle_defconfig | 2 +- doc/board/microchip/mpfs_icicle.rst | 6 +- .../dt-bindings/clock/microchip-mpfs-clock.h | 29 +- .../microchip-mpfs-plic.h | 196 -------- .../interrupt-controller/riscv-hart.h | 17 - 12 files changed, 514 insertions(+), 610 deletions(-) delete mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi rename arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} (100%) create mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts rename arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} (57%) delete mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h -- 2.40.1

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[PATCH V3 0/8] Update SPL splashscreen framework for AM62x
by Nikhil M Jain 15 Jun '23

15 Jun '23

This patch series aims at updating SPL splashscreen framework for AM62x. This patch series depends on https://lore.kernel.org/u-boot/20230504225829.2537050-1-sjg@chromium.org/ This series: - Fixes compilation issues in case splash related configs are not defined in SPL. - Does page table setup, dram initialisation and dcache enabling in one function call spl_enable_dcache. - Allows passing of framebuffer from spl to u-boot, eliminating flicker. V3: - Fix spacing issues. - Add Reviewed-by tag. - Replace #if with if in patch common: spl: spl: Remove video driver - Add link to updated memory map. V2: - Update cover letter. - Fix commit message. Nikhil M Jain (8): common: spl: spl: Update stack pointer address arch: arm: mach-k3: common: Return a pointer after setting page table board: ti: am62x: evm: Update function calls for splash screen include: video: Reserve video using blob common: board_f: Pass frame buffer info from SPL to u-boot drivers: video: Kconfig: Add config remove video common: spl: spl: Remove video driver configs: am62x_evm_a53: Add bloblist address arch/arm/mach-k3/am625_init.c | 1 + arch/arm/mach-k3/common.c | 2 ++ board/ti/am62x/evm.c | 41 ++++++++++++--------------------- common/board_f.c | 11 ++++++++- common/spl/spl.c | 23 +++++++++--------- configs/am62x_evm_a53_defconfig | 1 + drivers/video/Kconfig | 12 ++++++++++ drivers/video/video-uclass.c | 23 ++++++++++++++++++ include/video.h | 9 ++++++++ 9 files changed, 85 insertions(+), 38 deletions(-) -- 2.34.1

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[PATCH 0/2] board: fsl: lx2160ardb: fixup PHY addresses for new board revisions
by Ioana Ciornei 15 Jun '23

15 Jun '23

On the board revisions C and D, the LX2160A-RDB has the two 10G copper PHYs at different MDIO addresses. This patch set does the necessary fixup to both u-boot's and Linux's DTS so that the PHYs are properly described. Florin Chiculita (2): board: fsl: lx2160ardb: add api for obtaining board revision board: fsl: lx2160ardb: add dts fixup function for RevC and newer board/freescale/lx2160a/eth_lx2160ardb.c | 107 +++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 22 +++-- board/freescale/lx2160a/lx2160a.h | 5 ++ include/configs/lx2160ardb.h | 5 ++ 4 files changed, 134 insertions(+), 5 deletions(-) -- 2.25.1

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[PATCH v9 00/10] FMP versioning support
by Masahisa Kojima 15 Jun '23

15 Jun '23

Firmware version management is not implemented in the current FMP implementation. This series aims to add the versioning support in FMP. Currently, there is no way to know the current running firmware version through the EFI interface. FMP->GetImageInfo() returns always 0 for the version number. So a user can not know that expected firmware is running after the capsule update. EDK II reference implementation utilizes the FMP Payload Header inserted right before the capsule payload. U-Boot also follows the EDK II implementation. With this series applied, version number can be specified in the capsule file generation with mkeficapsule tool, then user can know the running firmware version through FMP->GetImageInfo() and ESRT. There is a design consideration for lowest supported version. If the backing storage is a file we can't trust any of that information since anyone can tamper with the file, although the variables are defined as RO. With that, we store the lowest supported version in the device tree. We can trust the information from dtb as long as the former stage boot loader verifies the image containing the dtb. The firmware version can not be stored in device tree because not all the capsule files do not have a device tree. Note that this series does not mandate the FMP Payload Header, compatible with boards that are already using the existing U-Boot FMP implementation. If no FMP Payload Header is found in the capsule file, fw_version, lowest supported version, last attempt version and last attempt status is set to 0 and this is the same behavior as existing FMP implementation. Major Changes in v9: - This version only updates python tests(test/py/tests/test_efi_capsule) - fix pylint warnings Major Changes in v8: - This version only updates python tests(test/py/tests/test_efi_capsule) - remove excess semicolons - add comments of newly created common functions Major Changes in v7: - refactor the efi_capsule python test - add test cases for the FMP versioning Major Changes in v6: - change the location of fw_version and lowest supported version - fw_version is stored in FMP Payload Header in the capsule file - lowest_supported_version is stored in the device tree Major Changes in v5: - major design changes, versioning is implemented with device tree instead of EFI variable Major Changes in v4: - add python-based test Major Changes in v3: - exclude CONFIG_FWU_MULT Masahisa Kojima (10): efi_loader: add the number of image entries in efi_capsule_update_info efi_loader: store firmware version into FmpState variable efi_loader: versioning support in GetImageInfo efi_loader: get lowest supported version from device tree efi_loader: check lowest supported version mkeficapsule: add FMP Payload Header doc: uefi: add firmware versioning documentation doc: uefi: add anti-rollback documentation test: efi_capsule: refactor efi_capsule test test/py: efi_capsule: test for FMP versioning arch/arm/mach-rockchip/board.c | 4 +- .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 2 +- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 2 +- board/emulation/qemu-arm/qemu-arm.c | 2 +- board/kontron/pitx_imx8m/pitx_imx8m.c | 2 +- board/kontron/sl-mx8mm/sl-mx8mm.c | 2 +- board/kontron/sl28/sl28.c | 2 +- board/rockchip/evb_rk3399/evb-rk3399.c | 2 +- board/sandbox/sandbox.c | 2 +- board/socionext/developerbox/developerbox.c | 2 +- board/st/stm32mp1/stm32mp1.c | 2 +- board/xilinx/common/board.c | 2 +- doc/develop/uefi/uefi.rst | 66 ++++ .../firmware/firmware-version.txt | 22 ++ doc/mkeficapsule.1 | 10 + include/efi_loader.h | 3 +- lib/efi_loader/efi_firmware.c | 276 ++++++++++++++-- lib/fwu_updates/fwu.c | 2 +- .../tests/test_efi_capsule/capsule_common.py | 142 +++++++++ test/py/tests/test_efi_capsule/conftest.py | 82 +++++ .../test_capsule_firmware_fit.py | 213 ++++++------- .../test_capsule_firmware_raw.py | 301 +++++++----------- .../test_capsule_firmware_signed_fit.py | 269 ++++++---------- .../test_capsule_firmware_signed_raw.py | 276 +++++++--------- test/py/tests/test_efi_capsule/version.dts | 24 ++ tools/eficapsule.h | 30 ++ tools/mkeficapsule.c | 37 ++- 27 files changed, 1102 insertions(+), 677 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt create mode 100644 test/py/tests/test_efi_capsule/capsule_common.py create mode 100644 test/py/tests/test_efi_capsule/version.dts -- 2.34.1

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Re: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT
by Rick Chen 15 Jun '23

15 Jun '23

> From: Bin Meng <bmeng(a)tinylab.org> > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot(a)lists.denx.de > Cc: Andre Przywara <andre.przywara(a)arm.com>; Anup Patel <apatel(a)ventanamicro.com>; Jonas Schwöbel <jonasschwoebel(a)yahoo.de>; Kautuk Consul <kconsul(a)ventanamicro.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; Michael Walle <michael(a)walle.cc>; Michal Simek <michal.simek(a)amd.com>; Nikita Shubin <n.shubin(a)yadro.com>; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Sean Anderson <seanga2(a)gmail.com>; Sergei Antonov <saproj(a)gmail.com>; Simon Glass <sjg(a)chromium.org>; Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com>; Svyatoslav Ryhel <clamor95(a)gmail.com>; Tianrui Wei <tianrui-wei(a)outlook.com>; William Zhang <william.zhang(a)broadcom.com>; Yanhong Wang <yanhong.wang(a)starfivetech.com>; Peter Yu-Chien Lin(林宇謙) <peterlin(a)andestech.com> > Subject: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT > > As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. > > Signed-off-by: Bin Meng <bmeng(a)tinylab.org> > > --- > > MAINTAINERS | 2 +- > arch/riscv/Kconfig | 8 ++++---- > arch/riscv/cpu/fu540/Kconfig | 2 +- > arch/riscv/cpu/fu740/Kconfig | 2 +- > arch/riscv/cpu/generic/Kconfig | 4 ++-- > arch/riscv/cpu/jh7110/Kconfig | 2 +- > arch/riscv/include/asm/global_data.h | 4 ++-- > arch/riscv/include/asm/syscon.h | 2 +- > arch/riscv/lib/Makefile | 2 +- > .../lib/{sifive_clint.c => aclint_ipi.c} | 16 +++++++-------- > board/openpiton/riscv64/Kconfig | 2 +- > board/sipeed/maix/Kconfig | 2 +- > drivers/timer/Makefile | 2 +- > ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +++++++++---------- > 14 files changed, 35 insertions(+), 35 deletions(-) rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%) rename drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint
by Rick Chen 15 Jun '23

15 Jun '23

> From: Bin Meng <bmeng(a)tinylab.org> > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot(a)lists.denx.de > Cc: Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com> > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint > > This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. > > The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. > > [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc > > Signed-off-by: Bin Meng <bmeng(a)tinylab.org> LGTM. Thanks, Rick

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[PATCH v2 1/3] mmc: Fix MMC_CMD_STOP_TRANSMISSION response type and add comment
by Marek Vasut 15 Jun '23

15 Jun '23

The MMC_CMD_STOP_TRANSMISSION response is R1 for read transfers per JEDEC Standard No. 84-B51 Page 126 . Correct the response type and add a comment about it. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- V2: New patch --- Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Cc: Hai Pham <hai.pham.ud(a)renesas.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Loic Poulain <loic.poulain(a)linaro.org> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Takeshi Kihara <takeshi.kihara.df(a)renesas.com> --- drivers/mmc/mmc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 965bc8f0dba..f9b2f940389 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -427,7 +427,12 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, if (blkcnt > 1) { cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; cmd.cmdarg = 0; - cmd.resp_type = MMC_RSP_R1b; + /* + * JEDEC Standard No. 84-B51 Page 126 + * CMD12 STOP_TRANSMISSION R1/R1b[3] + * NOTE 3 R1 for read cases and R1b for write cases. + */ + cmd.resp_type = MMC_RSP_R1; if (mmc_send_cmd(mmc, &cmd, NULL)) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) pr_err("mmc fail to send stop cmd\n"); -- 2.39.2

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[PATCH] rockchip: Pinephone Pro: Add DDR RAM type config
by Peter Robinson 14 Jun '23

14 Jun '23

Add the RAM_ROCKCHIP_LPDDR4 to fix the Pinephone Pro booting. When the configs were updated in 26f92be07e2 it somehow broke the PPP boot process so let's fix it. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> CC: Jagan Teki <jagan(a)edgeble.ai> CC: Kever Yang <kever.yang(a)rock-chips.com> --- configs/pinephone-pro-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 4edea88665f..e4a8beeb1ab 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -73,6 +73,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 -- 2.41.0

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