March 2023 - U-Boot

[PATCH] arm: mach-k3: am642: move do_dt_magic() after sysfw loading
by Christian Gmeiner 25 Apr '23

25 Apr '23

Makes it possible to use e.g mcu_spi0 for custom board detection. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- arch/arm/mach-k3/am642_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 96f292ea75..2478ac162b 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -185,8 +185,6 @@ void board_init_f(ulong dummy) preloader_console_init(); - do_dt_magic(); - #if defined(CONFIG_K3_LOAD_SYSFW) /* * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue @@ -213,6 +211,8 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + do_dt_magic(); + #if defined(CONFIG_ESM_K3) /* Probe/configure ESM0 */ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); -- 2.40.0

3 3

[PATCH] Revert "fdtdec: drop needlessly convoluted CONFIG_PHANDLE_CHECK_SEQ"
by Simon Glass 24 Apr '23

24 Apr '23

The fdt_path_offset() function is slow since it must scan the tree. This substantial overhead now applies to all boards. The original code may not be ideal but it is fit for purpose and is only needed on a few boards. We should revert this in time for the release. This reverts commit 26f981f295d00351b6f0c69b5317b254b2361cc0. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- configs/am65x_evm_a53_defconfig | 1 + configs/evb-ast2600_defconfig | 1 + configs/sama7g5ek_mmc1_defconfig | 1 + configs/sama7g5ek_mmc_defconfig | 1 + lib/Kconfig | 7 +++++++ lib/fdtdec.c | 7 +++++-- 6 files changed, 16 insertions(+), 2 deletions(-) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 65e41e5b6af..9c088e1d02e 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -180,3 +180,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index 5c4d8426607..f337128abb3 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -90,3 +90,4 @@ CONFIG_WDT=y CONFIG_SHA384=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index 20ca98821a0..16b138ff93d 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -80,3 +80,4 @@ CONFIG_TIMER=y CONFIG_MCHP_PIT64B_TIMER=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER_HII is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index c9f62a8ebe5..c08c889c04f 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -80,3 +80,4 @@ CONFIG_TIMER=y CONFIG_MCHP_PIT64B_TIMER=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER_HII is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/lib/Kconfig b/lib/Kconfig index c9f9ddce7d0..223b63cff52 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -960,4 +960,11 @@ config LMB_RESERVED_REGIONS Define the number of supported reserved regions in the library logical memory blocks. +config PHANDLE_CHECK_SEQ + bool "Enable phandle check while getting sequence number" + help + When there are multiple device tree nodes with same name, + enable this config option to distinguish them using + phandles in fdtdec_get_alias_seq() function. + endmenu diff --git a/lib/fdtdec.c b/lib/fdtdec.c index ffa78f97ca0..e20f6aad9c2 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -516,8 +516,11 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int offset, * Adding an extra check to distinguish DT nodes with * same name */ - if (offset != fdt_path_offset(blob, prop)) - continue; + if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) { + if (fdt_get_phandle(blob, offset) != + fdt_get_phandle(blob, fdt_path_offset(blob, prop))) + continue; + } val = trailing_strtol(name); if (val != -1) { -- 2.37.0.rc0.161.g10f37bed90-goog

3 11

[PATCH v3 00/25] bootstd: Add a boot menu
by Simon Glass 24 Apr '23

24 Apr '23

So far standard boot lacks a boot menu, although it is possible to create a rudimentary one using the existing 'bootmenu' command. Even then, this text-based menu offer only basic functionality and does not take full advantage of the displays which are common on many devices. This series provides a 'bootflow menu' command which allows the user to select from the available bootflows. An attempt is made to show the name of the available operating systems, by reading more information into the bootflow. A logo can be read also, where supported, so that this can be presented to the user when an option is highlighted. Full use is made of TrueType fonts, if enabled. For cases where only a serial console is available, it falls back to a simple text-based menu. All of this is implementing using a new 'expo' construct, a collection of scenes (like menu screens) which can be navigated by the user to view information and select options. This is fairly general and should be able to cope with a wider array of use cases, with less hacking of the menu code, such as is currently needed for CMD_BOOTEFI_BOOTMGR. Of course it would be possible to enhance the existing menu rather than creating a new setup. Instead it seems better to make the existing menu use expo, if code space permits. It avoids the event-loop problem and should be more extensible, given its loosely coupled components and use of IDs instead of pointers. Further motivation is provided in the documentation. For now the CLI keypress-decoding code is split out to be used by the new menu. The key codes defined by menu.h are reused also. This is of course just a starting point. Some ideas for future work are included in the documentation. Changes in v3: - Rebase to master Changes in v2: - Drop the _add suffix on expo creation function - Fix 'touse' typo - Fix pylint warning in mkdir_cond() - Put strings in a separate structure referenced by ID - Rebase to master - Rename vidconsole_get_font() to vidconsole_get_font_size() - Update for new API Simon Glass (25): sandbox: Enable mmc command and legacy images cli: Move readline character-processing to a state machine bootmenu: Add a few comments menu: Rename KEY_... to BKEY_... menu: Update bootmenu_autoboot_loop() to return the code menu: Update bootmenu_loop() to return the code menu: Use a switch statement menu: Make use of CLI character processing image: Add a function to find a script in an image image: Move common image code to image_board and command video: Enable VIDEO_ANSI by default only with EFI video: truetype: Rename the metrics function video: Fix unchnaged typo video: Add font functions to the vidconsole API bootstd: Read the Operating System name for distro/scripts bootstd: Allow reading a logo for the OS menu: Factor out menu-keypress decoding expo: Add basic implementation expo: Add support for scenes expo: Add support for scene menus expo: Add basic tests bootstd: Support creating a boot menu bootstd: Add a test for the bootstd menu bootstd: Support setting a theme for the menu expo: Add documentation .../cmd_stm32prog/cmd_stm32prog.c | 2 +- arch/sandbox/dts/test.dts | 11 + boot/Kconfig | 12 + boot/Makefile | 3 + boot/bootflow.c | 1 + boot/bootflow_internal.h | 47 ++ boot/bootflow_menu.c | 284 +++++++++ boot/bootmeth-uclass.c | 69 ++- boot/bootmeth_distro.c | 36 ++ boot/bootmeth_script.c | 40 +- boot/bootstd-uclass.c | 2 + boot/expo.c | 170 ++++++ boot/image-board.c | 133 +++++ boot/scene.c | 414 ++++++++++++++ boot/scene_internal.h | 123 ++++ boot/scene_menu.c | 390 +++++++++++++ cmd/bootflow.c | 44 +- cmd/bootmenu.c | 19 +- cmd/eficonfig.c | 38 +- cmd/font.c | 11 +- cmd/source.c | 140 +---- common/Makefile | 6 +- common/cli_getch.c | 208 +++++++ common/cli_readline.c | 150 +---- common/command.c | 19 + common/menu.c | 157 +++-- configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 2 + configs/snow_defconfig | 4 + configs/tools-only_defconfig | 2 + doc/develop/expo.rst | 188 ++++++ doc/develop/index.rst | 1 + drivers/usb/gadget/f_sdp.c | 2 +- drivers/video/Kconfig | 7 +- drivers/video/console_truetype.c | 37 +- drivers/video/vidconsole-uclass.c | 33 ++ include/bootflow.h | 40 ++ include/bootmeth.h | 16 + include/bootstd.h | 4 + include/cli.h | 74 +++ include/command.h | 12 + include/expo.h | 521 +++++++++++++++++ include/image.h | 17 +- include/menu.h | 77 ++- include/video.h | 2 +- include/video_console.h | 75 ++- test/boot/Makefile | 2 + test/boot/bootflow.c | 130 +++++ test/boot/expo.c | 539 ++++++++++++++++++ test/cmd/font.c | 6 +- test/py/tests/bootstd/armbian.bmp.xz | Bin 0 -> 1384 bytes test/py/tests/bootstd/mmc4.img.xz | Bin 0 -> 7072 bytes test/py/tests/test_android/test_avb.py | 2 + test/py/tests/test_ut.py | 218 ++++++- 54 files changed, 4075 insertions(+), 467 deletions(-) create mode 100644 boot/bootflow_internal.h create mode 100644 boot/bootflow_menu.c create mode 100644 boot/expo.c create mode 100644 boot/scene.c create mode 100644 boot/scene_internal.h create mode 100644 boot/scene_menu.c create mode 100644 common/cli_getch.c create mode 100644 doc/develop/expo.rst create mode 100644 include/expo.h create mode 100644 test/boot/expo.c create mode 100644 test/py/tests/bootstd/armbian.bmp.xz create mode 100644 test/py/tests/bootstd/mmc4.img.xz -- 2.39.0.314.g84b9a713c41-goog

5 39

[PATCH v2 00/18] virtio: pci: Add and fix consistency checks
by Andrew Scull 24 Apr '23

24 Apr '23

The virtio PCI drivers forgo a number of consistency checks, particularly around pointer validation and bounds checking. This series focuses on the modern driver to add those checks. The start of the series adds and fixes some basic bounds checks. Later patches ensure PCI addresses fall within the expected regions rather than any arbitrary address. This is acheived by introducing range parameters to a few of the dm_pci_* functions that allow the ranges to be checked. The series also adds a few new configs to allow parts of virtio and PCI to be disabled where the features may be unused and the current implementations don't have the needed consistencty checks. Changelog: v2: - Refactor dm_pci_* functions, not adding new ones - Reorder patches per request in v1 Andrew Scull (18): virtio: pci: Allow exclusion of legacy driver virtio: pci: Fix discovery of device config length virtio: pci: Bounds check device config access virtio: pci: Bounds check notification writes virtio: pci: Check virtio common config size virtio: pci: Check virtio capability is in bounds virtio: pci: Read entire capability into memory pci: Fix use of flags in dm_pci_map_bar() pci: Add config for Enhanced Allocation pci: Check region ranges are addressable pci: Range check address conversions test: pci: Test PCI address conversion functions pci: Map bars with offset and length pci: Match region flags using a mask pci: Update dm_pci_bus_to_virt() parameters pci: Add mask parameter to dm_pci_map_bar() virtio: pci: Check virtio configs are mapped virtio: pci: Make use of dm_pci_map_bar() arch/sandbox/dts/test.dts | 2 +- arch/x86/cpu/baytrail/cpu.c | 2 +- drivers/ata/ahci.c | 9 +- drivers/bios_emulator/atibios.c | 4 +- drivers/gpio/octeon_gpio.c | 2 +- drivers/i2c/designware_i2c_pci.c | 3 +- drivers/i2c/intel_i2c.c | 2 +- drivers/i2c/octeon_i2c.c | 2 +- drivers/mmc/octeontx_hsmmc.c | 2 +- drivers/mmc/pci_mmc.c | 2 +- drivers/mtd/nand/raw/octeontx_bch.c | 6 +- drivers/mtd/nand/raw/octeontx_nand.c | 2 +- drivers/net/bnxt/bnxt.c | 9 +- drivers/net/fsl_enetc.c | 2 +- drivers/net/fsl_enetc_mdio.c | 2 +- drivers/net/mscc_eswitch/felix_switch.c | 4 +- drivers/net/octeontx/bgx.c | 2 +- drivers/net/octeontx/nic_main.c | 2 +- drivers/net/octeontx/nicvf_main.c | 2 +- drivers/net/octeontx/smi.c | 2 +- drivers/net/octeontx2/cgx.c | 2 +- drivers/net/octeontx2/rvu_af.c | 2 +- drivers/net/octeontx2/rvu_pf.c | 3 +- drivers/net/pch_gbe.c | 2 +- drivers/nvme/nvme_pci.c | 4 +- drivers/pci/Kconfig | 7 + drivers/pci/pci-uclass.c | 197 +++++++++++------------- drivers/spi/octeon_spi.c | 2 +- drivers/usb/host/ohci-pci.c | 2 +- drivers/virtio/Kconfig | 9 ++ drivers/virtio/Makefile | 3 +- drivers/virtio/virtio_pci_legacy.c | 3 +- drivers/virtio/virtio_pci_modern.c | 143 +++++++++++------ include/pci.h | 49 ++++-- test/dm/pci.c | 118 +++++++++++++- 35 files changed, 399 insertions(+), 210 deletions(-) -- 2.35.1.1021.g381101b075-goog

6 48

[PATCH v2] nand: brcmnand: add iproc support
by Linus Walleij 22 Apr '23

22 Apr '23

Add support for the iproc Broadcom NAND controller, used in Northstar SoCs for example. Based on the Linux driver. Cc: Philippe Reynes <philippe.reynes(a)softathome.com> Cc: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael(a)amarulasolutions.com> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v1->v2: - Check return value of dev_read_resource() - Use devm_ioremap() - Collect Michael's Review tag --- drivers/mtd/nand/raw/Kconfig | 7 + drivers/mtd/nand/raw/brcmnand/Makefile | 1 + drivers/mtd/nand/raw/brcmnand/iproc_nand.c | 148 +++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/mtd/nand/raw/brcmnand/iproc_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5b35da45f584..6a13bc1e228a 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -156,6 +156,13 @@ config NAND_BRCMNAND_63158 help Enable support for broadcom nand driver on bcm63158. +config NAND_BRCMNAND_IPROC + bool "Support Broadcom NAND controller on the iproc family" + depends on NAND_BRCMNAND + help + Enable support for broadcom nand driver on the Broadcom + iproc family such as Northstar (BCM5301x, BCM4708...) + config NAND_DAVINCI bool "Support TI Davinci NAND controller" select SYS_NAND_SELF_INIT if TARGET_DA850EVM diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index f46a7edae321..0c6325aaa618 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o +obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o diff --git a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c new file mode 100644 index 000000000000..69711d98ce1b --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Code borrowed from the Linux driver + * Copyright (C) 2015 Broadcom Corporation + */ + +#include <common.h> +#include <asm/io.h> +#include <memalign.h> +#include <nand.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <dm.h> + +#include "brcmnand.h" + +struct iproc_nand_soc { + struct brcmnand_soc soc; + void __iomem *idm_base; + void __iomem *ext_base; +}; + +#define IPROC_NAND_CTLR_READY_OFFSET 0x10 +#define IPROC_NAND_CTLR_READY BIT(0) + +#define IPROC_NAND_IO_CTRL_OFFSET 0x00 +#define IPROC_NAND_APB_LE_MODE BIT(24) +#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6) + +static bool iproc_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct iproc_nand_soc *priv = + container_of(soc, struct iproc_nand_soc, soc); + void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET; + u32 val = brcmnand_readl(mmio); + + if (val & IPROC_NAND_CTLR_READY) { + brcmnand_writel(IPROC_NAND_CTLR_READY, mmio); + return true; + } + + return false; +} + +static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct iproc_nand_soc *priv = + container_of(soc, struct iproc_nand_soc, soc); + void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET; + u32 val = brcmnand_readl(mmio); + + if (en) + val |= IPROC_NAND_INT_CTRL_READ_ENABLE; + else + val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE; + + brcmnand_writel(val, mmio); +} + +static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare, + bool is_param) +{ + struct iproc_nand_soc *priv = + container_of(soc, struct iproc_nand_soc, soc); + void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET; + u32 val; + + val = brcmnand_readl(mmio); + + /* + * In the case of BE or when dealing with NAND data, always configure + * the APB bus to LE mode before accessing the FIFO and back to BE mode + * after the access is done + */ + if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN) || !is_param) { + if (prepare) + val |= IPROC_NAND_APB_LE_MODE; + else + val &= ~IPROC_NAND_APB_LE_MODE; + } else { /* when in LE accessing the parameter page, keep APB in BE */ + val &= ~IPROC_NAND_APB_LE_MODE; + } + + brcmnand_writel(val, mmio); +} + +static int iproc_nand_probe(struct udevice *dev) +{ + struct udevice *pdev = dev; + struct iproc_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc; + struct resource res; + int ret; + + soc = &priv->soc; + + ret = dev_read_resource_byname(pdev, "iproc-idm", &res); + if (ret) + return ret; + + priv->idm_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->idm_base)) + return PTR_ERR(priv->idm_base); + + ret = dev_read_resource_byname(pdev, "iproc-ext", &res); + if (ret) + return ret; + + priv->ext_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->ext_base)) + return PTR_ERR(priv->ext_base); + + soc->ctlrdy_ack = iproc_nand_intc_ack; + soc->ctlrdy_set_enabled = iproc_nand_intc_set; + soc->prepare_data_bus = iproc_nand_apb_access; + + return brcmnand_probe(pdev, soc); +} + +static const struct udevice_id iproc_nand_dt_ids[] = { + { + .compatible = "brcm,nand-iproc", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(iproc_nand) = { + .name = "iproc-nand", + .id = UCLASS_MTD, + .of_match = iproc_nand_dt_ids, + .probe = iproc_nand_probe, + .priv_auto = sizeof(struct iproc_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(iproc_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} -- 2.39.1

4 8

[PATCH] board: rockchip: add Anbernic RGXX3 Series Devices
by Chris Morgan 21 Apr '23

21 Apr '23

From: Chris Morgan <macromorgan(a)hotmail.com> The Anbernic RGxx3 is a "pseudo-device" that encompasses the following devices: - Anbernic RG353M - Anbernic RG353P - Anbernic RG353V - Anbernic RG353VS - Anbernic RG503 The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that is used for all RGxx3 devices. Via the board.c file, the bootloader automatically sets the correct fdtfile, board, and board_name environment variables so that the correct devicetree can be passed to Linux. It is also possible to simply hard-code a single devicetree in the boot.scr file and use that to load Linux as well. The common specifications for each device are: - Rockchip RK3566 SoC - 2 external SDMMC slots - 1 USB-C host port, 1 USB-C peripheral port - 1 mini-HDMI output - MIPI-DSI based display panel - ADC controlled joysticks with a GPIO mux - GPIO buttons - A PWM controlled vibrator - An ADC controlled button All of the common features are defined in the devicetree synced from upstream Linux. TODO: DSI panel auto-detection for the RG353 devices (requires porting of DSI controller driver and DSI-DPHY driver to send DSI commands to the panel). Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- arch/arm/dts/Makefile | 1 + .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 85 ++ arch/arm/dts/rk3566-anbernic-rgxx3.dts | 18 + arch/arm/dts/rk3566-anbernic-rgxx3.dtsi | 786 ++++++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 14 + board/anbernic/rgxx3_rk3566/Kconfig | 15 + board/anbernic/rgxx3_rk3566/MAINTAINERS | 6 + board/anbernic/rgxx3_rk3566/Makefile | 6 + board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 203 +++++ configs/anbernic-rgxx3_defconfig | 78 ++ doc/board/anbernic/index.rst | 9 + doc/board/anbernic/rgxx3.rst | 47 ++ doc/board/index.rst | 1 + doc/board/rockchip/rockchip.rst | 3 + include/configs/anbernic-rgxx3-rk3566.h | 12 + 15 files changed, 1284 insertions(+) create mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3.dts create mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3.dtsi create mode 100644 board/anbernic/rgxx3_rk3566/Kconfig create mode 100644 board/anbernic/rgxx3_rk3566/MAINTAINERS create mode 100644 board/anbernic/rgxx3_rk3566/Makefile create mode 100644 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c create mode 100644 configs/anbernic-rgxx3_defconfig create mode 100644 doc/board/anbernic/index.rst create mode 100644 doc/board/anbernic/rgxx3.rst create mode 100644 include/configs/anbernic-rgxx3-rk3566.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c160e884bf..74dd55f700 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ rk3568-evb.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-rock-3a.dtb diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi new file mode 100644 index 0000000000..2ae8186228 --- /dev/null +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0; + }; + + rng: rng@fe388000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xfe388000 0x0 0x2000>; + status = "okay"; + }; +}; + +&cru { + assigned-clocks = + <&pmucru CLK_RTC_32K>, + <&pmucru PLL_PPLL>, + <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, + <&cru PLL_GPLL>, + <&cru ACLK_BUS>, <&cru PCLK_BUS>, + <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, + <&cru HCLK_TOP>, <&cru PCLK_TOP>, + <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, + <&cru CPLL_500M>, <&cru CPLL_333M>, + <&cru CPLL_250M>, <&cru CPLL_125M>, + <&cru CPLL_100M>, <&cru CPLL_62P5M>, + <&cru CPLL_50M>, <&cru CPLL_25M>; + assigned-clock-rates = + <32768>, + <200000000>, + <100000000>, <1000000000>, + <1188000000>, + <150000000>, <100000000>, + <500000000>, <400000000>, + <150000000>, <100000000>, + <300000000>, <150000000>, + <500000000>, <333333333>, + <250000000>, <125000000>, + <100000000>, <62500000>, + <50000000>, <25000000>; + assigned-clock-parents = + <&pmucru CLK_RTC32K_FRAC>; +}; + +&i2c2 { + status = "okay"; +}; + +&pmucru { + assigned-clocks = <&pmucru SCLK_32K_IOE>; + assigned-clock-parents = <&pmucru CLK_RTC_32K>; +}; + +/* + * We don't need the clocks, but if they are present they may cause + * probing to fail so we remove them for U-Boot. + */ +&rk817 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ clocks; + /delete-property/ clock-names; +}; + +&sdhci { + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; + pinctrl-names = "default"; + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-spl; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts new file mode 100644 index 0000000000..404dddfafb --- /dev/null +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-anbernic-rgxx3.dtsi" + +/ { + +/* + * Note this is a pseudo-model that doesn't exist in mainline Linux. + * This model is used for all RGXX3 devices and the board.c file will + * set the correct dtb name for loading mainline Linux automatically. + */ + model = "RGXX3"; + compatible = "anbernic,rg353m", "anbernic,rg353p", + "anbernic,rg353v", "anbernic,rg353vs", + "anbernic,rg503", "rockchip,rk3566"; +}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi new file mode 100644 index 0000000000..ad43fa199c --- /dev/null +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi @@ -0,0 +1,786 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_X>; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_RX>; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_Y>; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_RY>; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <60>; + + /* + * Button is mapped to F key in BSP kernel, but + * according to input guidelines it should be mode. + */ + button-mode { + label = "MODE"; + linux,code = <BTN_MODE>; + press-threshold-microvolt = <1750>; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + + gpio_keys_control: gpio-keys-control { + compatible = "gpio-keys"; + pinctrl-0 = <&btn_pins_ctrl>; + pinctrl-names = "default"; + + button-b { + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + label = "SOUTH"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-l1 { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + label = "TL"; + linux,code = <BTN_TL>; + }; + + button-l2 { + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + label = "TL2"; + linux,code = <BTN_TL2>; + }; + + button-select { + gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + label = "SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-start { + gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + label = "START"; + linux,code = <BTN_START>; + }; + + button-thumbl { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = <BTN_THUMBL>; + }; + + button-thumbr { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = <BTN_THUMBR>; + }; + + button-up { + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + label = "NORTH"; + linux,code = <BTN_NORTH>; + }; + }; + + gpio_keys_vol: gpio-keys-vol { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&btn_pins_vol>; + pinctrl-names = "default"; + + button-vol-down { + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + label = "VOLUMEDOWN"; + linux,code = <KEY_VOLUMEDOWN>; + }; + + button-vol-up { + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + label = "VOLUMEUP"; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, + <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + ddc-i2c-bus = <&i2c5>; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + + amber_led: led-1 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_CHARGING; + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + }; + + red_led: led-2 { + color = <LED_COLOR_ID_RED>; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&vcc_lcd_h>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_lcd0_n"; + vin-supply = <&vcc_3v3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sys: regulator-vcc-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-name = "vcc_sys"; + }; + + vcc_wifi: regulator-vcc-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_wifi_h>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_wifi"; + }; + + vibrator: pwm-vibrator { + compatible = "pwm-vibrator"; + pwm-names = "enable"; + pwms = <&pwm5 0 1000000000 0>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-0 = <&hdmitxm0_cec>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "fcs,fan53555"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + /* Unknown/unused device at 0x3c */ + status = "disabled"; +}; + +&i2c5 { + pinctrl-0 = <&i2c5m1_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + pinctrl-names = "default"; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pinctrl { + gpio-btns { + btn_pins_ctrl: btn-pins-ctrl { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + btn_pins_vol: btn-pins-vol { + rockchip,pins = + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-led { + led_pins: led-pins { + rockchip,pins = + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + joy-mux { + joy_mux_en: joy-mux-en { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc3v3-lcd { + vcc_lcd_h: vcc-lcd-h { + rockchip,pins = + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-wifi { + vcc_wifi_h: vcc-wifi-h { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm5 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + pinctrl-names = "default"; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>; + pinctrl-names = "default"; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc1v8_dvp>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart2 { + status = "okay"; +}; + +/* + * Lack the schematics to verify, but port works as a peripheral + * (and not a host or OTG port). + */ +&usb_host0_xhci { + dr_mode = "peripheral"; + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 4e7c02cce0..94e04b79e7 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -1,11 +1,24 @@ if ROCKCHIP_RK3568 +choice + prompt "RK3568/RK3566 board select" + config TARGET_EVB_RK3568 bool "RK3568 evaluation board" select BOARD_LATE_INIT help RK3568 EVB is a evaluation board for Rockchp RK3568. +config TARGET_ANBERNIC_RGXX3_RK3566 + bool "Anbernic RGXX3" + help + Anbernic RGXX3 gaming device with Rockchip RK3566. This + config can be used with the RG353M, RG353P, RG353V, RG353VS, + and RG503. The correct device tree name will automatically + be selected by the bootloader. + +endchoice + config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 @@ -19,5 +32,6 @@ config SYS_MALLOC_F_LEN default 0x2000 source "board/rockchip/evb_rk3568/Kconfig" +source "board/anbernic/rgxx3_rk3566/Kconfig" endif diff --git a/board/anbernic/rgxx3_rk3566/Kconfig b/board/anbernic/rgxx3_rk3566/Kconfig new file mode 100644 index 0000000000..6743a28a2f --- /dev/null +++ b/board/anbernic/rgxx3_rk3566/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ANBERNIC_RGXX3_RK3566 + +config SYS_BOARD + default "rgxx3_rk3566" + +config SYS_VENDOR + default "anbernic" + +config SYS_CONFIG_NAME + default "anbernic-rgxx3-rk3566" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/anbernic/rgxx3_rk3566/MAINTAINERS b/board/anbernic/rgxx3_rk3566/MAINTAINERS new file mode 100644 index 0000000000..647e49d28a --- /dev/null +++ b/board/anbernic/rgxx3_rk3566/MAINTAINERS @@ -0,0 +1,6 @@ +RGXX3-RK3566 +M: Chris Morgan <macromorgan(a)hotmail.com> +S: Maintained +F: board/anbernic/rgxx3-rk3566 +F: include/configs/anbernic-rgxx3-rk3566 +F: configs/anbernic-rgxx3_defconfig diff --git a/board/anbernic/rgxx3_rk3566/Makefile b/board/anbernic/rgxx3_rk3566/Makefile new file mode 100644 index 0000000000..afd3e0adf6 --- /dev/null +++ b/board/anbernic/rgxx3_rk3566/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Chris Morgan <macromorgan(a)hotmail.com> +# + +obj-y += rgxx3-rk3566.o diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c new file mode 100644 index 0000000000..decc46db78 --- /dev/null +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Chris Morgan <macromorgan(a)hotmail.com> + */ + +#include <abuf.h> +#include <adc.h> +#include <asm/io.h> +#include <dm.h> +#include <linux/delay.h> +#include <pwm.h> +#include <rng.h> +#include <stdlib.h> +#include <mmc.h> +#include <env.h> + +#define GPIO0_BASE 0xfdd60000 +#define GPIO_SWPORT_DR_H 0x0004 +#define GPIO_SWPORT_DDR_H 0x000c +#define GPIO_A5 BIT(5) +#define GPIO_A6 BIT(6) + +#define GPIO_WRITEMASK(bits) ((bits) << 16) + +#define DTB_DIR "rockchip/" + +struct rg3xx_model { + const char *board; + const char *board_name; + const char *fdtfile; +}; + +enum rgxx3_device_id { + RG353M, + RG353P, + RG353V, + RG353VS, + RG503, +}; + +static const struct rg3xx_model rg3xx_model_details[] = { + [RG353M] = { + "rk3566-anbernic-rg353m", + "RG353M", + DTB_DIR "rk3566-anbernic-rg353m.dtb", + }, + [RG353P] = { + "rk3566-anbernic-rg353p", + "RG353P", + DTB_DIR "rk3566-anbernic-rg353p.dtb", + }, + [RG353V] = { + "rk3566-anbernic-rg353v", + "RG353V", + DTB_DIR "rk3566-anbernic-rg353v.dtb", + }, + [RG353VS] = { + "rk3566-anbernic-rg353vs", + "RG353VS", + DTB_DIR "rk3566-anbernic-rg353vs.dtb", + }, + [RG503] = { + "rk3566-anbernic-rg503", + "RG503", + DTB_DIR "rk3566-anbernic-rg503.dtb", + }, +}; + +/* + * Start LED very early so user knows device is on. Set color + * to amber. + */ +void spl_board_init(void) +{ + /* Set GPIO0_A5 and GPIO0_A6 to output. */ + writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5), + (GPIO0_BASE + GPIO_SWPORT_DDR_H)); + /* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */ + writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6, + (GPIO0_BASE + GPIO_SWPORT_DR_H)); +} + +/* Use hardware rng to seed Linux random. */ +int board_rng_seed(struct abuf *buf) +{ + struct udevice *dev; + size_t len = 0x8; + u64 *data; + + data = malloc(len); + if (!data) { + printf("Out of memory\n"); + return -ENOMEM; + } + + if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { + printf("No RNG device\n"); + return -ENODEV; + } + + if (dm_rng_read(dev, data, len)) { + printf("Reading RNG failed\n"); + return -EIO; + } + + abuf_init_set(buf, data, len); + + return 0; +} + +/* + * Buzz the buzzer so the user knows something is going on. Make it + * optional in case PWM is disabled. + */ +void __maybe_unused startup_buzz(void) +{ + struct udevice *dev; + int err; + + err = uclass_get_device(UCLASS_PWM, 0, &dev); + if (err) + printf("pwm not found\n"); + + pwm_set_enable(dev, 0, 1); + mdelay(200); + pwm_set_enable(dev, 0, 0); +} + +/* Detect which Anbernic RGXX3 device we are using so as to load the + * correct devicetree for Linux. Set an environment variable once + * found. The detection depends on the value of ADC channel 1, the + * presence of an eMMC on mmc0, and querying the DSI panel (TODO). + */ +int rgxx3_detect_device(void) +{ + u32 adc_info; + int ret; + int board_id = -ENXIO; + struct mmc *mmc; + + ret = adc_channel_single_shot("saradc@fe720000", 1, &adc_info); + if (ret) { + printf("Read SARADC failed with error %d\n", ret); + return ret; + } + + /* Observed value 517. */ + if (adc_info > 505 && adc_info < 530) + board_id = RG353M; + /* Observed value 695. */ + if (adc_info > 680 && adc_info < 710) + board_id = RG353V; + /* Documented value 860. */ + if (adc_info > 850 && adc_info < 870) + board_id = RG353P; + /* Observed value 1023. */ + if (adc_info > 1010) + board_id = RG503; + + /* + * Try to access the eMMC on an RG353V. If it's missing, it's + * an RG353VS. Note we could also check for a touchscreen at + * 0x1a on i2c2. + */ + if (board_id == RG353V) { + mmc = find_mmc_device(0); + if (mmc) { + ret = mmc_init(mmc); + if (ret) + board_id = RG353VS; + } + } + + if (board_id < 0) + return board_id; + + env_set("board", rg3xx_model_details[board_id].board); + env_set("board_name", + rg3xx_model_details[board_id].board_name); + env_set("fdtfile", rg3xx_model_details[board_id].fdtfile); + + return 0; +} + +int rk_board_late_init(void) +{ + int ret; + + /* Turn off orange LED and turn on green LED. */ + writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A5, + (GPIO0_BASE + GPIO_SWPORT_DR_H)); + + ret = rgxx3_detect_device(); + if (ret) { + printf("Unable to detect device type: %d\n", ret); + return ret; + } + + if (IS_ENABLED(CONFIG_DM_PWM)) + startup_buzz(); + + return 0; +} diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3_defconfig new file mode 100644 index 0000000000..b17e917914 --- /dev/null +++ b/configs/anbernic-rgxx3_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ARM_SMCCC_FEATURES=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_DM_REGULATOR_SCMI=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_REGEX=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/anbernic/index.rst b/doc/board/anbernic/index.rst new file mode 100644 index 0000000000..beddc26e4c --- /dev/null +++ b/doc/board/anbernic/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Anbernic +===== + +.. toctree:: + :maxdepth: 2 + + rgxx3.rst diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst new file mode 100644 index 0000000000..42bd4e29ba --- /dev/null +++ b/doc/board/anbernic/rgxx3.rst @@ -0,0 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Anbernic RGxx3 Devices +============================= + +This allows U-Boot to boot the following Anbernic devices: + + - Anbernic RG353M + - Anbernic RG353P + - Anbernic RG353V + - Anbernic RG353VS + - Anbernic RG503 + +The correct device is detected automatically by comparing ADC values +from ADC channel 1. In the event of an RG353V, an attempt is then made +to probe for an eMMC and if it fails the device is assumed to be an +RG353VS. Based on the detected device, the environment variables +"board", "board_name", and "fdtfile" are set to the correct values +corresponding to the board which can be read by a boot script to boot +with the correct device tree. + +Please note that there are some versions of the RG353 devices with +different panels. Panel auto-detection is planned for a later date. + +Building U-Boot +--------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf + $ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin + $ make anbernic-rgxx3_defconfig + $ make + +This will build ``u-boot-rockchip.bin`` which can be written to an SD +card. + +Image installation +------------------ + +Write the ``u-boot-rockchip.bin`` to an SD card offset 32kb from the +start. + +.. code-block:: bash + + $ dd if=u-boot-rockchip.bin of=/dev/mmcblk0 bs=512 seek=64 diff --git a/doc/board/index.rst b/doc/board/index.rst index 618d22e616..0420f0ef7f 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -11,6 +11,7 @@ Board-specific doc AndesTech/index allwinner/index amlogic/index + anbernic/index apple/index armltd/index atmel/index diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b5563b8f7f..204cace1e9 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -87,6 +87,9 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3399 (evb_rk3399) - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399) +* rk3566 + - Anbernic RGxx3 (rgxx3-rk3566) + * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) diff --git a/include/configs/anbernic-rgxx3-rk3566.h b/include/configs/anbernic-rgxx3-rk3566.h new file mode 100644 index 0000000000..3c4ea4e7d8 --- /dev/null +++ b/include/configs/anbernic-rgxx3-rk3566.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ANBERNIC_RGXX3_RK3566_H +#define __ANBERNIC_RGXX3_RK3566_H + +#include <configs/rk3568_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif -- 2.34.1

2 3

[PATCH] suniv: fix dramc autofresh freq calculation issue
by John Sanpe 21 Apr '23

21 Apr '23

External use mhz to express frequency, autofresh use hz, no unit conversion is performed when calling, cause dram instability at low frequency. Incorporated xboot repair patch for this driver. Signed-off-by: John Sanpe <sanpeqf(a)gmail.com> --- arch/arm/mach-sunxi/dram_suniv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 3aa3ce7627..830fa7895d 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -310,7 +310,7 @@ static u32 dram_get_dram_size(struct dram_para *para) para->size = 64; else para->size = 32; - dram_set_autofresh_cycle(para->clk); + dram_set_autofresh_cycle(para->clk * 1000000); para->access_mode = 0; dram_para_setup(para); -- 2.39.2

2 1

[PATCH 00/38] x86: Use qemu-x86_64 to boot EFI installers
by Simon Glass 20 Apr '23

20 Apr '23

This series adds various minor features so that qemu-x86_64 can boot the Ubuntu 2022.04 installer using a virtio device: qemu-system-x86_64 -M pc -drive format=raw,file=root.img -bios /tmp/b/qemu-x86_64/u-boot.rom -drive if=virtio,file=ubuntu-22.04.2-desktop-amd64.iso -smp 4 -m 4G -serial mon:stdio The main changes include: - Enable video in SPL while running in 32-bit mode - Drop the duplicate ACPI tables with EFI - Support PCI autoconfig in SPL - Support FAT on a CDROM filesystem - Improved bootstd rules around device tree and efi_set_bootdev() There are also quite a number of minor tweaks and fixes to make things easier to use. This series is based on an older version of the SPL-video series from Nikhil M Jain. It is available at u-boot-dm/bryc-working Simon Glass (38): x86: Tidy up availability of string functions x86: Allow listing MTRRs in SPL bios_emulator: Add Kconfig and adjust Makefile for SPL bios_emulator: Drop VIDEO_IO_OFFSET x86: Tidy up EFI code in interrupt_init() x86: Set high bits of the mtrr base registrer x86: Add a comment for board_init_f_r_trampoline() x86: Show the CPU physical address size with bdinfo x86: Correct get_sp() implementation for 64-bit x86: Show an error when a BINS exception occurs acpi: Add a comment to set the acpi tables bdinfo: Show the RAM top and approximate stack pointer part: Allow setting the partition-table type qfw: Show the file address if available log: Tidy up an ambiguous comment. video: Allow building video drivers for SPL qfw: Set the address of the ACPI tables efi: Show all known UUIDs with CONFIG_CMD_EFIDEBUG x86: Improve the trampoline in 64-bit mode Show the malloc base with the bdinfo command nvme: Provide more useful debugging messages pci: Support autoconfig in SPL pci: Allow the video BIOS to work in SPL with QEMU pci: Tidy up logging and reporting for video BIOS x86: Allow video-BIOS code to be built for SPL x86: Pass video settings from SPL to U-Boot proper x86: Init video in SPL if enabled pci: Adjust video BIOS debugging to be SPL-friendly pci: Mask the ROM address in case it is already enabled x86: Enable display for QEMU 64-bit x86: Allow logging to be used in SPL reliably fs: fat: Shrink the size of a few strings fs: fat: Support reading from a larger block size x86: Enable useful options for qemu-86_64 x86: Record the start and end of the tables sandbox: Correct header order in board file sandbox: Install ACPI tables on startup efi: Use the installed ACPI tables arch/sandbox/include/asm/global_data.h | 4 + arch/x86/cpu/i386/interrupt.c | 17 +-- arch/x86/cpu/mtrr.c | 62 +++++++- arch/x86/cpu/start64.S | 19 +++ arch/x86/include/asm/global_data.h | 4 + arch/x86/include/asm/mtrr.h | 20 +++ arch/x86/include/asm/string.h | 6 +- arch/x86/include/asm/u-boot-x86.h | 21 ++- arch/x86/lib/Makefile | 9 +- arch/x86/lib/bdinfo.c | 5 + arch/x86/lib/bios.c | 5 +- arch/x86/lib/bootm.c | 2 +- arch/x86/lib/spl.c | 26 +++- arch/x86/lib/tables.c | 4 +- board/google/Kconfig | 7 - board/sandbox/sandbox.c | 22 ++- cmd/Kconfig | 8 ++ cmd/acpi.c | 24 +++- cmd/bdinfo.c | 6 + cmd/part.c | 34 +++++ cmd/qfw.c | 2 +- cmd/x86/mtrr.c | 60 +------- common/board_f.c | 12 +- common/board_r.c | 7 +- common/log.c | 2 +- configs/qemu-x86_64_defconfig | 14 ++ disk/part.c | 16 +++ doc/usage/cmd/acpi.rst | 29 +++- doc/usage/cmd/part.rst | 74 ++++++++++ doc/usage/cmd/qfw.rst | 28 ++-- drivers/Kconfig | 2 + drivers/Makefile | 5 +- drivers/bios_emulator/Kconfig | 10 ++ drivers/bios_emulator/biosemui.h | 18 +-- drivers/bios_emulator/x86emu/sys.c | 1 + drivers/misc/qfw.c | 12 ++ drivers/nvme/nvme.c | 36 +++-- drivers/pci/Kconfig | 8 ++ drivers/pci/pci-uclass.c | 10 +- drivers/pci/pci_rom.c | 165 +++++++++++++++++----- fs/fat/Kconfig | 13 ++ fs/fat/fat.c | 117 ++++++++++++--- fs/fat/fat_write.c | 22 ++- include/asm-generic/global_data.h | 11 ++ include/bloblist.h | 1 + include/configs/conga-qeval20-qa3-e3845.h | 2 - include/configs/dfi-bt700.h | 2 - include/configs/minnowmax.h | 2 - include/configs/som-db5800-som-6867.h | 2 - include/configs/theadorable-x86-common.h | 2 - include/configs/x86-chromebook.h | 2 - include/part.h | 9 ++ include/pci_ids.h | 1 + include/video.h | 24 ++++ lib/efi_loader/efi_acpi.c | 33 +++-- lib/uuid.c | 2 +- test/dm/acpi.c | 38 +++++ 57 files changed, 866 insertions(+), 233 deletions(-) create mode 100644 drivers/bios_emulator/Kconfig -- 2.40.0.348.gf938b09366-goog

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[PATCH v3] watchdog: Add a watchdog driver for Raspberry Pi boards
by ETIENNE DUBLE 20 Apr '23

20 Apr '23

This driver supports the bcm2835 watchdog found on Raspberry Pi boards. It is derived from the Linux driver and was tested on two Raspberry Pi board versions (B+ and 3B+). Signed-off-by: Etienne Dublé <etienne.duble(a)imag.fr> --- Changes for v2: - fixed whitespaces in email - moved a static variable to the priv struct Changes for v3: - used the max timeout value the hardware supports - turned the warning to a one-line message drivers/watchdog/Kconfig | 9 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/bcm2835_wdt.c | 132 +++++++++++++++++++++++++++++++++ 3 files changed, 142 insertions(+) create mode 100644 drivers/watchdog/bcm2835_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f1b1cf63ca..06c0d630c8 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -30,6 +30,7 @@ config WATCHDOG_TIMEOUT_MSECS default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SOCFPGA default 16000 if ARCH_SUNXI + default 15000 if ARCH_BCM283X default 60000 help Watchdog timeout in msec @@ -326,6 +327,14 @@ config WDT_SUNXI help Enable support for the watchdog timer in Allwinner sunxi SoCs. +config WDT_BCM2835 + bool "Broadcom 2835 watchdog timer support" + depends on WDT && ARCH_BCM283X + default y + help + Enable support for the watchdog timer in Broadcom 283X SoCs such + as Raspberry Pi boards. + config XILINX_TB_WATCHDOG bool "Xilinx Axi watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 446d961d7d..f99915960c 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_WDT_APPLE) += apple_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o +obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o diff --git a/drivers/watchdog/bcm2835_wdt.c b/drivers/watchdog/bcm2835_wdt.c new file mode 100644 index 0000000000..3c1ead3dda --- /dev/null +++ b/drivers/watchdog/bcm2835_wdt.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 Lubomir Rintel <lkundrak(a)v3.sk> + * Copyright (C) 2023 Etienne Dublé (CNRS) <etienne.duble(a)imag.fr> + * + * This code is mostly derived from the linux driver. + */ + +#include <dm.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> + +#define PM_RSTC 0x1c +#define PM_WDOG 0x24 + +#define PM_PASSWORD 0x5a000000 + +/* The hardware supports a maximum timeout value of 0xfffff ticks + * (just below 16 seconds). + */ +#define PM_WDOG_MAX_TICKS 0x000fffff +#define PM_RSTC_WRCFG_CLR 0xffffffcf +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +#define PM_RSTC_RESET 0x00000102 + +#define MS_TO_WDOG_TICKS(x) (((x) << 16) / 1000) + +struct bcm2835_wdt_priv { + void __iomem *base; + u64 timeout_ticks; +}; + +static int bcm2835_wdt_start_ticks(struct udevice *dev, + u64 timeout_ticks, ulong flags) +{ + struct bcm2835_wdt_priv *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u32 cur; + + writel(PM_PASSWORD | timeout_ticks, base + PM_WDOG); + cur = readl(base + PM_RSTC); + writel(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET, + base + PM_RSTC); + + return 0; +} + +static int bcm2835_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct bcm2835_wdt_priv *priv = dev_get_priv(dev); + + priv->timeout_ticks = MS_TO_WDOG_TICKS(timeout_ms); + + if (priv->timeout_ticks > PM_WDOG_MAX_TICKS) { + printf("bcm2835_wdt: the timeout value is too high, using ~16s instead.\n"); + priv->timeout_ticks = PM_WDOG_MAX_TICKS; + } + + return bcm2835_wdt_start_ticks(dev, priv->timeout_ticks, flags); +} + +static int bcm2835_wdt_reset(struct udevice *dev) +{ + struct bcm2835_wdt_priv *priv = dev_get_priv(dev); + + /* restart the timer with the value of priv->timeout_ticks + * saved from the last bcm2835_wdt_start() call. + */ + return bcm2835_wdt_start_ticks(dev, priv->timeout_ticks, 0); +} + +static int bcm2835_wdt_stop(struct udevice *dev) +{ + struct bcm2835_wdt_priv *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + + writel(PM_PASSWORD | PM_RSTC_RESET, base + PM_RSTC); + + return 0; +} + +static int bcm2835_wdt_expire_now(struct udevice *dev, ulong flags) +{ + int ret; + + /* use a timeout of 10 ticks (~150us) */ + ret = bcm2835_wdt_start_ticks(dev, 10, flags); + if (ret) + return ret; + + mdelay(500); + + return 0; +} + +static const struct wdt_ops bcm2835_wdt_ops = { + .reset = bcm2835_wdt_reset, + .start = bcm2835_wdt_start, + .stop = bcm2835_wdt_stop, + .expire_now = bcm2835_wdt_expire_now, +}; + +static const struct udevice_id bcm2835_wdt_ids[] = { + { .compatible = "brcm,bcm2835-pm" }, + { .compatible = "brcm,bcm2835-pm-wdt" }, + { /* sentinel */ } +}; + +static int bcm2835_wdt_probe(struct udevice *dev) +{ + struct bcm2835_wdt_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + priv->timeout_ticks = PM_WDOG_MAX_TICKS; + + bcm2835_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(bcm2835_wdt) = { + .name = "bcm2835_wdt", + .id = UCLASS_WDT, + .of_match = bcm2835_wdt_ids, + .probe = bcm2835_wdt_probe, + .priv_auto = sizeof(struct bcm2835_wdt_priv), + .ops = &bcm2835_wdt_ops, +}; -- 2.34.1

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[PATCH 0/6] serial: msm-geni: fix UART baudrate on modern platforms
by Vladimir Zapolskiy 19 Apr '23

19 Apr '23

The changeset touches Qualcomm platforms, it adds a new quite trivial misc wrapper driver to be accessed by GENI UART to get information about a proper clock divisor. The change does not intend to break any currently supported Qualcomm platforms, there should be no need to update board config or dts files. Vladimir Zapolskiy (6): misc: add Qualcomm GENI SE QUP device driver serial: msm-geni: remove redundant includes serial: msm-geni: remove invalid se-clk clock name serial: msm-geni: fix code indentation serial: msm-geni: fix a compile time warning from msm_serial_setbrg() serial: msm-geni: correct oversampling value based on QUP hardware revision drivers/misc/Kconfig | 6 ++++ drivers/misc/Makefile | 1 + drivers/misc/qcom-geni-se.c | 42 +++++++++++++++++++++++ drivers/serial/serial_msm_geni.c | 57 ++++++++++++++++++++++---------- 4 files changed, 89 insertions(+), 17 deletions(-) create mode 100644 drivers/misc/qcom-geni-se.c -- 2.33.0

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