November 2023 - U-Boot

[PATCH v1] android_ab: don't ignore ab_control_store return code
by Alexey Romanov 20 Dec '23

20 Dec '23

ab_control_store() can return an error if writing to disk fails. In this case, we have to pass the error code to the caller. Signed-off-by: Alexey Romanov <avromanov(a)salutedevices.com> --- boot/android_ab.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/boot/android_ab.c b/boot/android_ab.c index 73b55c196c..5a3152dd53 100644 --- a/boot/android_ab.c +++ b/boot/android_ab.c @@ -337,7 +337,15 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info, if (store_needed) { abc->crc32_le = ab_control_compute_crc(abc); - ab_control_store(dev_desc, part_info, abc, 0); + ret = ab_control_store(dev_desc, part_info, abc, 0); + if (ret < 0) { +#if ANDROID_AB_BACKUP_OFFSET + free(backup_abc); +#endif + free(abc); + log_err("ANDROID: failed to store boot control block: %d\n", ret); + return ret; + } } #if ANDROID_AB_BACKUP_OFFSET @@ -346,8 +354,14 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info, * to the backup offset */ if (memcmp(backup_abc, abc, sizeof(*abc)) != 0) { - ab_control_store(dev_desc, part_info, abc, + ret = ab_control_store(dev_desc, part_info, abc, ANDROID_AB_BACKUP_OFFSET); + if (ret < 0) { + free(backup_abc); + free(abc); + log_err("ANDROID: failed to store boot control block: %d\n", ret); + return ret; + } } free(backup_abc); #endif -- 2.39.2

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[PATCH v1] spi: dw: add check for Rx FIFO overflow
by Maksim Kiselev 20 Dec '23

20 Dec '23

If even one byte is lost due to Rx FIFO overflow then we will never exit the read loop. Because the (priv->rx != priv->rx_end) condition will be always true. Let's check if Rx FIFO overflow occurred and exit the read loop in this case. Signed-off-by: Maksim Kiselev <bigunclemax(a)gmail.com> --- drivers/spi/designware_spi.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 1c7d0ca310..0f443bff8e 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -111,6 +111,15 @@ #define SR_TX_ERR BIT(5) #define SR_DCOL BIT(6) +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define DW_SPI_INT_MASK GENMASK(5, 0) +#define DW_SPI_INT_TXEI BIT(0) +#define DW_SPI_INT_TXOI BIT(1) +#define DW_SPI_INT_RXUI BIT(2) +#define DW_SPI_INT_RXOI BIT(3) +#define DW_SPI_INT_RXFI BIT(4) +#define DW_SPI_INT_MSTI BIT(5) + #define RX_TIMEOUT 1000 /* timeout in ms */ struct dw_spi_plat { @@ -588,7 +597,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) struct dw_spi_priv *priv = dev_get_priv(bus); u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; u8 op_buf[op_len]; - u32 cr0; + u32 cr0, sts; if (read) priv->tmode = CTRLR0_TMOD_EPROMREAD; @@ -632,12 +641,21 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) * them to fail because we are not reading/writing the fifo fast enough. */ if (read) { - priv->rx = op->data.buf.in; + void *prev_rx = priv->rx = op->data.buf.in; priv->rx_end = priv->rx + op->data.nbytes; dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev)); - while (priv->rx != priv->rx_end) + while (priv->rx != priv->rx_end) { dw_reader(priv); + if (prev_rx == priv->rx) { + sts = dw_read(priv, DW_SPI_RISR); + if (sts & DW_SPI_INT_RXOI) { + dev_err(bus, "FIFO overflow on Rx\n"); + return -EIO; + } + } + prev_rx = priv->rx; + } } else { u32 val; -- 2.40.1

3 3

[PATCH v1] gpio: dw: Drop unused headers
by Maksim Kiselev 19 Dec '23

19 Dec '23

Drop headers which are not used or needed in this file. Signed-off-by: Maksim Kiselev <bigunclemax(a)gmail.com> --- drivers/gpio/dwapb_gpio.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index e6e919444f..7a6eae9ba1 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -5,21 +5,15 @@ * DesignWare APB GPIO driver */ -#include <common.h> -#include <log.h> -#include <malloc.h> -#include <asm/arch/gpio.h> #include <asm/gpio.h> #include <asm/io.h> -#include <dm.h> +#include <dm/device.h> #include <dm/device-internal.h> #include <dm/device_compat.h> #include <dm/devres.h> -#include <dm/lists.h> -#include <dm/root.h> +#include <dm/read.h> #include <errno.h> #include <reset.h> -#include <linux/bitops.h> #define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc) #define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc) -- 2.40.1

2 1

[PATCH 1/2] tee: optee: don't fail on services enumeration failure
by Etienne Carriere 19 Dec '23

19 Dec '23

Change optee probe function to only warn when service enumeration sequence fails instead of reporting an optee driver probe failure. Indeed U-Boot can still use OP-TEE even if some OP-TEE services are not discovered. Fixes: 94ccfb78a4d6 ("drivers: tee: optee: discover OP-TEE services") Signed-off-by: Etienne Carriere <etienne.carriere(a)foss.st.com> --- drivers/tee/optee/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 9a9b697e91..5308dd58ce 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -841,7 +841,7 @@ static int optee_probe(struct udevice *dev) if (IS_ENABLED(CONFIG_OPTEE_SERVICE_DISCOVERY)) { ret = bind_service_drivers(dev); if (ret) - return ret; + dev_warn(dev, "optee service enumeration failed: %d\n", ret); } else if (IS_ENABLED(CONFIG_RNG_OPTEE)) { /* * Discovery of TAs on the TEE bus is not supported in U-Boot: -- 2.25.1

4 7

[PATCH v2] remoteproc: k3-dsp: Avoid reloading of firmware
by Udit Kumar 19 Dec '23

19 Dec '23

DSP core is going into abnormal state when load callback is called after starting of DSP core. Reload of firmware needs core to be stopped first, followed by load. So avoid loading of firmware, when core is started. Signed-off-by: Udit Kumar <u-kumar1(a)ti.com> --- Change log: Changes in v2: - Added details for in_use variable in comment - Link to v1 https://lore.kernel.org/all/20231124063111.1744600-1-u-kumar1@ti.com/ drivers/remoteproc/ti_k3_dsp_rproc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 576de4bb26..1c6515f9ab 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -56,6 +56,7 @@ struct k3_dsp_boot_data { * @data: Pointer to DSP specific boot data structure * @mem: Array of available memories * @num_mem: Number of available memories + * @in_use: flag to tell if the core is already in use. */ struct k3_dsp_privdata { struct reset_ctl dsp_rst; @@ -63,6 +64,7 @@ struct k3_dsp_privdata { struct k3_dsp_boot_data *data; struct k3_dsp_mem *mem; int num_mems; + bool in_use; }; /* @@ -128,6 +130,13 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) u32 boot_vector; int ret; + if (dsp->in_use) { + dev_err(dev, + "Invalid op: Trying to load/start on already running core %d\n", + dsp->tsp.proc_id); + return -EINVAL; + } + dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size); ret = ti_sci_proc_request(&dsp->tsp); if (ret) @@ -195,6 +204,7 @@ static int k3_dsp_start(struct udevice *dev) ti_sci_proc_power_domain_off(&dsp->tsp); } + dsp->in_use = true; proc_release: ti_sci_proc_release(&dsp->tsp); @@ -207,6 +217,7 @@ static int k3_dsp_stop(struct udevice *dev) dev_dbg(dev, "%s\n", __func__); + dsp->in_use = false; ti_sci_proc_request(&dsp->tsp); reset_assert(&dsp->dsp_rst); ti_sci_proc_power_domain_off(&dsp->tsp); -- 2.34.1

2 1

[PATCH] arm: vexpress64: juno: Allow boot from VirtIO
by robert.catherall＠foss.arm.com 19 Dec '23

19 Dec '23

From: Robert Catherall <robert.catherall(a)arm.com> The AEM and Juno FVPs (Fixed Virtual Platforms) support a VirtIO disc interface. Adding VIRTIO to the list of boot devices allows these FastModel platforms to boot from 'disc' in the same way the hardware counterpart can boot from SATA or USB. This is a NOP if CONFIG_CMD_VIRTIO is not enabled, so no impact on Juno hardware (which is built with vexpress_aemv8a_juno_defconfig) Signed-off-by: Robert Catherall <robert.catherall(a)arm.com> --- include/configs/vexpress_aemv8.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 24d8ca0866..8020689e39 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -187,6 +187,7 @@ func(USB, usb, 0) \ func(SATA, sata, 0) \ func(SATA, sata, 1) \ + FUNC_VIRTIO(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) \ func(AFS, afs, na) -- 2.17.1

3 2

[PATCH] doc: Remove README.sha1 file
by Peter Robinson 19 Dec '23

19 Dec '23

The contents of README.sha1 only refer to process around verification of the pcs440ep board firmware in flash. The device was removed in commit 242836a893ae ("powerpc: ppc4xx: remove pcs440ep support") in 2015 so this readme isn't really relevant anymore so can be removed. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- With the wide deprecation of sha1 in general we should likely also review the use of sha1 in U-Boot as a whole and look to move the remaining users of sha1 to sha2 or sha3 in general. doc/README.sha1 | 58 ------------------------------------------------- 1 file changed, 58 deletions(-) delete mode 100644 doc/README.sha1 diff --git a/doc/README.sha1 b/doc/README.sha1 deleted file mode 100644 index f178f372643..00000000000 --- a/doc/README.sha1 +++ /dev/null @@ -1,58 +0,0 @@ -SHA1 usage: ------------ - -In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated. -This SHA1 sum is used, to check, if the U-Boot Image in Flash is not -corrupted. - -The following command is available: - -=> help sha1 -sha1 address len [addr] calculate the SHA1 sum [save at addr] - -p calculate the SHA1 sum from the U-Boot image in flash and print - -c check the U-Boot image in flash - -"sha1 -p" - calculates and prints the SHA1 sum, from the Image stored in Flash - -"sha1 -c" - check, if the SHA1 sum from the Image stored in Flash is correct - - -It is possible to calculate a SHA1 checksum from a memoryrange with: - -"sha1 address len" - -If you want to store a new Image in Flash for the pcs440ep board, -which has no SHA1 sum, you can do the following: - -a) cp the new Image on a position in RAM (here 0x300000) - (for this example we use the Image from Flash, stored at 0xfffa0000 and - 0x60000 Bytes long) - -"cp.b fffa0000 300000 60000" - -b) Initialize the SHA1 sum in the Image with 0x00 - The SHA1 sum is stored in Flash at: - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + SHA1_SUM_POS - for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20 - = 0xffffffe0 - for the example in RAM: 0x300000 + 0x60000 + -0x20 - = 0x35ffe0 - - note: a SHA1 checksum is 20 bytes long. - -"mw.b 35ffe0 0 14" - -c) now calculate the SHA1 sum from the memoryrange and write - the calculated checksum at the right place: - -"sha1 300000 60000 35ffe0" - -Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum. - -If you do a "buildman -k pcs440ep" or a "make all" to get the U-Boot image, -which will be found in ../current/ipam390/ - the correct SHA1 sum will be -automagically included in the U-Boot image. - -Heiko Schocher, 11 Jul 2007 -- 2.42.0

3 2

[RFC PATCH] mxs: Don't enable 4P2 reg if mx28 is powered only from DCDC_BATT without 5V
by Alan Kay 19 Dec '23

19 Dec '23

mxs_power_enable_4p2() was added to mxs_batt_boot() in 'commit a0f97610757d ("ARM: mxs: Enable DCDC converter for battery boot")' to enable DCDC converter when board is powered from 5V and has detected sufficient battery voltage. This involves enabling 4P2 regulator and there is a code in mxs_power_enable_4p2() that disables VDDIO, VDDA, VDDD outputs of the DCDC converter and enables BO for each power rail e.g. setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); In case the mx28 is powered by the 5V source and linear regulators are supplying power to the VDDIO, VDDA, VDDD rails there is no issue. However if the mx28 is powered by the DCDC_BATT source only without 5V, disabling the DCDC converter outputs causes brownout power down. The proposed solution is not to call mxs_power_enable_4p2() at all if the mx28 is powered by the DCDC_BATT source only. There is no reason to enable 4P2 regulator in this case and setup of all registers is done in mxs_batt_boot(). Also there is no need to enable 5V brownout in mxs_power_init() in this case. Please consider if this is acceptable and I will submit a proper patch. Signed-off-by: Alan Kay <alan(a)londelec.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..c8feadce54 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,7 +752,9 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE mxs_power_enable_4p2(); +#endif } /** @@ -1267,7 +1269,9 @@ void mxs_power_init(void) POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); +#endif early_delay(1000); } -- 2.25.1

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[PATCH] mtd: spi-nor: Update block protection flags for ospi flash parts
by Venkatesh Yadav Abbarapu 18 Dec '23

18 Dec '23

Updating the block protection flags for Gigadevice gd25lx256e and ISSI is25wx256 OSPI flash parts. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 77eb9f352c..b939780889 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -191,7 +191,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, /* adding these 1.8V OSPI flash parts */ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | @@ -233,7 +234,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | + SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ -- 2.17.1

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[PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx
by Bruce Suen 18 Dec '23

18 Dec '23

Add Support XTX Technology XT26G01DXXXXX, XT26G11DXXXXX, XT26Q01DXXXXX, XT26G02DXXXXX, XT26G12DXXXXX, XT26Q02DXXXXX, XT26G04DXXXXX, and XT26Q04DXXXXX SPI NAND. These are 3V/1.8V 1G/2G/4Gbit serial SLC NAND flash device with on-die ECC(8bit strength per 512bytes). Datasheet Links: - http://www.xtxtech.com/download/?AId=458 - http://www.xtxtech.com/download/?AId=495 Signed-off-by: Bruce Suen <bruce_suen(a)163.com> --- drivers/mtd/nand/spi/Makefile | 1 + drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/xtx.c | 180 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 183 insertions(+) create mode 100644 drivers/mtd/nand/spi/xtx.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index 3051de4f7e..e46cfed446 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o +spinand-objs += xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 597b088ca7..0b4c067425 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -828,6 +828,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &paragon_spinand_manufacturer, &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, + &xtx_spinand_manufacturer, }; static int spinand_manufacturer_match(struct spinand_device *spinand, diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c new file mode 100644 index 0000000000..ced05b5895 --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * Derived from drivers/mtd/nand/spi/micron.c + * Copyright (c) 2016-2017 Micron Technology, Inc. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/bitfield.h> +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_XTX 0x0B + +#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6) +#define XT26XXXD_STATUS_ECC_NO_DETECTED (0) +#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1) +#define XT26XXXD_STATUS_ECC_8_CORRECTED (3) +#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = mtd->oobsize / 2 - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = { + .ecc = xt26xxxd_ooblayout_ecc, + .rfree = xt26xxxd_ooblayout_free, +}; + +static int xt26xxxd_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (FIELD_GET(STATUS_ECC_MASK, status)) { + case XT26XXXD_STATUS_ECC_NO_DETECTED: + return 0; + case XT26XXXD_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + case XT26XXXD_STATUS_ECC_1_7_CORRECTED: + return 4 + FIELD_GET(XT26XXXD_STATUS_ECC3_ECC2_MASK, status); + case XT26XXXD_STATUS_ECC_8_CORRECTED: + return 8; + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info xtx_spinand_table[] = { + SPINAND_INFO("XT26G01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G11D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G12D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), +}; + +static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer xtx_spinand_manufacturer = { + .id = SPINAND_MFR_XTX, + .name = "XTX", + .chips = xtx_spinand_table, + .nchips = ARRAY_SIZE(xtx_spinand_table), + .ops = &xtx_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index e8d6feb970..bf7696a981 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -251,6 +251,7 @@ extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; +extern const struct spinand_manufacturer xtx_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants -- 2.34.1

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