November 2023 - U-Boot

[PATCH RESEND v3 1/1] arm: dts: icnova-a20-adb4006: Add board support
by Ludwig Kormann 01 Nov '23

01 Nov '23

Add board support for ICnova A20 SomPi compute module on ICnova ADB4006 development board. Specification: SoM - Processor: Allwinner A20 Cortex-A7 Dual Core at 1GHz - 512MB DDR3 RAM - Fast Ethernet (Phy: Realtek RTL8201CP) ADB4006 - I2C - 2x USB 2.0 - 1x Fast Ethernet port - 1x SATA - 2x buttons (PWRON, Boot) - 2x LEDS - serial console - HDMI - µSD-Card slot - Audio Line-In / Line-Out - GPIO pinheaders https://wiki.in-circuit.de/index.php5?title=ICnova_ADB4006 https://wiki.in-circuit.de/index.php5?title=ICnova_A20_SODIMM devicetree upstreamed with linux 6.5 Signed-off-by: Ludwig Kormann <ludwig.kormann(a)ict42.de> --- changes in v3: - rebase on v2023.10 changes in v2: - rebase on v2023.07-rc2 - remove pin defines from defconfig - get dts reviewed on the linux mailing list and scheduled for kernel 6.5 [1] [1] https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git commit de2bdfb7f79d5c655eb056d459e02be2c7f13c8b --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts | 137 ++++++++++++++++++ arch/arm/dts/sun7i-a20-icnova-a20.dtsi | 62 ++++++++ board/sunxi/MAINTAINERS | 5 + configs/icnova-a20-adb4006_defconfig | 20 +++ 5 files changed, 225 insertions(+) create mode 100644 arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts create mode 100644 arch/arm/dts/sun7i-a20-icnova-a20.dtsi create mode 100644 configs/icnova-a20-adb4006_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 85fd5b1157..16d5930b78 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -667,6 +667,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-haoyu-marsboard.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ sun7i-a20-icnova-swac.dtb \ sun7i-a20-itead-ibox.dtb \ sun7i-a20-lamobo-r1.dtb \ diff --git a/arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts new file mode 100644 index 0000000000..577ead1d02 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +/dts-v1/; + +#include "sun7i-a20-icnova-a20.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "In-Circuit ICnova A20 ADB4006"; + compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ahci { + target-supply = <&reg_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&reg_ahci_5v { + status = "okay"; +}; + +&ac_power_supply { + status = "okay"; +}; + +&reg_usb1_vbus { + status = "okay"; +}; + +&reg_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb1_vbus-supply = <&reg_usb1_vbus>; + usb2_vbus-supply = <&reg_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun7i-a20-icnova-a20.dtsi b/arch/arm/dts/sun7i-a20-icnova-a20.dtsi new file mode 100644 index 0000000000..46616c6bc8 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-icnova-a20.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/interrupt-controller/irq.h> + +&cpu0 { + cpu-supply = <&reg_dcdc2>; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +#include "axp209.dtsi" + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +&reg_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +&reg_ldo1 { + regulator-name = "vdd-rtc"; +}; + +&reg_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 98bbd2dd25..67cdd01371 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -236,6 +236,11 @@ M: Stefan Roese <sr(a)denx.de> S: Maintained F: configs/icnova-a20-swac_defconfig +ICnova-A20-ADB4006 BOARD +M: Ludwig Kormann <ludwig.kormann(a)ict42.de> +S: Maintained +F: configs/icnova-a20-adb4006_defconfig + ITEAD IBOX BOARD M: Marcus Cooper <codekipper(a)gmail.com> S: Maintained diff --git a/configs/icnova-a20-adb4006_defconfig b/configs/icnova-a20-adb4006_defconfig new file mode 100644 index 0000000000..f70ffe45ab --- /dev/null +++ b/configs/icnova-a20-adb4006_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-a20-adb4006" +CONFIG_SPL=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=384 +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SUN7I_GMAC=y +CONFIG_AXP_ALDO4_VOLT=2800 +CONFIG_SCSI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y -- 2.30.2

2 3

[PATCH v4] cmd: mmc: Add mmc reg read command for reading card registers
by Marek Vasut 01 Nov '23

01 Nov '23

Add extension to the 'mmc' command to read out the card registers. Currently, only the eMMC OCR/CID/CSD/EXTCSD/RCA/DSR register are supported. A register value can either be displayed or read into an environment variable. Tested-by: Jaehoon Chung <jh80.chung(a)samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Abdellatif El Khlifi <abdellatif.elkhlifi(a)arm.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Roger Knecht <rknecht(a)pm.me> Cc: Sean Edmond <seanedmond(a)microsoft.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tobias Waldekranz <tobias(a)waldekranz.com> --- V2: - Update documentation V3: - Return CMD_RET_FAILURE on failure - Add RB/TB from Jaehoon V4: - Drop default n --- cmd/Kconfig | 7 ++++ cmd/mmc.c | 96 +++++++++++++++++++++++++++++++++++++++++++ doc/usage/cmd/mmc.rst | 26 ++++++++++++ 3 files changed, 129 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 60aed2c307c..fd16c3a48e5 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1313,6 +1313,13 @@ config CMD_BKOPS_ENABLE on a eMMC device. The feature is optionally available on eMMC devices conforming to standard >= 4.41. +config CMD_MMC_REG + bool "Enable support for reading card registers in the mmc command" + depends on CMD_MMC + help + Enable the commands for reading card registers. This is useful + mostly for debugging or extracting details from the card. + config CMD_MMC_RPMB bool "Enable support for RPMB in the mmc command" depends on SUPPORT_EMMC_RPMB diff --git a/cmd/mmc.c b/cmd/mmc.c index c6bd81cebbc..96befb27eec 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -1110,6 +1110,93 @@ static int do_mmc_boot_wp(struct cmd_tbl *cmdtp, int flag, return CMD_RET_SUCCESS; } +#if CONFIG_IS_ENABLED(CMD_MMC_REG) +static int do_mmc_reg(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); + struct mmc *mmc; + int i, ret; + u32 off; + + if (argc < 3 || argc > 5) + return CMD_RET_USAGE; + + mmc = find_mmc_device(curr_device); + if (!mmc) { + printf("no mmc device at slot %x\n", curr_device); + return CMD_RET_FAILURE; + } + + if (IS_SD(mmc)) { + printf("SD registers are not supported\n"); + return CMD_RET_FAILURE; + } + + off = simple_strtoul(argv[3], NULL, 10); + if (!strcmp(argv[2], "cid")) { + if (off > 3) + return CMD_RET_USAGE; + printf("CID[%i]: 0x%08x\n", off, mmc->cid[off]); + if (argv[4]) + env_set_hex(argv[4], mmc->cid[off]); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "csd")) { + if (off > 3) + return CMD_RET_USAGE; + printf("CSD[%i]: 0x%08x\n", off, mmc->csd[off]); + if (argv[4]) + env_set_hex(argv[4], mmc->csd[off]); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "dsr")) { + printf("DSR: 0x%08x\n", mmc->dsr); + if (argv[4]) + env_set_hex(argv[4], mmc->dsr); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "ocr")) { + printf("OCR: 0x%08x\n", mmc->ocr); + if (argv[4]) + env_set_hex(argv[4], mmc->ocr); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "rca")) { + printf("RCA: 0x%08x\n", mmc->rca); + if (argv[4]) + env_set_hex(argv[4], mmc->rca); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "extcsd") && + mmc->version >= MMC_VERSION_4_41) { + ret = mmc_send_ext_csd(mmc, ext_csd); + if (ret) + return CMD_RET_FAILURE; + if (!strcmp(argv[3], "all")) { + /* Dump the entire register */ + printf("EXT_CSD:"); + for (i = 0; i < MMC_MAX_BLOCK_LEN; i++) { + if (!(i % 10)) + printf("\n%03i: ", i); + printf(" %02x", ext_csd[i]); + } + printf("\n"); + return CMD_RET_SUCCESS; + } + off = simple_strtoul(argv[3], NULL, 10); + if (off > 512) + return CMD_RET_USAGE; + printf("EXT_CSD[%i]: 0x%02x\n", off, ext_csd[off]); + if (argv[4]) + env_set_hex(argv[4], ext_csd[off]); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} +#endif + static struct cmd_tbl cmd_mmc[] = { U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""), U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""), @@ -1142,6 +1229,9 @@ static struct cmd_tbl cmd_mmc[] = { U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""), U_BOOT_CMD_MKENT(bkops, 4, 0, do_mmc_bkops, "", ""), #endif +#if CONFIG_IS_ENABLED(CMD_MMC_REG) + U_BOOT_CMD_MKENT(reg, 5, 0, do_mmc_reg, "", ""), +#endif }; static int do_mmcops(struct cmd_tbl *cmdtp, int flag, int argc, @@ -1229,6 +1319,12 @@ U_BOOT_CMD( " WARNING: This is a write-once setting.\n" "mmc bkops <dev> [auto|manual] [enable|disable]\n" " - configure background operations handshake on device\n" +#endif +#if CONFIG_IS_ENABLED(CMD_MMC_REG) + "mmc reg read <reg> <offset> [env] - read card register <reg> offset <offset>\n" + " (optionally into [env] variable)\n" + " - reg: cid/csd/dsr/ocr/rca/extcsd\n" + " - offset: for cid/csd [0..3], for extcsd [0..511,all]\n" #endif ); diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst index 71a0303109c..c0924ba5769 100644 --- a/doc/usage/cmd/mmc.rst +++ b/doc/usage/cmd/mmc.rst @@ -21,6 +21,7 @@ Synopsis mmc bootpart-resize <dev> <dev part size MB> <RPMB part size MB> mmc partconf <dev> [[varname] | [<boot_ack> <boot_partition> <partition_access>]] mmc rst-function <dev> <value> + mmc reg read <reg> <offset> [env] Description ----------- @@ -183,6 +184,31 @@ The 'mmc rst-function' command changes the RST_n_FUNCTION field. 0x3 Reserved +The 'mmc reg read <reg> <offset> [env]' reads eMMC card register and +either print it to standard output, or store the value in environment +variable. + +<reg> with +optional offset <offset> into the register array, and print it to +standard output or store it into environment variable [env]. + + reg + cid + The Device IDentification (CID) register. Uses offset. + csd + The Device-Specific Data (CSD) register. Uses offset. + dsr + The driver stage register (DSR). + ocr + The operation conditions register (OCR). + rca + The relative Device address (RCA) register. + extcsd + The Extended CSD register. Uses offset. + offset + For 'cid'/'csd' 128 bit registers '[0..3]' in 32-bit increments. For 'extcsd' 512 bit register '[0..512,all]' in 8-bit increments, or 'all' to read the entire register. + env + Optional environment variable into which 32-bit value read from register should be stored. Examples -------- -- 2.42.0

3 2

[PATCH] mmc: sdhci: Rework SDHCI_QUIRK_BROKEN_R1B
by Sean Anderson 01 Nov '23

01 Nov '23

As noted in commit 3a6383207be ("mmc: sdhci: add the quirk for broken r1b response"), some MMC controllers don't always set the transfer complete bit with R1b responses. According to the SD Host Controller Simplified Specification v4.20, > In the case of a command pairing with response-with-busy[, Transfer > Complete] is set when busy is de-asserted. Refer to DAT Line Active > and Command Inhibit (DAT) in the Present State register. By polling the DAT Line Active bit in the present state register, we can detect when we are no longer busy, without waiting for a long timeout. This results in much faster reads/writes on buggy controllers. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- I've CC'd a few people who've added this quirk to controllers recently. Please let me know if your hardware still works. It's possible that my hardware is buggy in a different way. drivers/mmc/sdhci.c | 19 ++++++++++++------- include/sdhci.h | 1 + 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index fc9c6c37996..0178ed8a11e 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -306,14 +306,19 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (stat & SDHCI_INT_ERROR) break; - if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { - if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { + if (host->quirks & SDHCI_QUIRK_BROKEN_R1B && + cmd->resp_type & MMC_RSP_BUSY && !data) { + unsigned int state = + sdhci_readl(host, SDHCI_PRESENT_STATE); + + if (!(state & SDHCI_DAT_ACTIVE)) return 0; - } else { - printf("%s: Timeout for status update!\n", - __func__); - return -ETIMEDOUT; - } + } + + if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { + printf("%s: Timeout for status update: %08x %08x\n", + __func__, stat, mask); + return -ETIMEDOUT; } } while ((stat & mask) != mask); diff --git a/include/sdhci.h b/include/sdhci.h index 70fefca2a97..a1b74e3bd79 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -57,6 +57,7 @@ #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT BIT(0) #define SDHCI_DATA_INHIBIT BIT(1) +#define SDHCI_DAT_ACTIVE BIT(2) #define SDHCI_DOING_WRITE BIT(8) #define SDHCI_DOING_READ BIT(9) #define SDHCI_SPACE_AVAILABLE BIT(10) -- 2.35.1.1320.gc452695387.dirty

3 3

[PATCH] mmc: pci: Drop the superfluous cast
by Bin Meng 01 Nov '23

01 Nov '23

dm_pci_map_bar() return a value of (void *) already, hence no need to cast it again before assigning to host->ioaddr. Signed-off-by: Bin Meng <bmeng(a)tinylab.org> --- drivers/mmc/pci_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 9fb7044029..4d163ccba0 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -50,8 +50,8 @@ static int pci_mmc_probe(struct udevice *dev) desc = mmc_get_blk_desc(&plat->mmc); desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE); - host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, - PCI_REGION_MEM); + host->ioaddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); host->name = dev->name; host->cd_gpio = priv->cd_gpio; host->mmc = &plat->mmc; -- 2.34.1

3 3

[PATCH] mmc: spl: select SPL_BLK for SPL_DM_MMC
by Oleksandr Suvorov 01 Nov '23

01 Nov '23

mmc_bind() in mmc-uclass.c calls blk_create_devicef() which is defined in blk-uclass.c, so SPL_BLK is required by SPL_DM_MMC. Implicitly select SPL_BLK for SPL_DM_MMC. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> --- drivers/mmc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index de01b9687ba..d24677de076 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -46,6 +46,7 @@ config SPL_DM_MMC depends on SPL_DM && DM_MMC default n if ARCH_MVEBU && !MVEBU_SPL_BOOT_DEVICE_MMC default y + select SPL_BLK help This enables the MultiMediaCard (MMC) uclass which supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) -- 2.41.0

3 3

[PATCH] riscv: Weakly define invalidate_icache_range()
by Samuel Holland 01 Nov '23

01 Nov '23

Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/riscv/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index c46b49eb0ac..afad7e117f3 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end) { } -void invalidate_icache_range(unsigned long start, unsigned long end) +__weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the -- 2.41.0

2 1

[PATCH] riscv: Align the trap handler to 64 bytes
by Samuel Holland 01 Nov '23

01 Nov '23

This is required on CPUs which always operate in CLIC mode, such as the T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the trap vector base address held in mtvec is constrained to be aligned on a 64-byte or larger power-of-two boundary." Reported-by: Madushan Nishantha <jlmadushan(a)gmail.com> Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/riscv/cpu/mtrap.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 6eb3ed1d5a8..5cad7b41ff7 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -26,7 +26,7 @@ .text /* trap entry */ - .align 2 + .align 6 .global trap_entry trap_entry: addi sp, sp, -32 * REGBYTES -- 2.41.0

2 1

[PATCH] riscv: Sort target configs alphabetically
by Samuel Holland 01 Nov '23

01 Nov '23

Clean things up for the next time somebody adds a target. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/riscv/Kconfig | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8fc81fb284c..6d0d812ddb5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,6 +14,9 @@ config TARGET_ANDES_AE350 config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_OPENPITON_RISCV64 + bool "Support RISC-V cores on OpenPiton SoC" + config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" @@ -24,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6 +config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" + select SYS_CACHE_SHIFT_6 + config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board" select BOARD_LATE_INIT @@ -32,13 +39,6 @@ config TARGET_TH1520_LPI4A bool "Support Sipeed's TH1520 Lichee PI 4A Board" select SYS_CACHE_SHIFT_6 -config TARGET_SIPEED_MAIX - bool "Support Sipeed Maix Board" - select SYS_CACHE_SHIFT_6 - -config TARGET_OPENPITON_RISCV64 - bool "Support RISC-V cores on OpenPiton SoC" - endchoice config SYS_ICACHE_OFF @@ -76,12 +76,12 @@ config SPL_ZERO_MEM_BEFORE_USE source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" +source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" -source "board/thead/th1520_lpi4a/Kconfig" -source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" -- 2.41.0

2 1

[PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver
by Chanho Park 01 Nov '23

01 Nov '23

This patchset adds to support StarFive JH7110 TRNG driver. Due to lack of readl_relaxed API, the first patch tries to import the APIs(read/write_relaxed) from Linux kernel's implementation. The second patch adds the missing security clocks which are required by the trng IP. This IP can support 128-bit and 256-bit random number generation but this patch makes 256-bit default mode for convenience. Changes from v1: - Patch #3: Apply Heinrich's reviews and his codes - Patch #5: Add Heinrich's R-b tag Chanho Park (5): riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG driver riscv: dts: jh7110: Add rng device tree node configs: visionfive2: Enable JH7110 RNG driver arch/riscv/dts/jh7110.dtsi | 10 + arch/riscv/include/asm/io.h | 45 +++++ configs/starfive_visionfive2_defconfig | 2 + drivers/clk/starfive/clk-jh7110.c | 10 + drivers/rng/Kconfig | 6 + drivers/rng/Makefile | 1 + drivers/rng/jh7110_rng.c | 258 +++++++++++++++++++++++++ 7 files changed, 332 insertions(+) create mode 100644 drivers/rng/jh7110_rng.c -- 2.39.2

2 7

Re bootstd: Skip over bad device during bootflows scanning
by Simon Glass 01 Nov '23

01 Nov '23

Hi Tony, Sorry I cannot reply to the patch[1]. Can you please send the console trace for this situation? I don't want to ignore errors completely, so wonder if there is a special error code which could be produced when a device is missing? Regards, Simon [1] https://patchwork.ozlabs.org/project/uboot/patch/20231030194650.11594-1-mib…

2 2