January 2023 - U-Boot

[PATCH v3] rtc: add ht1380 driver
by Sergei Antonov 03 Jan '23

03 Jan '23

Support Holtek HT1380/HT1381 Serial Timekeeper Chip. It provides seconds , minutes, hours, day of the week, date, month and year information. Datasheet: https://www.holtek.com.tw/documents/10179/11842/ht1380_1v130.pdf Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- v3: Suggested by Simon Glass: * remove extra brackets * pass GPIOD_IS_OUT to gpio_request_by_name() and drop the extra code below * add text to Kconfig: how it is connected, i.e. three GPIOs * rename dts names to plural: rst/clk/dat-gpios Suggested by Tom Rini: * enable on sandbox so that it gets build tested v2: * The RESET pin is now to be described as ACTIVE_LOW in dts. Changes suggested by Simon Glass: * a more detailed driver description in Kconfig * multi-line comments' style * enum for 0x80 and the 0x20 at top of file * lower-case hex constants * function comments for ht1380_reset_on/off * blank line before returns configs/sandbox_defconfig | 1 + drivers/rtc/Kconfig | 9 ++ drivers/rtc/Makefile | 1 + drivers/rtc/ht1380.c | 329 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 340 insertions(+) create mode 100644 drivers/rtc/ht1380.c diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 404e4a3324a2..f9c996b4299d 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -334,3 +334,4 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_IPV6=y +CONFIG_RTC_HT1380=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 23963271928a..04ca2914f1be 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -220,4 +220,13 @@ config RTC_ZYNQMP Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. +config RTC_HT1380 + bool "Enable Holtek HT1380/HT1381 RTC driver" + depends on DM_RTC && DM_GPIO + help + Say "yes" here to get support for Holtek HT1380/HT1381 + Serial Timekeeper IC which provides seconds, minutes, hours, + day of the week, date, month and year information. It is to be + connected via 3 GPIO pins which work as reset, clock, and data. + endmenu diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 009dd9d28c95..f3164782b605 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +obj-$(CONFIG_RTC_HT1380) += ht1380.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c new file mode 100644 index 000000000000..85fcee3e71e6 --- /dev/null +++ b/drivers/rtc/ht1380.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Holtek HT1380/HT1381 Serial Timekeeper Chip + * + * Communication with the chip is vendor-specific. + * It is done via 3 GPIO pins: reset, clock, and data. + * Describe in .dts this way: + * + * rtc { + * compatible = "holtek,ht1380"; + * rst-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + * clk-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + * dat-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>; + * }; + * + */ + +#include <common.h> +#include <dm.h> +#include <rtc.h> +#include <bcd.h> +#include <asm/gpio.h> +#include <linux/delay.h> + +struct ht1380_priv { + struct gpio_desc rst_desc; + struct gpio_desc clk_desc; + struct gpio_desc dat_desc; +}; + +enum registers { + SEC, + MIN, + HOUR, + MDAY, + MONTH, + WDAY, + YEAR, + WP, + N_REGS +}; + +enum hour_mode { + AMPM_MODE = 0x80, /* RTC is in AM/PM mode */ + PM_NOW = 0x20, /* set if PM, clear if AM */ +}; + +static const int BURST = 0xbe; +static const int READ = 1; + +static void ht1380_half_period_delay(void) +{ + /* + * Delay for half a period. 1 us complies with the 500 KHz maximum + * input serial clock limit given by the datasheet. + */ + udelay(1); +} + +static int ht1380_send_byte(struct ht1380_priv *priv, int byte) +{ + int ret; + + for (int bit = 0; bit < 8; bit++) { + ret = dm_gpio_set_value(&priv->dat_desc, byte >> bit & 1); + if (ret) + break; + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 1); + if (ret) + break; + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + break; + } + + return ret; +} + +/* + * Leave reset state. The transfer operation can then be started. + */ +static int ht1380_reset_off(struct ht1380_priv *priv) +{ + const unsigned int T_CC = 4; /* us, Reset to Clock Setup */ + int ret; + + /* + * Leave RESET state. + * Make sure we make the minimal delay required by the datasheet. + */ + ret = dm_gpio_set_value(&priv->rst_desc, 0); + udelay(T_CC); + + return ret; +} + +/* + * Enter reset state. Completes the transfer operation. + */ +static int ht1380_reset_on(struct ht1380_priv *priv) +{ + const unsigned int T_CWH = 4; /* us, Reset Inactive Time */ + int ret; + + /* + * Enter RESET state. + * Make sure we make the minimal delay required by the datasheet. + */ + ret = dm_gpio_set_value(&priv->rst_desc, 1); + udelay(T_CWH); + + return ret; +} + +static int ht1380_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + int ret, i, bit, reg[N_REGS]; + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + return ret; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = ht1380_reset_off(priv); + if (ret) + goto exit; + + ret = ht1380_send_byte(priv, BURST + READ); + if (ret) + goto exit; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_IN); + if (ret) + goto exit; + + for (i = 0; i < N_REGS; i++) { + reg[i] = 0; + + for (bit = 0; bit < 8; bit++) { + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 1); + if (ret) + goto exit; + ht1380_half_period_delay(); + + reg[i] |= dm_gpio_get_value(&priv->dat_desc) << bit; + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + goto exit; + } + } + + ret = -EINVAL; + + /* Correctness check: some bits are always zero */ + if (reg[MIN] & 0x80 || reg[HOUR] & 0x40 || reg[MDAY] & 0xc0 || + reg[MONTH] & 0xe0 || reg[WDAY] & 0xf8 || reg[WP] & 0x7f) + goto exit; + + /* Correctness check: some registers are always non-zero */ + if (!reg[MDAY] || !reg[MONTH] || !reg[WDAY]) + goto exit; + + tm->tm_sec = bcd2bin(reg[SEC]); + tm->tm_min = bcd2bin(reg[MIN]); + if (reg[HOUR] & AMPM_MODE) { + /* AM-PM Mode, range is 01-12 */ + tm->tm_hour = bcd2bin(reg[HOUR] & 0x1f) % 12; + if (reg[HOUR] & PM_NOW) { + /* it is PM (otherwise AM) */ + tm->tm_hour += 12; + } + } else { + /* 24-hour Mode, range is 0-23 */ + tm->tm_hour = bcd2bin(reg[HOUR]); + } + tm->tm_mday = bcd2bin(reg[MDAY]); + tm->tm_mon = bcd2bin(reg[MONTH]); + tm->tm_year = 2000 + bcd2bin(reg[YEAR]); + tm->tm_wday = bcd2bin(reg[WDAY]) - 1; + tm->tm_yday = 0; + tm->tm_isdst = 0; + + ret = 0; + +exit: + ht1380_reset_on(priv); + + return ret; +} + +static int ht1380_write_protection_off(struct ht1380_priv *priv) +{ + int ret; + const int PROTECT = 0x8e; + + ret = ht1380_reset_off(priv); + if (ret) + return ret; + + ret = ht1380_send_byte(priv, PROTECT); + if (ret) + return ret; + ret = ht1380_send_byte(priv, 0); /* WP bit is 0 */ + if (ret) + return ret; + + return ht1380_reset_on(priv); +} + +static int ht1380_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + int ret, i, reg[N_REGS]; + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + return ret; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT); + if (ret) + goto exit; + + ret = ht1380_write_protection_off(priv); + if (ret) + goto exit; + + reg[SEC] = bin2bcd(tm->tm_sec); + reg[MIN] = bin2bcd(tm->tm_min); + reg[HOUR] = bin2bcd(tm->tm_hour); + reg[MDAY] = bin2bcd(tm->tm_mday); + reg[MONTH] = bin2bcd(tm->tm_mon); + reg[WDAY] = bin2bcd(tm->tm_wday) + 1; + reg[YEAR] = bin2bcd(tm->tm_year - 2000); + reg[WP] = 0x80; /* WP bit is 1 */ + + ret = ht1380_reset_off(priv); + if (ret) + goto exit; + + ret = ht1380_send_byte(priv, BURST); + for (i = 0; i < N_REGS && ret; i++) + ret = ht1380_send_byte(priv, reg[i]); + +exit: + ht1380_reset_on(priv); + + return ret; +} + +static int ht1380_probe(struct udevice *dev) +{ + int ret; + struct ht1380_priv *priv; + + priv = dev_get_priv(dev); + if (!priv) + return -EINVAL; + + ret = gpio_request_by_name(dev, "rst-gpios", 0, + &priv->rst_desc, GPIOD_IS_OUT); + if (ret) + goto fail_rst; + + ret = gpio_request_by_name(dev, "clk-gpios", 0, + &priv->clk_desc, GPIOD_IS_OUT); + if (ret) + goto fail_clk; + + ret = gpio_request_by_name(dev, "dat-gpios", 0, + &priv->dat_desc, 0); + if (ret) + goto fail_dat; + + ret = ht1380_reset_on(priv); + if (ret) + goto fail; + + return 0; + +fail: + dm_gpio_free(dev, &priv->dat_desc); +fail_dat: + dm_gpio_free(dev, &priv->clk_desc); +fail_clk: + dm_gpio_free(dev, &priv->rst_desc); +fail_rst: + return ret; +} + +static int ht1380_remove(struct udevice *dev) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + + dm_gpio_free(dev, &priv->rst_desc); + dm_gpio_free(dev, &priv->clk_desc); + dm_gpio_free(dev, &priv->dat_desc); + + return 0; +} + +static const struct rtc_ops ht1380_rtc_ops = { + .get = ht1380_rtc_get, + .set = ht1380_rtc_set, +}; + +static const struct udevice_id ht1380_rtc_ids[] = { + { .compatible = "holtek,ht1380" }, + { } +}; + +U_BOOT_DRIVER(rtc_ht1380) = { + .name = "rtc-ht1380", + .id = UCLASS_RTC, + .probe = ht1380_probe, + .remove = ht1380_remove, + .of_match = ht1380_rtc_ids, + .ops = &ht1380_rtc_ops, + .priv_auto = sizeof(struct ht1380_priv), +}; -- 2.34.1

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[PATCH 0/3] uniphier: solve some issues and update
by Dai Okamura 03 Jan '23

03 Jan '23

This is a series of corrections for uniphier SoCs. - Fix boot failure on PXs3 Ref board - Migrate to DM_TIMER of arm a9 global timer, and remove CONFIG_SYS_TIMER_RATE (to meet the deadline 2023.01 just in time!) Dai Okamura (3): pinctrl: uniphier: add check if pins are valid pinctrl: uniphier: add ethernet TX pin data for PXs3 arm: uniphier: use DM_TIMER of arm a9 global timer arch/arm/dts/uniphier-v7-u-boot.dtsi | 4 ++ arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/arm32/Makefile | 2 - arch/arm/mach-uniphier/arm32/timer.c | 39 ------------------- configs/uniphier_v7_defconfig | 2 + .../pinctrl/uniphier/pinctrl-uniphier-core.c | 3 ++ .../pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 20 +++++++++- include/configs/uniphier.h | 3 +- 8 files changed, 30 insertions(+), 44 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm32/timer.c -- 2.35.1 >From 6efd1b587db0550014af833e2c3bee3fa94e7bf0 Mon Sep 17 00:00:00 2001 From: Dai Okamura <okamura.dai(a)socionext.com> Date: Fri, 9 Dec 2022 19:52:39 +0900 Subject: [PATCH 0/4] uniphier: solve some issues and update This is a series of corrections for uniphier SoCs. - Fix boot failure on PXs3 Ref board - Fix deadlock to access i2c if failed one time - Migrate to DM_TIMER of arm a9 global timer, and remove CONFIG_SYS_TIMER_RATE (to meet the deadline 2023.01 just in time!) Dai Okamura (4): pinctrl: uniphier: add check if pins are valid pinctrl: uniphier: add ethernet TX pin data for PXs3 i2c: uniphier-f: correct error recovery arm: uniphier: use DM_TIMER of arm a9 global timer arch/arm/dts/uniphier-v7-u-boot.dtsi | 4 ++ arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/arm32/Makefile | 2 - arch/arm/mach-uniphier/arm32/timer.c | 39 ------------------- configs/uniphier_v7_defconfig | 2 + drivers/i2c/i2c-uniphier-f.c | 4 +- .../pinctrl/uniphier/pinctrl-uniphier-core.c | 3 ++ .../pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 20 +++++++++- include/configs/uniphier.h | 3 +- 9 files changed, 32 insertions(+), 46 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm32/timer.c -- 2.35.1

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[PATCH 1/2] dts: synquacer: Drop unused and undocumented SPI properties
by Rob Herring 03 Jan '23

03 Jan '23

'active_clk_edges' and 'chipselect_num' SPI controller properties are unused in u-boot and Linux. They are also not documented in the binding. So drop them. Signed-off-by: Rob Herring <robh(a)kernel.org> --- arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index 6b85c05458d4..9f9837b33bef 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -20,8 +20,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - active_clk_edges; - chipselect_num = <1>; flash@0 { #address-cells = <1>; -- 2.35.1

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[PATCH 0/4] Synquacer DT schema fixes
by Rob Herring 03 Jan '23

03 Jan '23

This is a series of DT fixes for the Synquacer. These issues were found running the dtschema tools. I don't have a board, but Ilias has tested the changes for me. Thanks! Signed-off-by: Rob Herring <robh(a)kernel.org> --- Rob Herring (4): dts: synquacer: Drop CPU 'arm,armv8' compatibles dts: synquacer: Use generic node names dts: synquacer: Fix "arm,armv7-timer-mem" node address sizes dts: synquacer: Fix idle-states 'entry-method' value .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 2 +- arch/arm/dts/synquacer-sc2a11-developerbox.dts | 2 +- arch/arm/dts/synquacer-sc2a11.dtsi | 70 +++++++++++----------- 3 files changed, 37 insertions(+), 37 deletions(-) --- base-commit: bebb393b340295edb9ba50a996fc0510cd1b6ac0 change-id: 20221206-synquacer-dts-521500f88a1d Best regards, -- Rob Herring <robh(a)kernel.org>

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[PATCH] arm: dts: ti: k3-am64-mcu: Add pinctrl
by Christian Gmeiner 03 Jan '23

03 Jan '23

Add the definition of the pinctrl for the MCU domain. Same as kernel commit 500e6dfbb465531150ac6e2ff0856dd357ddc8a4 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- arch/arm/dts/k3-am64-mcu.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi index 59cc58f7d0..2bb5c9ff17 100644 --- a/arch/arm/dts/k3-am64-mcu.dtsi +++ b/arch/arm/dts/k3-am64-mcu.dtsi @@ -97,4 +97,12 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x4084000 0x00 0x84>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; -- 2.38.1

3 2

[PATCH] powerpc: dts: keymile: Deduplicate binman code
by Pali Rohár 03 Jan '23

03 Jan '23

kmcent2-u-boot.dtsi file contains copy of powerpc u-boot.dtsi binman file. So remove code duplication and replace it by including u-boot.dtsi file. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/powerpc/dts/kmcent2-u-boot.dtsi | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index ab76a9f1226c..d0277627644b 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -74,24 +74,6 @@ compatible = "fsl,pcie-t104x"; law_trgt_if = <0>; }; - - binman { - filename = "u-boot-with-dtb.bin"; - skip-at-start = <CONFIG_SYS_TEXT_BASE>; - sort-by-offset; - pad-byte = <0xff>; - size = <CONFIG_SYS_MONITOR_LEN>; - - u-boot-with-ucode-ptr { - offset = <CONFIG_SYS_TEXT_BASE>; - optional-ucode; - }; - - u-boot-dtb-with-ucode { - align = <256>; - }; - powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; - }; - }; }; + +#include "u-boot.dtsi" -- 2.20.1

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Rockchip RK3328 4-byte addressing problem in SPI
by Marcin Woźniak 03 Jan '23

03 Jan '23

Hello, I would like to let you know how i've lost about 2 weeks because of lack of Rockchip BOOTROM documentation. I tried to use Mainline Uboot to Boot NanoPI R2S using soldered SPI Winbond 25Q256 chip. I had to make some patches in Uboot core files to make it work. First one adds SPI boot device. File |arch/arm/mach-rockchip/rk3328/rk3328.c with adding: | |[BROM_BOOTSOURCE_SPINOR] "/spi@ff190000", |const char * const boot_devices || Second was |arch/arm/mach-rockchip/spl-boot-order.c and last if statement:| |if (!uclass_get_device_by_of_offset(UCLASS_SPI, node, &parent)) return BOOT_DEVICE_SPI;| || This patch is added because RockChip SPI driver is using UCLASS_SPI instead of SPI_FLASH so boot device wasn't connecting with right DM Driver rk_spi.c Third one fixed SPL and it was added at the end: |drivers/spi/rk_spi.c | |DM_DRIVER_ALIAS(rockchip_rk3288_spi, rockchip_rk3328_spi);| After that board booted successfully. Second bigger problem was a mistake and lack of RockChip Bootrom documentation. I've soldered 32Mbyte Flash and didn't know that U-Boot in SPL was switching it's 3-byte address mode to 4-byte one to gain access to full 32 Mbytes. The problem was that board booted in cold-start but after issuing "reset" - it was going to MASKROM mode like no SPI was soldered or empty. After loosing two weeks i figured that RockChip bootrom talks to SPI using only 3-byte addressing. So leaving 4-byte switched by UBoot SPI chip made it unusable to RockChip Bootrom. I found this by dumping Bootrom and decompiling it. I don't know if it's enough information to make a patch to MainLine (at least for SPI boot in RK3328). Problem with 3-byte addressing is a complete different story. Sorry for my "unproffesional" mail. I am writing this type of message for a first time. Marcin || |||||||| ||

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[PATCH v2 0/2] rockchip: rk3399: pass platform parameter to TF-A
by Quentin Schulz 03 Jan '23

03 Jan '23

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> Finally pass the FDT address to TF-A since it now gracefully fallbacks to hardcoded defaults if it cannot parse it. This allows us to avoid modifying hardcoded values in TF-A to enable the console. This was tested with TF-A v2.7.0 on Puma Haikou RK3399. We do this only for new RK3399 boards, where this will be a conscious choice to enable CONFIG_SPL_ATF_NO_PLATFORM_PARAM, and Puma since it's been tested with upstream TF-A. The imply condition on SPL_ATF is always true because SPL_ATF is selected for all RK3399-based boards in arch/arm/mach-rockchip/Kconfig. For board maintainers who received this mail, this patch series does not modify anything for your board. However, this highlights that your board does not make use of a feature (passing U-Boot DTB to TF-A) I find useful. I know this has been a pain point for some of you since TF-A has a default baudrate of 115200 on UART2 for its debug console which meant you had the choice of: 1) patch TF-A to run at 1500000 baudrate instead (Rockchip's BSP default) and/or a different UART controller than UART2, 2) not have TF-A output, You're now aware there's a third choice: disable SPL_ATF_NO_PLATFORM_PARAM Kconfig option if your TF-A is of version 2.4 or newer. Up to you to send a patch for your board defconfig. This option was not disabled on all platforms on purpose since Kever prefers to be careful since some boards might require downstream/blob-only TF-A that are older than 2.4 version. To: Simon Glass <sjg(a)chromium.org> To: Philipp Tomsich <philipp.tomsich(a)vrull.eu> To: Kever Yang <kever.yang(a)rock-chips.com> To: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> To: Andy Yan <andy.yan(a)rock-chips.com> To: Manivannan Sadhasivam <manivannan.sadhasivam(a)linaro.org> To: Nick Xie <nick(a)khadas.com> To: Jagan Teki <jagan(a)amarulasolutions.com> To: Deepak Das <deepakdas.linux(a)gmail.com> To: Alexandre Vicenzi <linux(a)alxd.me> To: Xiaobo Tian <peterwillcn(a)gmail.com> To: Peter Robinson <pbrobinson(a)gmail.com> To: Klaus Goger <klaus.goger(a)theobroma-systems.com> To: Levin Du <djw(a)t-chip.com.cn> To: Suniel Mahesh <sunil(a)amarulasolutions.com> To: Akash Gajjar <akash(a)openedev.com> Cc: Hugh Cole-Baker <sigmaris(a)gmail.com> Cc: Walter Lozano <walter.lozano(a)collabora.com> Cc: Quentin Schulz <foss+uboot(a)0leil.net> Cc: u-boot(a)lists.denx.de Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Changes in v2: - keep the option selected for existing boards except Puma, - added board maintainers to recipients of this mail, - Link to v1: https://lore.kernel.org/r/20221114-rk3399-tf-a-plat-param-v1-0-0f873897bda7… --- Quentin Schulz (2): rockchip: rk3399: pass platform parameter to TF-A by default for new RK3399 boards rockchip: puma: pass platform parameter to TF-A arch/arm/mach-rockchip/Kconfig | 1 - configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/eaidk-610-rk3399_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/orangepi-rk3399_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + 26 files changed, 25 insertions(+), 1 deletion(-) --- base-commit: 582e3c9fb2337c2f49faa73ac86dde25f4d56901 change-id: 20221114-rk3399-tf-a-plat-param-3ab055f40b9e Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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Possible bug in BTRFS w/ Duplication
by Sam Winchenbach 03 Jan '23

03 Jan '23

Hello, Hello, I have hit the following situation when trying to load files from a BTRFS partition with duplication enabled. In the first example I read a 16KiB file - __btrfs_map_block() changes the length to something larger than the file being read. This works fine, as length is later clamped to the file size. In the second example, __btrfs_map_block() changes the length parameter to something smaller than the file (the size of a stripe). This seems to break this check here: read = len; num_copies = btrfs_num_copies(fs_info, logical, len); for (i = 1; i <= num_copies; i++) { ret = read_extent_data(fs_info, dest, logical, &read, i); if (ret < 0 || read != len) { continue; } finished = true; break; } The problem being that read is always less than len. I am not sure if __btrfs_map_block is changing "len" to the incorrect value, or if there is some logic in "read_extent_data" that isn't correct. Any pointers on how this code is supposed to work would be greatly appreciated. Thanks. === EXAMPLE 2 === Zynq> load mmc 1:0 0 16K [btrfs_file_read,fs/btrfs/inode.c:710] === read the aligned part === [btrfs_read_extent_reg,fs/btrfs/inode.c:458] before read_extent_data (ret = 0, read = 16384, len = 16384) [read_extent_data,fs/btrfs/disk-io.c:547] before __btrfs_map_block (len = 16384) [read_extent_data,fs/btrfs/disk-io.c:550] after __btrfs_map_block (len = 28672) [read_extent_data,fs/btrfs/disk-io.c:565] before __btrfs_devread (len = 16384) [read_extent_data,fs/btrfs/disk-io.c:568] after __btrfs_devread (len = 16384) [btrfs_read_extent_reg,fs/btrfs/inode.c:460] after read_extent_data (ret = 0, read = 16384, len = 16384) cur: 0, extent_num_bytes: 16384, aligned_end: 16384 16384 bytes read in 100 ms (159.2 KiB/s) === EXAMPLE 2 === Zynq> load mmc 1:0 0 32K [btrfs_file_read,fs/btrfs/inode.c:710] === read the aligned part === [btrfs_read_extent_reg,fs/btrfs/inode.c:458] before read_extent_data (ret = 0, read = 32768, len = 32768) [read_extent_data,fs/btrfs/disk-io.c:547] before __btrfs_map_block (len = 32768) [read_extent_data,fs/btrfs/disk-io.c:550] after __btrfs_map_block (len = 12288) [read_extent_data,fs/btrfs/disk-io.c:565] before __btrfs_devread (len = 12288) [read_extent_data,fs/btrfs/disk-io.c:568] after __btrfs_devread (len = 12288) [btrfs_read_extent_reg,fs/btrfs/inode.c:460] after read_extent_data (ret = 0, read = 12288, len = 32768) [btrfs_read_extent_reg,fs/btrfs/inode.c:458] before read_extent_data (ret = 0, read = 12288, len = 32768) [read_extent_data,fs/btrfs/disk-io.c:547] before __btrfs_map_block (len = 12288) [read_extent_data,fs/btrfs/disk-io.c:550] after __btrfs_map_block (len = 12288) [read_extent_data,fs/btrfs/disk-io.c:565] before __btrfs_devread (len = 12288) [read_extent_data,fs/btrfs/disk-io.c:568] after __btrfs_devread (len = 12288) [btrfs_read_extent_reg,fs/btrfs/inode.c:460] after read_extent_data (ret = 0, read = 12288, len = 32768) file: fs/btrfs/inode.c, line: 468 cur: 0, extent_num_bytes: 32768, aligned_end: 32768 -----> btrfs_read_extent_reg: -5, line: 758 BTRFS: An error occurred while reading file 32K Failed to load '32K' Sam Winchenbach Embedded Software Engineer III Tethers Unlimited, Inc. | Connect Your Universe | www.tethers.com swinchenbach(a)tethers.com | C: 207-974-6934 11711 North Creek Pkwy # D113, Bothell, WA 98011-8808, USA CONFIDENTIALITY NOTE: The information contained in this transmission may be privileged and confidential information and is intended only for the use of the individual or entity named above. If the reader of this message is not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this communication is strictly prohibited. If you have received this transmission in error, please immediately reply to the sender that you have received this communication in error and then delete it. Thank you. ITAR/EAR NOTICE: This email and/or attachments may contain technical data controlled by the US International Traffic and Arms Regulations (ITAR) or the Export Administration Regulations (EAR). Export from the US or disclosure to foreign nationals in the U.S. without an export license is a violation of law. It is the recipient's responsibility to assure this item can be legally shared with another party.

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[PATCH 0/3] Initial support for Pinephone Pro
by Peter Robinson 03 Jan '23

03 Jan '23

This adds initial support for the PINE64 Pinephone Pro. It's a rebase to upstream core rk3399 DT pieces, and the addition of the upstream PPP DT from 6.1-rc1 and the U-Boot pieces are based on my work on the Pinebook Pro. Peter Robinson (3): arm64: dts: rk3399: sync rk3399.dtsi from 6.1-rc1 arm64: dts: rk3399: Add upstream Pinephone Pro dts rockchip: Add initial support for the PINE64 Pinephone Pro arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 39 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 398 ++++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 36 +- arch/arm/dts/rk3399.dtsi | 200 ++++++++- arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinephone-pro-rk3399/Makefile | 1 + .../pinephone-pro-rk3399.c | 76 ++++ configs/pinephone-pro-rk3399_defconfig | 104 +++++ drivers/clk/rockchip/clk_rk3399.c | 2 +- include/configs/pinephone-pro-rk3399.h | 19 + include/dt-bindings/clock/rk3399-cru.h | 24 +- include/dt-bindings/power/rk3399-power.h | 1 + 16 files changed, 875 insertions(+), 63 deletions(-) create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c create mode 100644 configs/pinephone-pro-rk3399_defconfig create mode 100644 include/configs/pinephone-pro-rk3399.h -- 2.38.1

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