September 2022 - U-Boot

Re: [PATCH] mmc: ftsdc010: make command timeout 250 ms as in the comment
by Rick Chen 05 Sep '22

05 Sep '22

> From: Sergei Antonov <saproj(a)gmail.com> > Sent: Friday, September 02, 2022 3:40 PM > To: u-boot(a)lists.denx.de > Cc: jh80.chung(a)samsung.com; peng.fan(a)nxp.com; yamada.masahiro(a)socionext.com; sjg(a)chromium.org; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Sergei Antonov <saproj(a)gmail.com> > Subject: [PATCH] mmc: ftsdc010: make command timeout 250 ms as in the comment > > Get rid of discrepancy beween comment /* 250 ms */ and code which shifts by 4 thus dividing by 16. > So change code to shift by 2 and make the timeout value 250 ms. > > Signed-off-by: Sergei Antonov <saproj(a)gmail.com> > --- > drivers/mmc/ftsdc010_mci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 570d54cf9d8f..cabb747fbbdb 100644 > --- a/drivers/mmc/ftsdc010_mci.c > +++ b/drivers/mmc/ftsdc010_mci.c > @@ -30,7 +30,7 @@ > #include <syscon.h> > #include <linux/err.h> > > -#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ > +#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */ Reviewed-by: Rick Chen <rick(a)andestech.com>

1 0

[PATCH v2 0/8] Enable CONFIG_TIMER for all Kirkwood / MVEBU boards
by Stefan Roese 04 Sep '22

04 Sep '22

This patchset enhaces the recently added Orion Timer driver to support all other Kirkwood & 32bit MVEBU Armada platforms. Additionally, this timer support is then enabled per default for those platforms, so that the board config files don't need to be changed. Also necessary is some dts hacking, so that the timer DT node is available in early U-Boot stages. I've successfully tested this patchset on an Armada XP board. Additional test on other boards and platforms are very welcome and necessary. Thanks, Stefan Stefan Roese (8): timer: orion-timer: Use timer_conv_64() to fix timer wrap around timer: orion-timer: Add support for other Armada SoC's timer: orion-timer: Add timer_get_boot_us() for BOOTSTAGE support arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms arm: mvebu: dts: Makefile: Compile Armada 375 dtb in a separate step arm: mvebu: dts: armada-375.dtsi: Add timer0 & timer1 arm: mvebu: dts: mvebu-u-boot.dtsi: Add "u-boot,dm-pre-reloc" to timer DT node kirkwood: lsxl: Sync defconfigs arch/arm/Kconfig | 4 ++ arch/arm/dts/Makefile | 6 ++- arch/arm/dts/armada-375.dtsi | 4 +- arch/arm/dts/mvebu-u-boot.dtsi | 11 +++++ arch/arm/mach-mvebu/include/mach/config.h | 5 --- configs/lschlv2_defconfig | 3 -- configs/lsxhl_defconfig | 3 -- drivers/timer/Kconfig | 5 ++- drivers/timer/orion-timer.c | 53 +++++++++++++++++++++-- 9 files changed, 75 insertions(+), 19 deletions(-) -- 2.37.3

4 21

[PATCH v2 0/2] efi_selftest: unit test for EFI Conformance Profile Table
by Heinrich Schuchardt 04 Sep '22

04 Sep '22

Add a new unit test to test the integrity of the EFI Conformance Profile Table. The first patch contains the prerequisite refactoring. v2: add missing efi_selftest_ecpt.c Heinrich Schuchardt (2): efi_selftest: export efi_st_get_config_table() efi_selftest: unit test for EFI Conformance Profile Table include/efi_selftest.h | 11 ++++ lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest.c | 38 +++++++------- lib/efi_selftest/efi_selftest_ecpt.c | 76 ++++++++++++++++++++++++++++ lib/efi_selftest/efi_selftest_fdt.c | 17 ------- lib/efi_selftest/efi_selftest_util.c | 11 ++++ 6 files changed, 118 insertions(+), 36 deletions(-) create mode 100644 lib/efi_selftest/efi_selftest_ecpt.c -- 2.37.2

2 6

[PATCH] clk: rockchip: rk3399: Fix Unknown clock 77 on mmc@fe310000
by Michal Suchanek 04 Sep '22

04 Sep '22

Adding some debug prints I can see: MMC: mmc@fe320000: Got clock clock-controller@ff760000 76 mmc@fe310000: Got clock clock-controller@ff760000 77 Unknown clock 77 rockchip_dwmmc_get_mmc_clk: err=-2 mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0 According to kernel code the SDIO clock is identical to SDMMC clock except for the con 16->15 change. Add support for the clock to avoid the error. Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/clk/rockchip/clk_rk3399.c | 66 ++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 23 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 7d31a9f22a..97bf1c6e15 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -728,6 +728,12 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id) u32 div, con; switch (clk_id) { + case HCLK_SDIO: + case SCLK_SDIO: + con = readl(&cru->clksel_con[15]); + /* dwmmc controller have internal div 2 */ + div = 2; + break; case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->clksel_con[16]); @@ -750,37 +756,46 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id) return DIV_TO_RATE(GPLL_HZ, div); } +static void rk3399_dwmmc_set_clk(struct rockchip_cru *cru, + unsigned int con, ulong set_rate) +{ + /* Select clk_sdmmc source from GPLL by default */ + /* mmc clock defaulg div 2 internal, provide double in cru */ + int src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); + + if (src_clk_div > 128) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); + assert(src_clk_div - 1 < 128); + rk_clrsetreg(&cru->clksel_con[con], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } +} + static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru, ulong clk_id, ulong set_rate) { - int src_clk_div; - int aclk_emmc = 198 * MHz; - switch (clk_id) { + case HCLK_SDIO: + case SCLK_SDIO: + rk3399_dwmmc_set_clk(cru, 15, set_rate); + break; case HCLK_SDMMC: case SCLK_SDMMC: - /* Select clk_sdmmc source from GPLL by default */ - /* mmc clock defaulg div 2 internal, provide double in cru */ - src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); - - if (src_clk_div > 128) { - /* use 24MHz source for 400KHz clock */ - src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); - assert(src_clk_div - 1 < 128); - rk_clrsetreg(&cru->clksel_con[16], - CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, - CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | - (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); - } else { - rk_clrsetreg(&cru->clksel_con[16], - CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, - CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | - (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); - } + rk3399_dwmmc_set_clk(cru, 16, set_rate); break; - case SCLK_EMMC: + case SCLK_EMMC: { + int aclk_emmc = 198 * MHz; /* Select aclk_emmc source from GPLL */ - src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc); + int src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc); + assert(src_clk_div - 1 < 32); rk_clrsetreg(&cru->clksel_con[21], @@ -797,6 +812,7 @@ static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru, CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); break; + } default: return -EINVAL; } @@ -918,6 +934,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk) switch (clk->id) { case 0 ... 63: return 0; + case HCLK_SDIO: + case SCLK_SDIO: case HCLK_SDMMC: case SCLK_SDMMC: case SCLK_EMMC: @@ -992,6 +1010,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case PCLK_PERILP1: return 0; + case HCLK_SDIO: + case SCLK_SDIO: case HCLK_SDMMC: case SCLK_SDMMC: case SCLK_EMMC: -- 2.37.1

2 1

[PATCH v2] gpio: ftgpio010: Add support for Faraday Technology FTGPIO010
by Sergei Antonov 04 Sep '22

04 Sep '22

Add Faraday Technology's FTGPIO010 controller driver. Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- v1 -> v2: Replace setbits_le32() with a simpler function out_le32(). Replace readl() with in_le32() to respect endianness. drivers/gpio/Kconfig | 6 +++ drivers/gpio/Makefile | 1 + drivers/gpio/ftgpio010.c | 100 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 drivers/gpio/ftgpio010.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c949f9d2f7cc..2a60478b476a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -605,4 +605,10 @@ config TURRIS_OMNIA_MCU help Support for GPIOs on MCU connected to Turris Omnia via i2c. +config FTGPIO010 + bool "Faraday Technology FTGPIO010 driver" + depends on DM_GPIO + help + Support for GPIOs on Faraday Technology's FTGPIO010 controller. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9d718a554e59..eee7908871d8 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o +obj-$(CONFIG_FTGPIO010) += ftgpio010.o diff --git a/drivers/gpio/ftgpio010.c b/drivers/gpio/ftgpio010.c new file mode 100644 index 000000000000..fa6b180963d3 --- /dev/null +++ b/drivers/gpio/ftgpio010.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Faraday Technology's FTGPIO010 controller. + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/gpio.h> + +struct ftgpio010_regs { + u32 out; + u32 in; + u32 direction; + u32 reserved; + u32 set; + u32 clear; +}; + +struct ftgpio010_plat { + struct ftgpio010_regs __iomem *regs; +}; + +static int ftgpio010_direction_input(struct udevice *dev, unsigned int pin) +{ + struct ftgpio010_plat *plat = dev_get_plat(dev); + struct ftgpio010_regs *const regs = plat->regs; + + clrbits_le32(&regs->direction, 1 << pin); + return 0; +} + +static int ftgpio010_direction_output(struct udevice *dev, unsigned int pin, + int val) +{ + struct ftgpio010_plat *plat = dev_get_plat(dev); + struct ftgpio010_regs *const regs = plat->regs; + + /* change the data first, then the direction. to avoid glitch */ + out_le32(val ? &regs->set : &regs->clear, 1 << pin); + setbits_le32(&regs->direction, 1 << pin); + + return 0; +} + +static int ftgpio010_get_value(struct udevice *dev, unsigned int pin) +{ + struct ftgpio010_plat *plat = dev_get_plat(dev); + struct ftgpio010_regs *const regs = plat->regs; + + return in_le32(&regs->in) >> pin & 1; +} + +static int ftgpio010_set_value(struct udevice *dev, unsigned int pin, int val) +{ + struct ftgpio010_plat *plat = dev_get_plat(dev); + struct ftgpio010_regs *const regs = plat->regs; + + out_le32(val ? &regs->set : &regs->clear, 1 << pin); + return 0; +} + +static int ftgpio010_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = ofnode_read_u32_default(dev_ofnode(dev), + "nr-gpios", 32); + return 0; +} + +static int ftgpio010_of_to_plat(struct udevice *dev) +{ + struct ftgpio010_plat *plat = dev_get_plat(dev); + + plat->regs = dev_read_addr_ptr(dev); + return 0; +} + +static const struct dm_gpio_ops ftgpio010_ops = { + .direction_input = ftgpio010_direction_input, + .direction_output = ftgpio010_direction_output, + .get_value = ftgpio010_get_value, + .set_value = ftgpio010_set_value, +}; + +static const struct udevice_id ftgpio010_ids[] = { + { .compatible = "faraday,ftgpio010" }, + { } +}; + +U_BOOT_DRIVER(ftgpio010) = { + .name = "ftgpio010", + .id = UCLASS_GPIO, + .of_match = ftgpio010_ids, + .ops = &ftgpio010_ops, + .of_to_plat = ftgpio010_of_to_plat, + .plat_auto = sizeof(struct ftgpio010_plat), + .probe = ftgpio010_probe, +}; -- 2.34.1

2 1

[PATCH v1] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files
by Johan Jonker 04 Sep '22

04 Sep '22

Move all rk3128 u-boot specific properties in separate dtsi files. Sort emmc node. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3128-evb-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3128-evb.dts | 10 +++++----- arch/arm/dts/rk3128-u-boot.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/dts/rk3128.dtsi | 11 ----------- 4 files changed, 39 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/rk3128-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3128-u-boot.dtsi diff --git a/arch/arm/dts/rk3128-evb-u-boot.dtsi b/arch/arm/dts/rk3128-evb-u-boot.dtsi new file mode 100644 index 00000000..8b16bbe4 --- /dev/null +++ b/arch/arm/dts/rk3128-evb-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3128-u-boot.dtsi" + +&emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index a407ac2d..e7d8f7c9 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -37,6 +37,11 @@ }; }; +&emmc { + fifo-mode; + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -74,11 +79,6 @@ status = "okay"; }; -&emmc { - fifo-mode; - status = "okay"; -}; - &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi new file mode 100644 index 00000000..dbb41fe1 --- /dev/null +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" + +/ { + dmc: dmc@20004000 { + compatible = "rockchip,rk3128-dmc", "syscon"; + reg = <0x0 0x20004000 0x0 0x1000>; + u-boot,dm-pre-reloc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&emmc { + max-frequency = <150000000>; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + max-frequency = <150000000>; +}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 62fd5343..589818da 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -237,14 +237,7 @@ clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; }; - dmc: dmc@20004000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3128-dmc", "syscon"; - reg = <0x0 0x20004000 0x0 0x1000>; - }; - cru: clock-controller@20000000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-cru"; reg = <0x20000000 0x1000>; rockchip,grf = <&grf>; @@ -440,7 +433,6 @@ sdmmc: dwmmc@10214000 { compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; - max-frequency = <150000000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -453,10 +445,8 @@ }; emmc: dwmmc@1021c000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; - max-frequency = <150000000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; @@ -538,7 +528,6 @@ }; grf: syscon@20008000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-grf", "syscon"; reg = <0x20008000 0x1000>; }; -- 2.20.1

1 0

[PATCH v1] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts
by Johan Jonker 04 Sep '22

04 Sep '22

Bulk convert rk3128 DT gpios to their constant counterparts. sed -i -f script.sed rk3128.dtsi sed -i -f script.sed rk3128-evb.dts ================================ /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO$[0-9]$ /<\1 /g s/<$[^ ][^ ]* *$0 /<\1RK_PA0 /g s/<$[^ ][^ ]* *$1 /<\1RK_PA1 /g s/<$[^ ][^ ]* *$2 /<\1RK_PA2 /g s/<$[^ ][^ ]* *$3 /<\1RK_PA3 /g s/<$[^ ][^ ]* *$4 /<\1RK_PA4 /g s/<$[^ ][^ ]* *$5 /<\1RK_PA5 /g s/<$[^ ][^ ]* *$6 /<\1RK_PA6 /g s/<$[^ ][^ ]* *$7 /<\1RK_PA7 /g s/<$[^ ][^ ]* *$8 /<\1RK_PB0 /g s/<$[^ ][^ ]* *$9 /<\1RK_PB1 /g s/<$[^ ][^ ]* *$10 /<\1RK_PB2 /g s/<$[^ ][^ ]* *$11 /<\1RK_PB3 /g s/<$[^ ][^ ]* *$12 /<\1RK_PB4 /g s/<$[^ ][^ ]* *$13 /<\1RK_PB5 /g s/<$[^ ][^ ]* *$14 /<\1RK_PB6 /g s/<$[^ ][^ ]* *$15 /<\1RK_PB7 /g s/<$[^ ][^ ]* *$16 /<\1RK_PC0 /g s/<$[^ ][^ ]* *$17 /<\1RK_PC1 /g s/<$[^ ][^ ]* *$18 /<\1RK_PC2 /g s/<$[^ ][^ ]* *$19 /<\1RK_PC3 /g s/<$[^ ][^ ]* *$20 /<\1RK_PC4 /g s/<$[^ ][^ ]* *$21 /<\1RK_PC5 /g s/<$[^ ][^ ]* *$22 /<\1RK_PC6 /g s/<$[^ ][^ ]* *$23 /<\1RK_PC7 /g s/<$[^ ][^ ]* *$24 /<\1RK_PD0 /g s/<$[^ ][^ ]* *$25 /<\1RK_PD1 /g s/<$[^ ][^ ]* *$26 /<\1RK_PD2 /g s/<$[^ ][^ ]* *$27 /<\1RK_PD3 /g s/<$[^ ][^ ]* *$28 /<\1RK_PD4 /g s/<$[^ ][^ ]* *$29 /<\1RK_PD5 /g s/<$[^ ][^ ]* *$30 /<\1RK_PD6 /g s/<$[^ ][^ ]* *$31 /<\1RK_PD7 /g s/<$[^ ][^ ]* *[^ ][^ ]* *$0 /<\1RK_FUNC_GPIO /g s/<$[^ ][^ ]* *[^ ][^ ]* *$RK_FUNC_$[1-9]$ /<\1\2 /g Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3128-evb.dts | 4 +- arch/arm/dts/rk3128.dtsi | 86 ++++++++++++++++++------------------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index 2fb2b0da..a407ac2d 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -82,13 +82,13 @@ &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 5d2499c1..62fd5343 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -618,85 +618,85 @@ */ emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; emmc_pwren: emmc-pwren { - rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; nandc{ nandc_ale:nandc-ale { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cle:nandc-cle { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_wrn:nandc-wrn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdn:nandc-rdn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdy:nandc-rdy { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cs0:nandc-cs0 { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_data: nandc-data { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, + <1 RK_PC3 2 &pcfg_pull_none>; }; }; @@ -727,75 +727,75 @@ pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 3 &pcfg_pull_none>, - <2 21 3 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, + <2 RK_PC5 3 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; }; }; spi0 { spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; }; -- 2.20.1

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Pull request of efi-2022-10-rc4-2
by Heinrich Schuchardt 03 Sep '22

03 Sep '22

Dear Tom, The following changes since commit 67fe8cc0016756f3479288b3f67d59a517e512d5: Merge tag 'efi-2022-10-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-09-02 09:09:47 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2022-10-rc4-2 for you to fetch changes up to fbc04c0dab139c12ed61500fac3cc204009e8c54: efi_loader: fix display of NVMe EUI-64 (2022-09-03 10:49:17 +0200) Gitlab CI showed no issues: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/13319 ---------------------------------------------------------------- Pull request of efi-2022-10-rc4-2 UEFI: * provide EFI Conformance Profile Table * fix display of NVMe EUI-64 * fixes for Simple Text Input Ex Protocol * fix exception unit-test on non-x86 sandbox ---------------------------------------------------------------- Heinrich Schuchardt (5): efi_loader: printing UEFI revision in helloworld.efi efi_loader: compliance Simple Text Input Ex Protocol efi_loader: support CTRL+\ - CTRL+_ efi_selftest: on sandbox use host specific assembly efi_loader: fix display of NVMe EUI-64 Jose Marinho (2): efi: Create ECPT table efi: ECPT add EBBRv2.0 conformance profile include/efi_api.h | 16 ++++++ include/efi_loader.h | 7 +++ lib/efi_loader/Kconfig | 17 ++++++ lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_conformance.c | 60 +++++++++++++++++++++ lib/efi_loader/efi_console.c | 5 ++ lib/efi_loader/efi_device_path_to_text.c | 7 +-- lib/efi_loader/efi_setup.c | 6 +++ lib/efi_loader/helloworld.c | 66 ++++++++++++++++++----- lib/efi_selftest/efi_selftest_miniapp_exception.c | 9 +++- lib/uuid.c | 4 ++ 11 files changed, 182 insertions(+), 16 deletions(-) create mode 100644 lib/efi_loader/efi_conformance.c

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[PATCH v2] net: enetc: Fix use after free issue in fsl_enetc.c
by Siarhei Yasinski 03 Sep '22

03 Sep '22

If ethernet connected to SFP, like this: &enetc_port0 { phy-connection-type = "sgmii"; sfp = <&sfp0>; managed = "in-band-status"; status = "okay"; }; Then enetc_config_phy returns -ENODEV and memory containing mdio interface is freeing. It's better to unregister and free mdio resources. Signed-off-by: Siarhei Yasinski <siarhei.yasinski(a)sintecs.eu> --- drivers/net/fsl_enetc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index cd4c2c29a6..d3326054a2 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -22,6 +22,8 @@ #define ENETC_DRIVER_NAME "enetc_eth" +static int enetc_remove(struct udevice *dev); + /* * sets the MAC address in IERB registers, this setting is persistent and * carried over to Linux. @@ -319,6 +321,7 @@ static int enetc_config_phy(struct udevice *dev) static int enetc_probe(struct udevice *dev) { struct enetc_priv *priv = dev_get_priv(dev); + int ret; if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) { enetc_dbg(dev, "interface disabled\n"); @@ -350,7 +353,10 @@ static int enetc_probe(struct udevice *dev) enetc_start_pcs(dev); - return enetc_config_phy(dev); + ret = enetc_config_phy(dev); + if(ret) + enetc_remove(dev); + return ret; } /* -- 2.25.1

2 2

[PATCH v2 1/1] doc: man-page for tftpput
by Heinrich Schuchardt 03 Sep '22

03 Sep '22

Provide a man-page for the tftpput command. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- v2: fix typos --- doc/usage/cmd/tftpput.rst | 69 +++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 2 files changed, 70 insertions(+) create mode 100644 doc/usage/cmd/tftpput.rst diff --git a/doc/usage/cmd/tftpput.rst b/doc/usage/cmd/tftpput.rst new file mode 100644 index 0000000000..c14df86628 --- /dev/null +++ b/doc/usage/cmd/tftpput.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +tftpput command +=============== + +Synopsis +-------- + +:: + + tftpput address size [[hostIPaddr:]filename] + +Decription +---------- + +The tftpput command is used to transfer a file to a TFTP server. + +address + memory address where the data starts + +size + number of bytes to be transferred + +hostIPaddr + IP address of the TFTP server, defaults to $serverip + +filename + path of the file to be written. If not provided, the client's IP address is + used to construct a default file name, e.g. C0.A8.00.28.img for IP address + 192.168.0.40. + +Example +------- + +In the example the following steps are executed: + +* setup client network address +* load a file from the SD-card +* send the file via TFTP to a server + +:: + + => setenv autoload no + => dhcp + BOOTP broadcast 1 + DHCP client bound to address 192.168.1.40 (7 ms) + => load mmc 0:1 $loadaddr test.txt + 260096 bytes read in 13 ms (19.1 MiB/s) + => tftpput $loadaddr $filesize 192.168.1.3:upload/test.txt + Using ethernet@1c30000 device + TFTP to server 192.168.1.3; our IP address is 192.168.1.40 + Filename 'upload/test.txt'. + Save address: 0x42000000 + Save size: 0x3f800 + Saving: ################# + 4.4 MiB/s + done + Bytes transferred = 260096 (3f800 hex) + => + +Configuration +------------- + +The command is only available if CONFIG_CMD_TFTPPUT=y. + +Return value +------------ + +The return value $? is 0 (true) on success and 1 (false) otherwise. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 28f9683a3e..f1beeec59c 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -63,6 +63,7 @@ Shell commands cmd/scp03 cmd/setexpr cmd/size + cmd/tftpput cmd/true cmd/ums cmd/wdt -- 2.37.2

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