September 2022 - U-Boot

Falcon mode: hangs on booting Linux
by Ayrton Leyssens 06 Sep '22

06 Sep '22

Hi all I have some problems with a TI AM335x and U-Boot Falcon mode. My Linux kernel does not want to boot 'the old way' using ATAGS in Falcon mode. Using plain U-Boot the kernel boots like it should. Setting up all: setenv bootargs root=/dev/mmcblk0p6 console=ttyS0,115200n8; fatload mmc 1:3 0x82000000 uImage; spl export atags 0x82000000; fatwrite mmc 1:1 0x80000100 args 0x200; saveenv; reset; In this case my kernel boots. If I powercycle the board, U-Boot hangs on 'Jumping to Linux' in 'spl.c: "jump_to_image_linux"' I am using U-Boot 2020.07 Printing the args file, shows my bootargs are set. Adding debug before jump_to_image_linux, shows the Linux header is read and it knows its entry_point and load_addr Thanks for showing me the way Ayrton

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[PATCH] clk: at91: sam9x60: change parent clock from mck_pres to mck_div
by Eugen Hristev 06 Sep '22

06 Sep '22

From: Mihai Sain <mihai.sain(a)microchip.com> ddrck and qspick should have mck_div as parent clocks to be in sync with linux driver. Signed-off-by: Mihai Sain <mihai.sain(a)microchip.com> --- drivers/clk/at91/sam9x60.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 4d00ee2ddc..6b5486c6c9 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -265,10 +265,10 @@ static const struct { u8 id; u8 cid; } sam9x60_systemck[] = { - { .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, }, + { .n = "ddrck", .p = "mck_div", .id = 2, .cid = ID_DDR, }, { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, - { .n = "qspick", .p = "mck_pres", .id = 19, .cid = ID_QSPI, }, + { .n = "qspick", .p = "mck_div", .id = 19, .cid = ID_QSPI, }, }; /** -- 2.25.1

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[PATCH v16 00/10] enable menu-driven UEFI variable maintenance
by Masahisa Kojima 06 Sep '22

06 Sep '22

This series adds the menu-driven UEFI boot variable maintenance through the "eficonfig" new command. This series also adds the removable media support in bootmenu. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/eficonfig_upstream_v16 [Major Changes] - there is detailed changelog in each commit Masahisa Kojima (10): eficonfig: menu-driven addition of UEFI boot option eficonfig: add "Edit Boot Option" menu entry menu: add KEY_PLUS, KEY_MINUS and KEY_SPACE handling eficonfig: add "Delete Boot Option" menu entry bootmenu: add removable media entries eficonfig: scan media device in eficonfig startup eficonfig: add "Change Boot Order" menu entry doc:bootmenu: add description for UEFI boot support doc:eficonfig: add documentation for eficonfig command test: unit test for eficonfig cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/bootmenu.c | 22 +- cmd/eficonfig.c | 2458 +++++++++++++++++ common/menu.c | 9 + configs/sandbox_defconfig | 1 + doc/usage/cmd/bootmenu.rst | 74 + doc/usage/cmd/eficonfig.rst | 71 + doc/usage/index.rst | 1 + include/efi_config.h | 98 + include/efi_loader.h | 53 + include/menu.h | 3 + lib/efi_loader/efi_bootmgr.c | 7 + lib/efi_loader/efi_boottime.c | 52 +- lib/efi_loader/efi_console.c | 70 + lib/efi_loader/efi_disk.c | 50 + lib/efi_loader/efi_file.c | 75 +- test/py/tests/test_eficonfig/conftest.py | 40 + .../py/tests/test_eficonfig/test_eficonfig.py | 354 +++ 19 files changed, 3393 insertions(+), 53 deletions(-) create mode 100644 cmd/eficonfig.c create mode 100644 doc/usage/cmd/eficonfig.rst create mode 100644 include/efi_config.h create mode 100644 test/py/tests/test_eficonfig/conftest.py create mode 100644 test/py/tests/test_eficonfig/test_eficonfig.py -- 2.17.1

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[PATCH v2] tee: optee: rework TA bus scanning code
by Ilias Apalodimas 06 Sep '22

06 Sep '22

Late versions of OP-TEE support a pseudo bus. TAs that behave as hardware blocks (e.g TPM, RNG etc) present themselves on a bus which we can scan. Unfortunately U-Boot doesn't support that yet. It's worth noting that we already have a workaround for RNG. The details are in commit 70812bb83da6 ("tee: optee: bind rng optee driver") So let's add a list of devices based on U-Boot Kconfig options that we will scan until we properly implement the tee-bus functionality. While at it change the behaviour of the tee core itself wrt to device binding. If some device binding fails, print a warning instead of disabling OP-TEE. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Changes since v1: - remove a macro and use ARRAY_SIZE directly - print a warning instead of disabling op-tee if a driver binding fails drivers/tee/optee/core.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index a89d62aaf0b3..3cc92f09d299 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -31,6 +31,18 @@ struct optee_pdata { optee_invoke_fn *invoke_fn; }; +static const struct { + const char *drv_name; + const char *dev_name; +} optee_bus_probe[] = { +#ifdef CONFIG_RNG_OPTEE + { "optee-rng", "optee-rng" }, +#endif +#ifdef CONFIG_TPM2_FTPM_TEE + { "ftpm-tee", "ftpm-tee" }, +#endif +}; + struct rpc_param { u32 a0; u32 a1; @@ -643,7 +655,7 @@ static int optee_probe(struct udevice *dev) struct optee_pdata *pdata = dev_get_plat(dev); u32 sec_caps; struct udevice *child; - int ret; + int ret, i; if (!is_optee_api(pdata->invoke_fn)) { dev_err(dev, "OP-TEE api uid mismatch\n"); @@ -672,10 +684,13 @@ static int optee_probe(struct udevice *dev) * in U-Boot, the discovery of TA on the TEE bus is not supported: * only bind the drivers associated to the supported OP-TEE TA */ - if (IS_ENABLED(CONFIG_RNG_OPTEE)) { - ret = device_bind_driver(dev, "optee-rng", "optee-rng", &child); + + for (i = 0; i < ARRAY_SIZE(optee_bus_probe); i++) { + ret = device_bind_driver(dev, optee_bus_probe[i].drv_name, + optee_bus_probe[i].dev_name, &child); if (ret) - return ret; + dev_warn(dev, "Failed to bind device %s\n", + optee_bus_probe[i].dev_name); } return 0; -- 2.34.1

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[PATCH] ddr: fsl: Make bank_addr_bits reflect actual bits
by Sean Anderson 06 Sep '22

06 Sep '22

In both the Freescale DDR controller and the SPD spec, bank address bits are stored as the number of bank address bits minus 2. For example, if a chip had 8 banks (3 total bank address bits), the value of bank_addr_bits would be 1. This is rather surprising for users configuring their memory manually, since they can't set bank_addr_bits to the actual number of bank address bits. Rectify this. There is at least one example of this kind of mistake already, in board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank address bits, but bank_addr_bits was set to 2, implying 4 bank address bits. Such a value is reserved in BA_BITS_CS, but I suspect the controller simply ignores the top bit, making this kind of mistake harmless, if misleading. Fixes: e8a7f1c32b5 ("powerpc/t1023rdb: Add T1023 RDB board support") Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- board/freescale/ls1043ardb/ddr.c | 2 +- drivers/ddr/fsl/ctrl_regs.c | 2 +- drivers/ddr/fsl/ddr4_dimm_params.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 08b43ff5e4c..4d2fce38412 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -114,7 +114,7 @@ dimm_params_t ddr_raw_timing = { .mirrored_dimm = 0, .n_row_addr = 15, .n_col_addr = 10, - .bank_addr_bits = 0, + .bank_addr_bits = 2, .bank_group_bits = 2, .edc_config = 0, .burst_lengths_bitmask = 0x0c, diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index b5122d1a1c3..0b0b4e5cb7e 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -214,7 +214,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; #ifdef CONFIG_SYS_FSL_DDR4 - ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; + ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits - 2; bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; #else n_banks_per_sdram_device diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index e2bdc12ef2c..ea791622628 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -246,7 +246,7 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, /* SDRAM device parameters */ pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; pdimm->n_col_addr = (spd->addressing & 0x7) + 9; - pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3; + pdimm->bank_addr_bits = ((spd->density_banks >> 4) & 0x3) + 2; pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3; /* -- 2.35.1.1320.gc452695387.dirty

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[PATCH] ddr: fsl: Reduce the size of interactive options
by Sean Anderson 06 Sep '22

06 Sep '22

The interactive mode uses large several tables of options which can be configured. However, much of the contents of these tables are repetetive. For example, no struct is larger than half a kilobyte, so the offset only takes up 9 bits. Similarly, the size is only ever 4 or 8, and printhex is a boolean. Reduce the size of these fields. This reduces the size of the options tables by around 10 KiB. However, the largest contributor to the size of the options tables is the use of a pointer for the strings. A better approach would be to use a separate array of strings, and store an integer index in the options tables. However, this would require a large re-architecting of this file. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- drivers/ddr/fsl/interactive.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 2f76beb2dbe..eb2f06e8300 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -27,9 +27,9 @@ /* Option parameter Structures */ struct options_string { const char *option_name; - size_t offset; - unsigned int size; - const char printhex; + u32 offset : 9; + u32 size : 4; + u32 printhex : 1; }; static unsigned int picos_to_mhz(unsigned int picos) -- 2.35.1.1320.gc452695387.dirty

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[PATCH 1/3] board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop
by Pali Rohár 06 Sep '22

06 Sep '22

CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one then CPLD triggers reset of CPU in few ms. This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset. But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop. To prevent reboot loop when using SPL, calls board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB. With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 7b168fa091b1..26ea8a525228 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -91,6 +91,16 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible. + */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); } diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + console_init_f(); /* Set pmuxcr to allow both i2c1 and i2c2 */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1

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[PATCH v2 0/2] serial_mxc: fixing reception
by Johannes Schneider 06 Sep '22

06 Sep '22

while writing to a imx-serial device is probably thoroughly tested - and obviosly works for the debug-serial - using a serial driver to read data received over the serial interface does not work reliably. the patches in this series address issues found during the implementation of a custom uboot-command to query a coprocessor, connected to an imx8mm over uart4, for mainboard-identification strings (no changes since v1) Johannes Schneider (2): serial: mxc: enable the RX pipeline serial: mxc: have putc use the TXFIFO drivers/serial/serial_mxc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.25.1

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[PATCH 1/2] HSD #1507453717: arm: socfpga: stratix10: add QSPI boot feature
by Jit Loon Lim 06 Sep '22

06 Sep '22

From: "Ooi, Joyce" <joyce.ooi(a)intel.com> This patch adds the QSPI boot feature for Stratix10 Signed-off-by: Ooi, Joyce <joyce.ooi(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/socfpga_stratix10_socdk_qspi.dts | 14 ++++ configs/socfpga_stratix10_qspi_defconfig | 73 +++++++++++++++++++ include/configs/socfpga_soc64_common.h | 8 ++ 4 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga_stratix10_socdk_qspi.dts create mode 100644 configs/socfpga_stratix10_qspi_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ceaa39e4b4..c58acb480d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -436,7 +436,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ socfpga_n5x_socdk.dtb \ - socfpga_stratix10_socdk.dtb + socfpga_stratix10_socdk.dtb \ + socfpga_stratix10_socdk_qspi.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb diff --git a/arch/arm/dts/socfpga_stratix10_socdk_qspi.dts b/arch/arm/dts/socfpga_stratix10_socdk_qspi.dts new file mode 100644 index 0000000000..729b9e5b84 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk_qspi.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + */ + +#include "socfpga_stratix10_socdk.dts" +#include "socfpga_stratix10_socdk-u-boot.dtsi" + +/ { + chosen { + u-boot,boot0 = <&flash0>; + }; + +}; diff --git a/configs/socfpga_stratix10_qspi_defconfig b/configs/socfpga_stratix10_qspi_defconfig new file mode 100644 index 0000000000..ebeecf0233 --- /dev/null +++ b/configs/socfpga_stratix10_qspi_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x02080000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_qspi" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BLK=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 06198ddd82..c966d31362 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -37,6 +37,14 @@ * Environment variable */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "qspibootimageaddr=0x020B0000\0" \ + "qspifdtaddr=0x02090000\0" \ + "bootimagesize=0x01400000\0" \ + "fdtimagesize=0x00010000\0" \ + "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ + "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ + "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ -- 2.26.2

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RISCV: the machanism of available_harts may cause other harts boot failure
by Rick Chen 06 Sep '22

06 Sep '22

Hi, When I free-run a SMP system, I once hit a failure case where some harts didn't boot to the kernel shell successfully. However it can't be duplicated anymore even if I try many times. But when I set a break during debugging with GDB, it can trigger the failure case each time. I think the mechanism of available_harts does not provide a method that guarantees the success of the SMP system. Maybe we shall think of a better way for the SMP booting or just remove it ? Thread 8 hit Breakpoint 1, harts_early_init () (gdb) c Continuing. [Switching to Thread 7] Thread 7 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 6] Thread 6 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 5] Thread 5 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 4] Thread 4 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 3] Thread 3 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 2] Thread 2 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 1] Thread 1 hit Breakpoint 1, harts_early_init () (gdb) Continuing. [Switching to Thread 5] Thread 5 hit Breakpoint 3, 0x0000000001200000 in ?? () (gdb) info threads Id Target Id Frame 1 Thread 1 (hart 1) secondary_hart_loop () at arch/riscv/cpu/start.S:436 2 Thread 2 (hart 2) secondary_hart_loop () at arch/riscv/cpu/start.S:436 3 Thread 3 (hart 3) secondary_hart_loop () at arch/riscv/cpu/start.S:436 4 Thread 4 (hart 4) secondary_hart_loop () at arch/riscv/cpu/start.S:436 * 5 Thread 5 (hart 5) 0x0000000001200000 in ?? () 6 Thread 6 (hart 6) 0x000000000000b650 in ?? () 7 Thread 7 (hart 7) 0x000000000000b650 in ?? () 8 Thread 8 (hart 8) 0x0000000000005fa0 in ?? () (gdb) c Continuing. [ 0.175619] smp: Bringing up secondary CPUs ... [ 1.230474] CPU1: failed to come online [ 2.282349] CPU2: failed to come online [ 3.334394] CPU3: failed to come online [ 4.386783] CPU4: failed to come online [ 4.427829] smp: Brought up 1 node, 4 CPUs /root # cat /proc/cpuinfo processor : 0 hart : 4 isa : rv64i2p0m2p0a2p0c2p0xv5-1p1 mmu : sv39 processor : 5 hart : 5 isa : rv64i2p0m2p0a2p0c2p0xv5-1p1 mmu : sv39 processor : 6 hart : 6 isa : rv64i2p0m2p0a2p0c2p0xv5-1p1 mmu : sv39 processor : 7 hart : 7 isa : rv64i2p0m2p0a2p0c2p0xv5-1p1 mmu : sv39 /root # Thanks, Rick

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