September 2022 - U-Boot

[PATCH] arm: socfpga: switching watchdog 0 to watchdog 1
by teik.heng.chong＠intel.com 19 Sep '22

19 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Switching to watchdog 1, because there is a hardware bug found in watchdog 0, it cannot reliable trigger a reset to the CPU. More details can be referred in : Linux commit "59d94d2ed45d598211feb52566e6a806d17f8a3f" Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- arch/arm/mach-socfpga/spl_a10.c | 4 ++-- include/configs/socfpga_arria10_socdk.h | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 5d661fb995..f743c0624f 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -263,8 +263,8 @@ void board_init_f(ulong dummy) cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG - /* release watchdog 0 from reset */ - socfpga_reset_deassert_wd0(); + /* release watchdog 1 from reset */ + socfpga_reset_deassert_wd1(); /* reconfigure and enable the watchdog */ hw_watchdog_init(); diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c..cc2aeebe5b 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -36,4 +36,12 @@ /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> +/* + * L4 Watchdog + */ +#ifdef CONFIG_HW_WATCHDOG +#undef CONFIG_DW_WDT_BASE +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD1_ADDRESS +#endif + #endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */ -- 2.25.1

1 0

[PATCH] arm: socfpga: Add watchdog 1 support to A10
by teik.heng.chong＠intel.com 19 Sep '22

19 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Add watchdog 1 support to A10, ensure the same enable/disable process as watchdog 0. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- .../mach-socfpga/include/mach/base_addr_a10.h | 1 + .../include/mach/reset_manager_arria10.h | 1 + arch/arm/mach-socfpga/reset_manager_arria10.c | 21 ++++++++++++++----- arch/arm/mach-socfpga/spl_a10.c | 2 +- 4 files changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index b947cc0729..246618f4da 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -17,6 +17,7 @@ #define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 #define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 #define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 #define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 #define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 9aacf3e2c6..53efb64234 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -13,6 +13,7 @@ void socfpga_watchdog_disable(void); void socfpga_reset_deassert_noc_ddr_scheduler(void); int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_deassert_wd0(void); +void socfpga_reset_deassert_wd1(void); int socfpga_bridges_reset(void); #define RSTMGR_A10_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 13a5cf314b..25c7291246 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -61,6 +61,9 @@ void socfpga_watchdog_disable(void) /* assert reset for watchdog */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, + ALT_RSTMGR_PER1MODRST_WD1_SET_MSK); } /* Release NOC ddr scheduler from reset */ @@ -116,6 +119,13 @@ void socfpga_reset_deassert_wd0(void) ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); } +/* Release Watchdog 1 from reset through reset manager */ +void socfpga_reset_deassert_wd1(void) +{ + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, + ALT_RSTMGR_PER1MODRST_WD1_SET_MSK); +} + /* * Assert or de-assert SoCFPGA reset manager reset. */ @@ -154,15 +164,16 @@ void socfpga_per_reset(u32 reset, int set) } /* - * Assert reset on every peripheral but L4WD0. + * Assert reset on every peripheral but L4WD0 & l4WD1. * Watchdog must be kept intact to prevent glitches * and/or hangs. * For the Arria10, we disable all the peripherals except L4 watchdog0, - * L4 Timer 0, and ECC. + * L4 watchdog1, L4 Timer 0, and ECC. */ void socfpga_per_reset_all(void) { - const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | + const u32 l4wd = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | + 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD1)) | (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); unsigned mask_ecc_ocp = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | @@ -174,8 +185,8 @@ void socfpga_per_reset_all(void) ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; - /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */ - writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST); + /* disable all components except ECC_OCP, L4 Timer0, L4 WD0 & l4 WD1 */ + writel(~l4wd, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST); setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST, ~mask_ecc_ocp); diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 96bad162df..5d661fb995 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -255,7 +255,7 @@ void board_init_f(ulong dummy) socfpga_sdram_remap_zero(); socfpga_pl310_clear(); - /* Assert reset to all except L4WD0 and L4TIMER0 */ + /* Assert reset to all except L4WD0, L4WD1 and L4TIMER0 */ socfpga_per_reset_all(); socfpga_watchdog_disable(); -- 2.25.1

1 0

[PATCH] arm: socfpga: Remove confusing timer related words from watchdog reset
by teik.heng.chong＠intel.com 19 Sep '22

19 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> It's confusing to have timer related words along with watchdog reset dessert function, because the function is only release watchdog from reset, so it has no related to any timer setting. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++-- arch/arm/mach-socfpga/spl_a10.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 26faa628a0..9aacf3e2c6 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -12,7 +12,7 @@ void socfpga_watchdog_disable(void); void socfpga_reset_deassert_noc_ddr_scheduler(void); int socfpga_reset_deassert_bridges_handoff(void); -void socfpga_reset_deassert_osc1wd0(void); +void socfpga_reset_deassert_wd0(void); int socfpga_bridges_reset(void); #define RSTMGR_A10_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 27c0308011..13a5cf314b 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -109,8 +109,8 @@ int socfpga_reset_deassert_bridges_handoff(void) mask_noc, false, 1000, false); } -/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */ -void socfpga_reset_deassert_osc1wd0(void) +/* Release Watchdog 0 from reset through reset manager */ +void socfpga_reset_deassert_wd0(void) { clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index ec67a5b0eb..96bad162df 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -263,8 +263,8 @@ void board_init_f(ulong dummy) cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG - /* release osc1 watchdog timer 0 from reset */ - socfpga_reset_deassert_osc1wd0(); + /* release watchdog 0 from reset */ + socfpga_reset_deassert_wd0(); /* reconfigure and enable the watchdog */ hw_watchdog_init(); -- 2.25.1

1 0

[PATCH] ddr: socfpga: Improve A10 SDRAM ECC init function to support watchdog reset
by teik.heng.chong＠intel.com 19 Sep '22

19 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> There is a potential risk that memset on DDR taking too long than the timeout set for watchdog, hence the function is restructured so that splitting up the DDR into chunks for memset and resetting the watchdog for each chunk memory. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- drivers/ddr/altera/sdram_arria10.c | 38 ++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 4a8f8dea1c..6eb7a34bc0 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -22,6 +22,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/kernel.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; @@ -48,6 +49,8 @@ static u64 sdram_size_calc(void); #define CORE2SEQ_INT_REQ 0xF #define SEQ2CORE_INT_RESP_BIT 3 +#define PGTABLE_OFF 0x4000 + static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = (void *)SOCFPGA_SDR_ADDRESS; static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = @@ -196,19 +199,44 @@ static int sdram_is_ecc_enabled(void) /* Initialize SDRAM ECC bits to avoid false DBE */ static void sdram_init_ecc_bits(u32 size) { - icache_enable(); + u32 start, size_init, start_addr; + + start = get_timer(0); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = size; - memset(0, 0, 0x8000); - gd->arch.tlb_addr = 0x4000; + gd->arch.tlb_addr = gd->bd->bi_dram[0].start + PGTABLE_OFF; gd->arch.tlb_size = PGTABLE_SIZE; + memset((void *)gd->bd->bi_dram[0].start, 0, gd->arch.tlb_addr + + gd->arch.tlb_size + SZ_1K); + + icache_enable(); dcache_enable(); - printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20); - memset((void *)0x8000, 0, size - 0x8000); + start_addr = gd->arch.tlb_addr + gd->arch.tlb_size; + size -= (gd->arch.tlb_addr + gd->arch.tlb_size); + + printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n", size >> 20); + + + while (size > 0) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + memset((void *)start_addr, 0, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + flush_dcache_all(); + printf("DDRCAL: Scrubbing ECC RAM done.\n"); + dcache_disable(); + + printf("DDRCAL: SDRAM-ECC initialized success with %d ms\n", + (u32)get_timer(start)); } /* Function to startup the SDRAM*/ -- 2.25.1

1 0

[PATCH] arm: socfpga: A10: Enable Designware watchdog
by teik.heng.chong＠intel.com 19 Sep '22

19 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Some bootROMs enable the watchdog before jumping to SPL, so calling WATCHDOG_RESET() is required to reset watchdog timely especially in long looping. Enable Designware watchdog driver is required to support WATCHDOG_RESET(). Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- arch/arm/mach-socfpga/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index df44530e83..505d30f9e4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -64,8 +64,10 @@ config TARGET_SOCFPGA_ARRIA10 select SPL_ALTERA_SDRAM select SPL_BOARD_INIT if SPL select SPL_CACHE if SPL + select SPL_WDT if SPL select CLK select SPL_CLK if SPL + select DESIGNWARE_WATCHDOG select DM_I2C select DM_RESET select SPL_DM_RESET if SPL @@ -74,6 +76,7 @@ config TARGET_SOCFPGA_ARRIA10 select SYSCON select SPL_SYSCON if SPL select ETH_DESIGNWARE_SOCFPGA + select WDT imply FPGA_SOCFPGA imply SPL_USE_TINY_PRINTF -- 2.25.1

1 0

[PATCH] MAINTAINERS: imx: Add an entry for the serial driver
by Fabio Estevam 18 Sep '22

18 Sep '22

From: Fabio Estevam <festevam(a)denx.de> Currently, when running ./scripts/get_maintainer.pl on serial_mxc.c no i.MX maintainer is returned. Fix it by adding an entry for this driver. Reported-by: Pali Rohár <pali(a)kernel.org> Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 36a2b69fcb..83346183ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -264,6 +264,7 @@ F: arch/arm/include/asm/arch-mx*/ F: arch/arm/include/asm/arch-vf610/ F: arch/arm/include/asm/mach-imx/ F: board/freescale/*mx*/ +F: drivers/serial/serial_mxc.c ARM HISILICON M: Peter Griffin <peter.griffin(a)linaro.org> -- 2.25.1

3 2

[PATCH 1/7] ARM: imx: Enable USB ethernet on i.MX8M Plus DHCOM
by Marek Vasut 18 Sep '22

18 Sep '22

Enable both USB CDC ethernet and USB host ethernet on i.MX8M Plus DHCOM. This is useful for bringing up systems without ethernet plug, but with either USB host or gadget plug. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: uboot-imx <uboot-imx(a)nxp.com> --- configs/imx8mp_dhcom_pdk2_defconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index f3b69070698..2ea5c9a2b1b 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -86,6 +86,7 @@ CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y @@ -239,20 +240,23 @@ CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="DH electronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x0 CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT_OVERLAY=y -- 2.35.1

2 13

[PATCH V2] Kconfig: enlarge CONFIG_SYS_MALLOC_F_LEN
by Peng Fan (OSS) 18 Sep '22

18 Sep '22

From: Peng Fan <peng.fan(a)nxp.com> "alloc space exhausted" happens in very early stage, which could be seen with DEBUG_UART options enabled and leeds to an non-functional board. kontron_pitx_imx8m: CONFIG_DEBUG_UART_BASE=0x30880000 # for serial3 CONFIG_DEBUG_UART_CLOCK=24000000 imx8mqevk: CONFIG_DEBUG_UART_BASE=0x30860000 # for uart1 CONFIG_DEBUG_UART_CLOCK=24000000 It is because CONFIG_SYS_MALLOC_F_LEN is too small and still leave CONFIG_SPL_SYS_MALLOC_F_LEN as 0x2000. Reported-by: Heiko Thiery <heiko.thiery(a)gmail.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: set for all i.MX8MQ Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 991b260182e..c8c22555a94 100644 --- a/Kconfig +++ b/Kconfig @@ -299,7 +299,7 @@ config SYS_MALLOC_F_LEN default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \ ROCKCHIP_RK3399 default 0x8000 if RCAR_GEN3 - default 0x10000 if ARCH_IMX8 || (ARCH_IMX8M && !IMX8MQ) + default 0x10000 if ARCH_IMX8 || ARCH_IMX8M default 0x2000 help Before relocation, memory is very limited on many platforms. Still, @@ -325,6 +325,7 @@ config SPL_SYS_MALLOC_F_LEN depends on SYS_MALLOC_F && SPL default 0 if !SPL_FRAMEWORK default 0x2800 if RCAR_GEN3 + default 0x2000 if IMX8MQ default SYS_MALLOC_F_LEN help In SPL memory is very limited on many platforms. Still, -- 2.36.0

4 4

[PATCH] ARM: imx: dh-imx6: Increase SF erase area for u-boot update
by Marek Vasut 18 Sep '22

18 Sep '22

Erase the entire U-Boot area during U-Boot update instead of just a subset of it. This way, in case u-boot-with-spl.imx grows, the sf write won't write over non-erased part of the SPI NOR. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/dh_imx6.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 79424647f61..0f7e1c5c451 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -60,7 +60,7 @@ "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ "load mmc 0:1 ${loadaddr} /boot/u-boot-with-spl.imx && "\ - "sf probe && sf erase 0x0 0xa0000 && " \ + "sf probe && sf erase 0x0 0x100000 && " \ "sf write ${loadaddr} 0x400 ${filesize}\0" \ BOOTENV -- 2.35.1

2 1

[PATCH] ARM: imx: Enable SPL GPIO hog on i.MX8M Plus DHCOM
by Marek Vasut 18 Sep '22

18 Sep '22

Enable GPIO hog support in SPL to match the GPIO hog support in U-Boot proper. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: uboot-imx <uboot-imx(a)nxp.com> --- configs/imx8mp_dhcom_pdk2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 0315a4cfb21..e78b9a1569e 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -169,6 +169,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x20000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_INPUT is not set -- 2.35.1

3 2