September 2022 - U-Boot

[PATCH v1] wdt: nuvoton: add expire function for generic reset
by Jim Liu 24 Oct '22

24 Oct '22

Add expire_now function for generic sysreset request Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/watchdog/npcm_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 256020f5d3..e56aa0ebe1 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -75,6 +75,11 @@ static int npcm_wdt_reset(struct udevice *dev) return 0; } +static int npcm_wdt_expire_now(struct udevice *dev, ulong flags) +{ + return npcm_wdt_reset(dev); +} + static int npcm_wdt_of_to_plat(struct udevice *dev) { struct npcm_wdt_priv *priv = dev_get_priv(dev); @@ -87,6 +92,7 @@ static int npcm_wdt_of_to_plat(struct udevice *dev) } static const struct wdt_ops npcm_wdt_ops = { + .expire_now = npcm_wdt_expire_now, .start = npcm_wdt_start, .reset = npcm_wdt_reset, .stop = npcm_wdt_stop, -- 2.17.1

2 2

[PATCH 0/7] arm: dts: Create common imx8mn-u-boot
by Adam Ford 24 Oct '22

24 Oct '22

Every imx8mn board has a bunch of similar entries on their respective board-u-boot.dtsi file to make the board bootable. Instead of maintaining multiple files with duplicate code, have them all point to a new, common file. This file includes the necessary nodes that were common to nearly all boards and added spba1 to help faciliate SPL_DM_SERIAL. This also adds support for CONFIG_FSPI_CONF_HEADER which can be used to generate flash.bin files for booting from FlexSPI. Adam Ford (7): arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi arm: dts: imx8mn-beacon-kit: Consolidate with imx8mn-u-boot arm: dts: imx8mn-bsh-smm-s2: Consolidate with imx8mn-u-boot arm: dts: imx8mn-ddr4-evk: Consolidate with imx8mn-u-boot arm: dts: imx8mn-evk: Consolidate with imx8mn-u-boot arm: dts: imx8mn-var-som-symphony: Consolidate with imx8mn-u-boot arm: dts: imx8mn-venice: Consolidate with imx8mn-u-boot arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 180 +------------ .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 172 +----------- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 180 +------------ arch/arm/dts/imx8mn-evk-u-boot.dtsi | 108 -------- arch/arm/dts/imx8mn-u-boot.dtsi | 248 ++++++++++++++++++ .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 188 +------------ arch/arm/dts/imx8mn-venice-u-boot.dtsi | 188 +------------ 7 files changed, 254 insertions(+), 1010 deletions(-) create mode 100644 arch/arm/dts/imx8mn-u-boot.dtsi -- 2.34.1

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[PATCH 0/6] imx: imx6ul: kontron-sl-mx6ul: Fixes and improvements
by Frieder Schrempf 24 Oct '22

24 Oct '22

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> This series fixes some issues with the kontron-sl-mx6ul board configuration. It also syncs devicetrees with changes in the Linux kernel. Notes: * This series is based on imx/master and fixes the previously merged sync patch from Marcel [1]. * The devicetree changes this is based on are still pending in Linux (see [2]). [1] https://patchwork.ozlabs.org/project/uboot/patch/20220721132748.1052244-9-m… [2] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220815082814.… Frieder Schrempf (6): Makefile: Make flash.bin target available for all platforms imx: imx6ul: kontron-sl-mx6ul: Enable migrated Kconfig options imx: imx6ul: kontron-sl-mx6ul: Fix CONFIG_ENV_SPI_BUS imx: imx6ul: kontron-sl-mx6ul: Select correct boot and env device imx: imx6ul: kontron-sl-mx6ul: Migrate to use CONFIG_EXTRA_ENV_TEXT imx: imx6ul: kontron-sl-mx6ul: Sync devicetrees Makefile | 4 +- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6ul-kontron-bl-43.dts | 103 +++++ ...i => imx6ul-kontron-bl-common-u-boot.dtsi} | 0 ...x-s.dtsi => imx6ul-kontron-bl-common.dtsi} | 0 ...oot.dtsi => imx6ul-kontron-bl-u-boot.dtsi} | 2 +- ...tron-n631x-s.dts => imx6ul-kontron-bl.dts} | 9 +- arch/arm/dts/imx6ul-kontron-n6x1x-s.dts | 423 ------------------ ...mon.dtsi => imx6ul-kontron-sl-common.dtsi} | 15 + ...-n631x-som.dtsi => imx6ul-kontron-sl.dtsi} | 6 +- ...ot.dtsi => imx6ull-kontron-bl-u-boot.dtsi} | 2 +- arch/arm/dts/imx6ull-kontron-bl.dts | 15 + arch/arm/dts/imx6ull-kontron-n641x-s.dts | 16 - ...n641x-som.dtsi => imx6ull-kontron-sl.dtsi} | 6 +- board/kontron/sl-mx6ul/MAINTAINERS | 6 +- board/kontron/sl-mx6ul/Makefile | 2 + board/kontron/sl-mx6ul/sl-mx6ul-common.c | 24 + board/kontron/sl-mx6ul/sl-mx6ul-common.h | 11 + board/kontron/sl-mx6ul/sl-mx6ul.c | 15 + board/kontron/sl-mx6ul/sl-mx6ul.env | 4 + board/kontron/sl-mx6ul/spl.c | 39 +- configs/kontron-sl-mx6ul_defconfig | 13 +- include/configs/kontron-sl-mx6ul.h | 10 +- 23 files changed, 242 insertions(+), 487 deletions(-) create mode 100644 arch/arm/dts/imx6ul-kontron-bl-43.dts rename arch/arm/dts/{imx6ul-kontron-n6x1x-s-u-boot.dtsi => imx6ul-kontron-bl-common-u-boot.dtsi} (100%) rename arch/arm/dts/{imx6ul-kontron-n6x1x-s.dtsi => imx6ul-kontron-bl-common.dtsi} (100%) rename arch/arm/dts/{imx6ul-kontron-n631x-s-u-boot.dtsi => imx6ul-kontron-bl-u-boot.dtsi} (75%) rename arch/arm/dts/{imx6ul-kontron-n631x-s.dts => imx6ul-kontron-bl.dts} (52%) delete mode 100644 arch/arm/dts/imx6ul-kontron-n6x1x-s.dts rename arch/arm/dts/{imx6ul-kontron-n6x1x-som-common.dtsi => imx6ul-kontron-sl-common.dtsi} (90%) rename arch/arm/dts/{imx6ul-kontron-n631x-som.dtsi => imx6ul-kontron-sl.dtsi} (62%) rename arch/arm/dts/{imx6ull-kontron-n641x-s-u-boot.dtsi => imx6ull-kontron-bl-u-boot.dtsi} (75%) create mode 100644 arch/arm/dts/imx6ull-kontron-bl.dts delete mode 100644 arch/arm/dts/imx6ull-kontron-n641x-s.dts rename arch/arm/dts/{imx6ull-kontron-n641x-som.dtsi => imx6ull-kontron-sl.dtsi} (55%) create mode 100644 board/kontron/sl-mx6ul/sl-mx6ul-common.c create mode 100644 board/kontron/sl-mx6ul/sl-mx6ul-common.h create mode 100644 board/kontron/sl-mx6ul/sl-mx6ul.env -- 2.37.2

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[PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1
by Marcel Ziswiler 24 Oct '22

24 Oct '22

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> This series synchronises them imx device trees with the upstream Linux kernel (v6.0-rc1). I split it into two parts. This is part 1. It also fixes a few issues as discussed during/after the pre-mature application of my first series [1]. I am not touching kontron-sl-mx6ul as Frieder already took care of those [2]. Feedback welcome. Thanks! [1] https://patchwork.ozlabs.org/project/uboot/cover/20220721132748.1052244-1-m… [2] https://patchwork.ozlabs.org/project/uboot/cover/20220823142917.306176-1-fr… Changes in v2: - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks! - imx8ulp: Re-added s400_mu device tree node. Marcel Ziswiler (8): vf610: synchronise device tree with linux imxrt1020: fix lpuart issue in common u-boot device tree imxrt1050: synchronise device tree with linux imx8ulp: synchronise device tree with linux imx8mq: synchronise device tree with linux imx8mp: synchronise device tree with linux imx8mn: synchronise device tree with linux imx8mm: synchronise device tree with linux arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 43 ++ arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 12 +- arch/arm/dts/imx8mm-mx8menlo.dts | 4 +- arch/arm/dts/imx8mm-u-boot.dtsi | 2 +- arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +- arch/arm/dts/imx8mm-venice-gw7901.dts | 8 +- arch/arm/dts/imx8mm-venice-gw7902.dts | 10 +- arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +- arch/arm/dts/imx8mm-verdin.dtsi | 10 +- arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 2 +- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 2 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn-evk.dtsi | 45 +- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +- arch/arm/dts/imx8mn-venice-gw7902.dts | 8 +- arch/arm/dts/imx8mn-venice-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn.dtsi | 13 +- arch/arm/dts/imx8mp-dhcom-pdk2.dts | 27 +- arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 +- arch/arm/dts/imx8mp-evk.dts | 126 ++-- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48 +- arch/arm/dts/imx8mp-u-boot.dtsi | 2 +- arch/arm/dts/imx8mp-venice-gw74xx.dts | 116 ++-- arch/arm/dts/imx8mp-verdin.dtsi | 14 +- arch/arm/dts/imx8mp.dtsi | 33 +- arch/arm/dts/imx8mq-evk.dts | 43 ++ arch/arm/dts/imx8mq-u-boot.dtsi | 10 +- arch/arm/dts/imx8mq.dtsi | 15 +- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +- arch/arm/dts/imx8ulp-evk.dts | 191 +----- arch/arm/dts/imx8ulp-pinfunc.h | 4 +- arch/arm/dts/imx8ulp.dtsi | 564 +++++------------- arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 +- arch/arm/dts/imxrt1020-evk.dts | 1 - arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++++- arch/arm/dts/imxrt1050-evk.dts | 257 +------- arch/arm/dts/imxrt1050-pinfunc.h | 2 +- arch/arm/dts/imxrt1050.dtsi | 168 +++--- arch/arm/dts/vf610-pinfunc.h | 2 +- include/dt-bindings/clock/imx8mp-clock.h | 13 +- include/dt-bindings/clock/imx8ulp-clock.h | 49 +- include/dt-bindings/clock/imxrt1050-clock.h | 9 +- include/dt-bindings/interconnect/imx8mm.h | 50 ++ include/dt-bindings/interconnect/imx8mn.h | 41 ++ include/dt-bindings/power/imx8mp-power.h | 15 +- include/dt-bindings/power/imx8ulp-power.h | 26 + include/dt-bindings/reset/imx8mp-reset.h | 50 ++ include/dt-bindings/reset/imx8mq-reset.h | 61 +- include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++ 52 files changed, 1146 insertions(+), 1256 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mm.h create mode 100644 include/dt-bindings/interconnect/imx8mn.h create mode 100644 include/dt-bindings/power/imx8ulp-power.h create mode 100644 include/dt-bindings/reset/imx8mp-reset.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h -- 2.35.1

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[PATCH] cmd: sf: Handle unaligned 'update' start offset
by Marek Vasut 23 Oct '22

23 Oct '22

Currently the 'sf update' command fails in case the 'start' offset is not aligned to SPI NOR erase block size. Add the missing alignment calculation. In case the start offset is in the middle of erase block, round start address down to the nearest aligned one, compare only the updated data between what is in the SPI NOR and what is being written, copy new data at offset of the compare buffer, and write back the entire erase block. This is useful e.g. on i.MX6Q where the u-boot-with-spl.imx is at offset 0x400 in the SPI NOR, while the SPI NOR may have erase block size e.g. 0x1000 bytes. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Jan Kiszka <jan.kiszka(a)siemens.com> Cc: Pratyush Yadav <p.yadav(a)ti.com> Cc: Sean Anderson <seanga2(a)gmail.com> --- cmd/sf.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/cmd/sf.c b/cmd/sf.c index bd102f5af9d..f9b2d9a47a7 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -179,16 +179,18 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset, size_t len, const char *buf, char *cmp_buf, size_t *skipped) { char *ptr = (char *)buf; + u32 start_offset = offset % flash->sector_size; + u32 read_offset = offset - start_offset; - debug("offset=%#x, sector_size=%#x, len=%#zx\n", - offset, flash->sector_size, len); + debug("offset=%#x+%#x, sector_size=%#x, len=%#zx\n", + read_offset, start_offset, flash->sector_size, len); /* Read the entire sector so to allow for rewriting */ - if (spi_flash_read(flash, offset, flash->sector_size, cmp_buf)) + if (spi_flash_read(flash, read_offset, flash->sector_size, cmp_buf)) return "read"; /* Compare only what is meaningful (len) */ - if (memcmp(cmp_buf, buf, len) == 0) { - debug("Skip region %x size %zx: no change\n", - offset, len); + if (memcmp(cmp_buf + start_offset, buf, len) == 0) { + debug("Skip region %x+%x size %zx: no change\n", + start_offset, read_offset, len); *skipped += len; return NULL; } @@ -197,7 +199,7 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset, return "erase"; /* If it's a partial sector, copy the data into the temp-buffer */ if (len != flash->sector_size) { - memcpy(cmp_buf, buf, len); + memcpy(cmp_buf + start_offset, buf, len); ptr = cmp_buf; } /* Write one complete sector */ @@ -238,6 +240,8 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset, for (; buf < end && !err_oper; buf += todo, offset += todo) { todo = min_t(size_t, end - buf, flash->sector_size); + todo = min_t(size_t, end - buf, + flash->sector_size - (offset % flash->sector_size)); if (get_timer(last_update) > 100) { printf(" \rUpdating, %zu%% %lu B/s", 100 - (end - buf) / scale, -- 2.35.1

2 1

[PATCH] mtd: spi-nor-core: Fix index value for SCCR dwords
by tkuw584924＠gmail.com 23 Oct '22

23 Oct '22

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> Array index for SCCR 22th DWORD should be 21. Fixes: bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> --- drivers/mtd/spi/spi-nor-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e3c86e080a1d..65dc69a4be9a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2493,7 +2493,7 @@ static int spi_nor_parse_sccr(struct spi_nor *nor, for (i = 0; i < sccr_header->length; i++) table[i] = le32_to_cpu(table[i]); - if (FIELD_GET(SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE, table[22])) + if (FIELD_GET(SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE, table[21])) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; out: -- 2.25.1

2 1

[PATCH 0/4] mtd: spi-nor-core: Track flash's internal address mode in s25hx-t
by tkuw584924＠gmail.com 23 Oct '22

23 Oct '22

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> For S25hx-T support in Linux (single die package only), flash's internal address mode is not changed and it is assumed as factory default. Current implementation of u-boot forces to 4-byte address mode while some parts are 3-byte address mode by default. That will cause a problem when we use u-boot to load the Linux kernel. This series tries to avoid the problem, by porting two changes from linux [0][1] and additional rework. [0] https://patchwork.ozlabs.org/project/linux-mtd/patch/20200525091544.17270-7… [1] https://patchwork.ozlabs.org/project/linux-mtd/patch/20220725092505.446315-… Takahiro Kuwano (4): mtd: spi-nor-core: Default to addr_width of 3 for configurable widths mtd: spi-nor-core: Track flash's internal address mode mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytes mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal address mode drivers/mtd/spi/spi-nor-core.c | 42 ++++++++++++++++++++++++---------- include/linux/mtd/spi-nor.h | 5 ++++ 2 files changed, 35 insertions(+), 12 deletions(-) -- 2.25.1

2 5

[PATCH 0/3] mtd: spi-nor-core: Add support for s28hl512t, s28hl01gt, and s28hs01gt
by tkuw584924＠gmail.com 23 Oct '22

23 Oct '22

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> These devices are variants of s28hs512t(1.8V 512Mb) with different density(1Gb) and power supply voltage(3V). Datasheet: https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HS512T_S28HS01GT_S28HL2… Tested on Zynq-7000 platform with Infineon SPI controller Takahiro Kuwano (3): mtd: spi-nor-core: Rename s28hs512t prefix mtd: spi-nor-core: Rename configuration macro for S28 support mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs configs/j721s2_evm_a72_defconfig | 2 +- configs/j721s2_evm_r5_defconfig | 2 +- drivers/mtd/spi/Kconfig | 10 +++---- drivers/mtd/spi/spi-nor-core.c | 48 +++++++++++++++++--------------- drivers/mtd/spi/spi-nor-ids.c | 5 +++- 5 files changed, 36 insertions(+), 31 deletions(-) -- 2.25.1

2 4

[PATCH] configs: imx8mn_beacon_fspi: Add config for booting from QSPI
by Adam Ford 22 Oct '22

22 Oct '22

The imx8mn-beacon SOM has a QSPI part on it connected to the FlexSPI controller. Add a defconfig option which supports booting from the QSPI NOR flash instead of sd/mmc. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- This won't fully function without this series: https://patchwork.ozlabs.org/project/uboot/list/?series=312016 diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig new file mode 100644 index 0000000000..ecaefd8930 --- /dev/null +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -0,0 +1,156 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_BEACON=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x44000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" +CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="FEC" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x0 +CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FSPI_CONF_HEADER=y +CONFIG_FSPI_CONF_FILE="fspi_header.bin" -- 2.34.1

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[PATCH] fdt: change splicing offset detection
by Elijah Conners 22 Oct '22

22 Oct '22

In fdt_rw.c, -FDT_ERR_BADOFFSET is returned when either the sum of the old length and the splice point are less than the splice point, or when the sum of the old length and the splice point exceed the end of the pointer. Adding an int and a pointer may result in a pointer overflow, an undefined behavior, which means that the result of this if statement can't be recovered from. Checking if the old length exceeds the end of the pointer minus the pointer is a much safer check. Signed-off-by: Elijah Conners <business(a)elijahpepe.com> --- scripts/dtc/libfdt/fdt_rw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/dtc/libfdt/fdt_rw.c b/scripts/dtc/libfdt/fdt_rw.c index 2eb2b38703..672b74ae7a 100644 --- a/scripts/dtc/libfdt/fdt_rw.c +++ b/scripts/dtc/libfdt/fdt_rw.c @@ -58,7 +58,7 @@ static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen) char *p = splicepoint; char *end = (char *)fdt + fdt_data_size_(fdt); - if (((p + oldlen) < p) || ((p + oldlen) > end)) + if (oldlen >= (end - p)) return -FDT_ERR_BADOFFSET; if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt)) return -FDT_ERR_BADOFFSET; -- 2.29.2.windows.2

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