September 2022 - U-Boot

[PATCH v3] video: simplefb: add rotation support
by Takumi Sueda 31 Oct '22

31 Oct '22

It introduces the way to rotate the screen for boards with rotated screen. Signed-off-by: Takumi Sueda <puhitaku(a)gmail.com> --- drivers/video/simplefb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 2b0d8835e3..235ec761f7 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -43,7 +43,11 @@ static int simple_video_probe(struct udevice *dev) uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0); uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0); - uc_priv->rot = 0; + uc_priv->rot = fdtdec_get_uint(blob, node, "rot", 0); + if (uc_priv->rot > 3) { + log_debug("%s: invalid rot\n", __func__); + return log_msg_ret("rot", -EINVAL); + } format = fdt_getprop(blob, node, "format", NULL); debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format); -- 2.20.1

2 1

[PATCH v3 0/2] automatically stip btool_ from btool names
by Quentin Schulz 30 Oct '22

30 Oct '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> Commit daa2da754afe ("binman: btool: gzip: fix packer name so that binary can be found") introduced some sort of work-around to make the gzip binary found by bintool. However, this work-around would need to be applied to any btool whose name is prefixed with btool_ (usually to avoid conflict with other python modules). Instead, let's handle this specific case directly inside bintool so that the btools don't have to handle it themselves. This also reverts the now-unnecessary work-around for gzip btool. To: Simon Glass <sjg(a)chromium.org> To: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Cc: Quentin Schulz <foss+uboot(a)0leil.net> Cc: u-boot(a)lists.denx.de Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Quentin Schulz (2): binman: bintool: remove btool_ prefix from btool names Revert "binman: btool: gzip: fix packer name so that binary can be found" tools/binman/bintool.py | 2 ++ tools/binman/btool/btool_gzip.py | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) --- base-commit: 97c0a9c5708dc60d82cad721a8b882f0ce37e83d change-id: 20220930-upstream-gzip-binman-v3-91b83bf16795 Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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[PATCH v1] spi: nuvoton: add NPCM PSPI controller driver
by Jim Liu 27 Oct '22

27 Oct '22

Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/npcm_pspi.c | 226 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/spi/npcm_pspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..4e4e05f849 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -289,6 +289,11 @@ config NPCM_FIU_SPI This enables support for the Flash Interface Unit SPI controller in master mode. +config NPCM_PSPI + bool "PSPI driver for Nuvoton NPCM SoC" + help + PSPI driver for NPCM SoC + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..1b843636bc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o +obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c new file mode 100644 index 0000000000..bd9ac65411 --- /dev/null +++ b/drivers/spi/npcm_pspi.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology. + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <clk.h> +#include <asm/gpio.h> +#include <linux/iopoll.h> + +#define MAX_DIV 127 + +/* Register offsets */ +#define PSPI_DATA 0 +#define PSPI_CTL1 2 +#define PSPI_STAT 4 + +/* PSPI_CTL1 fields */ +#define PSPI_CTL1_SPIEN BIT(0) +#define PSPI_CTL1_SCM BIT(7) +#define PSPI_CTL1_SCIDL BIT(8) +#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9) +#define PSPI_CTL1_SCDV_SHIFT 9 + +/* PSPI_STAT fields */ +#define PSPI_STAT_BSY BIT(0) +#define PSPI_STAT_RBF BIT(1) + +struct npcm_pspi_priv { + void __iomem *base; + struct clk clk; + struct gpio_desc cs_gpio; + u32 max_hz; +}; + +static inline void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 0); +} + +static inline void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 1); +} + +static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val |= PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + void __iomem *base = priv->base; + const u8 *tx = dout; + u8 *rx = din; + u32 bytes = bitlen / 8; + u8 tmp; + u32 val; + int i, ret = 0; + + npcm_pspi_enable(priv); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + for (i = 0; i < bytes; i++) { + /* Making sure we can write */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + if (tx) + writeb(*tx++, base + PSPI_DATA); + else + writeb(0, base + PSPI_DATA); + + /* Wait till write completed */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + /* Wait till read buffer full */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + (val & PSPI_STAT_RBF), + 1000000); + if (ret < 0) + break; + + tmp = readb(base + PSPI_DATA); + if (rx) + *rx++ = tmp; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + npcm_pspi_disable(priv); + + return ret; +} + +static int npcm_pspi_set_speed(struct udevice *bus, uint speed) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + ulong apb_clock; + u32 divisor; + u16 val; + + apb_clock = clk_get_rate(&priv->clk); + if (!apb_clock) + return -EINVAL; + + if (speed > priv->max_hz) + speed = priv->max_hz; + + divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1); + if (divisor > MAX_DIV) + divisor = MAX_DIV; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SCDV_MASK; + val |= divisor << PSPI_CTL1_SCDV_SHIFT; + writew(val, priv->base + PSPI_CTL1); + + debug("%s: apb_clock=%lu speed=%d divisor=%u\n", + __func__, apb_clock, speed, divisor); + + return 0; +} + +static int npcm_pspi_set_mode(struct udevice *bus, uint mode) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + u16 pspi_mode, val; + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + pspi_mode = 0; + break; + case SPI_MODE_1: + pspi_mode = PSPI_CTL1_SCM; + break; + case SPI_MODE_2: + pspi_mode = PSPI_CTL1_SCIDL; + break; + case SPI_MODE_3: + pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM; + break; + default: + break; + } + + val = readw(priv->base + PSPI_CTL1); + val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM); + val |= pspi_mode; + writew(val, priv->base + PSPI_CTL1); + + return 0; +} + +static int npcm_pspi_probe(struct udevice *bus) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + int node = dev_of_offset(bus); + int ret; + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) + return ret; + + priv->base = dev_read_addr_ptr(bus); + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, + &priv->cs_gpio, GPIOD_IS_OUT); + + return 0; +} + +static const struct dm_spi_ops npcm_pspi_ops = { + .xfer = npcm_pspi_xfer, + .set_speed = npcm_pspi_set_speed, + .set_mode = npcm_pspi_set_mode, +}; + +static const struct udevice_id npcm_pspi_ids[] = { + { .compatible = "nuvoton,npcm845-pspi"}, + { .compatible = "nuvoton,npcm750-pspi"}, + { } +}; + +U_BOOT_DRIVER(npcm_pspi) = { + .name = "npcm_pspi", + .id = UCLASS_SPI, + .of_match = npcm_pspi_ids, + .ops = &npcm_pspi_ops, + .priv_auto = sizeof(struct npcm_pspi_priv), + .probe = npcm_pspi_probe, +}; -- 2.17.1

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[PATCH] drivers: mmc: Reset watchdog when accessing mmc device
by qianfanguijin＠163.com 27 Oct '22

27 Oct '22

From: qianfan Zhao <qianfanguijin(a)163.com> watchdog will reset when 'mmc read' or 'ext4load' a large file from mmc device. Reset watchdog when accessing mmc device. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- drivers/mmc/mmc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4d9871d69f..27ffdb7fa7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -24,6 +24,7 @@ #include <memalign.h> #include <linux/list.h> #include <div64.h> +#include <watchdog.h> #include "mmc_private.h" #define DEFAULT_CMD6_TIMEOUT_MS 500 @@ -297,6 +298,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) if (timeout_ms-- <= 0) break; + WATCHDOG_RESET(); udelay(1000); } @@ -500,6 +502,8 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, blocks_todo -= cur; start += cur; dst += cur * mmc->read_bl_len; + + WATCHDOG_RESET(); } while (blocks_todo > 0); return blkcnt; -- 2.25.1

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[PATCH] crypto: hash: sw: fix Kconfig dependencies
by Benjamin Bara 26 Oct '22

26 Oct '22

From: Benjamin Bara <Benjamin.Bara(a)skidata.com> Fix SHA512 config name and add missing SHA384 config. Signed-off-by: Benjamin Bara <Benjamin.Bara(a)skidata.com> --- drivers/crypto/hash/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig index bf9540eca6..aa355c44be 100644 --- a/drivers/crypto/hash/Kconfig +++ b/drivers/crypto/hash/Kconfig @@ -10,7 +10,8 @@ config HASH_SOFTWARE depends on MD5 depends on SHA1 depends on SHA256 - depends on SHA512_ALGO + depends on SHA384 + depends on SHA512 help Enable driver for hashing operations in software. Currently it support multiple hash algorithm including CRC/MD5/SHA. -- 2.34.1

2 1

[PATCH 0/3] Clarify standalone application support
by Paul Barker 26 Oct '22

26 Oct '22

While looking into the support for u-boot standalone applications I noticed that there was some mis-alignment between the license exception and the files which needed to be included to get a functioning application. I also noticed that the set of SPI access functions defined in the jump table was missing a key function and did not match the set of prototypes defined in the exports header. These patches should rectify the issues I found. Paul Barker (3): Licenses: Clarify exceptions for standalone apps examples: hello_world: Drop inclusion of common header exports: Fix export of SPI access functions Licenses/Exceptions | 12 ++++++++---- examples/standalone/hello_world.c | 1 - include/_exports.h | 4 ++++ include/exports.h | 15 ++++++++++++++- 4 files changed, 26 insertions(+), 6 deletions(-) -- 2.25.1

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[u-boot][PATCH] spl: spl_legacy: Fix NAND boot on OMAP3 BeagleBoard
by Roger Quadros 26 Oct '22

26 Oct '22

OMAP3 BeagleBoard NAND boot hangs when spl_load_legacy_img() tries to read the header into 'struct hdr' which is allocated on the stack. As the header has already been read once before by spl_nand.c, we can avoid the extra header read here by simply passing around the pointer to the header. This fixes NAND boot on OMAP3 BeagleBoard. Signed-off-by: Roger Quadros <rogerq(a)kernel.org> --- common/spl/spl_legacy.c | 19 ++++++++----------- common/spl/spl_nand.c | 2 +- common/spl/spl_nor.c | 6 +++++- include/spl.h | 7 +++++-- 4 files changed, 19 insertions(+), 15 deletions(-) diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index ae8731c782..2e9226c990 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -77,32 +77,29 @@ static inline int spl_image_get_comp(const struct image_header *hdr) int spl_load_legacy_img(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, - struct spl_load_info *load, ulong header) + struct spl_load_info *load, ulong offset, + struct image_header *hdr) { __maybe_unused SizeT lzma_len; __maybe_unused void *src; - struct image_header hdr; ulong dataptr; int ret; - /* Read header into local struct */ - load->read(load, header, sizeof(hdr), &hdr); - /* * If the payload is compressed, the decompressed data should be * directly write to its load address. */ - if (spl_image_get_comp(&hdr) != IH_COMP_NONE) + if (spl_image_get_comp(hdr) != IH_COMP_NONE) spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; - ret = spl_parse_image_header(spl_image, bootdev, &hdr); + ret = spl_parse_image_header(spl_image, bootdev, hdr); if (ret) return ret; /* Read image */ - switch (spl_image_get_comp(&hdr)) { + switch (spl_image_get_comp(hdr)) { case IH_COMP_NONE: - dataptr = header; + dataptr = offset; /* * Image header will be skipped only if SPL_COPY_PAYLOAD_ONLY @@ -119,7 +116,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, lzma_len = LZMA_LEN; /* dataptr points to compressed payload */ - dataptr = header + sizeof(hdr); + dataptr = offset + sizeof(hdr); debug("LZMA: Decompressing %08lx to %08lx\n", dataptr, spl_image->load_addr); @@ -143,7 +140,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, default: debug("Compression method %s is not supported\n", - genimg_get_comp_short_name(image_get_comp(&hdr))); + genimg_get_comp_short_name(image_get_comp(hdr))); return -EINVAL; } diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 7b7579a2df..5eb67b5468 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -119,7 +119,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.bl_len = 1; load.read = spl_nand_legacy_read; - return spl_load_legacy_img(spl_image, bootdev, &load, offset); + return spl_load_legacy_img(spl_image, bootdev, &load, offset, header); } else { err = spl_parse_image_header(spl_image, bootdev, header); if (err) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 7986e930d2..f00a5c395b 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -111,10 +111,14 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, /* Legacy image handling */ if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) { + struct image_header hdr; + load.bl_len = 1; load.read = spl_nor_load_read; + spl_nor_load_read(&load, spl_nor_get_uboot_base(), sizeof(hdr), &hdr); return spl_load_legacy_img(spl_image, bootdev, &load, - spl_nor_get_uboot_base()); + spl_nor_get_uboot_base(), + &hdr); } return 0; diff --git a/include/spl.h b/include/spl.h index aac6648f94..7fa5e51c39 100644 --- a/include/spl.h +++ b/include/spl.h @@ -353,7 +353,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, * spl_load_legacy_img() - Loads a legacy image from a device. * @spl_image: Image description to set up * @load: Structure containing the information required to load data. - * @header: Pointer to image header (including appended image) + * @offset: Pointer to image + * @hdr: Pointer to image header * * Reads an legacy image from the device. Loads u-boot image to * specified load address. @@ -361,7 +362,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, */ int spl_load_legacy_img(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, - struct spl_load_info *load, ulong header); + struct spl_load_info *load, ulong offset, + struct image_header *hdr); + /** * spl_load_imx_container() - Loads a imx container image from a device. -- 2.17.1

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[PATCH v3] imx: imx8qm: cgtqmx8: switch to binman
by Oliver Graute 25 Oct '22

25 Oct '22

Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> Reviewed-by: Fabio Estevam <festevam(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes for v3 -added Reviewed-by -rebased on master arch/arm/dts/imx8qm-cgtqmx8.dts | 1 + arch/arm/mach-imx/imx8/Kconfig | 1 + board/congatec/cgtqmx8/imximage.cfg | 4 ++-- configs/cgtqmx8_defconfig | 2 +- doc/board/congatec/cgtqmx8.rst | 3 +-- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts index 555c357f6f..919d00644f 100644 --- a/arch/arm/dts/imx8qm-cgtqmx8.dts +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -12,6 +12,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Congatec QMX8 Qseven series"; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4414cbc213..3094524460 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -74,6 +74,7 @@ config TARGET_IMX8QM_MEK config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg index 5ecde0c530..43035088e3 100644 --- a/board/congatec/cgtqmx8/imximage.cfg +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -4,8 +4,8 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 2cf882f826..fb334bc4a4 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst index bccdef2f16..16711a844d 100644 --- a/doc/board/congatec/cgtqmx8.rst +++ b/doc/board/congatec/cgtqmx8.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make cgtqmx8_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- -- 2.17.1

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[PATCH 016/347] FogBugz #516535: Fix QSPI write issues
by Jit Loon Lim 25 Oct '22

25 Oct '22

From: Chee Hong Ang <chee.hong.ang(a)intel.com> QSPI driver perform chip select on every flash read/write access. The driver need to disable/enable the QSPI controller while performing chip select. This may cause some data lost especially the QSPI controller is configured to run at slower speed as it may take longer time to access the flash device. This patch prevent the driver from disable/enable the QSPI controller too soon and inadvertently halting any ongoing flash read/write access by ensuring the QSPI controller is always in idle mode after each read/write access. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- drivers/spi/cadence_qspi_apb.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f..5e03495f45 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); - /* Check indirect done status */ - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); - if (ret) { - printf("Indirect read clear completion error (%i)\n", ret); - goto failrd; - } + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; return 0; @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, if (bounce_buf) free(bounce_buf); + + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failwr: -- 2.25.1

3 2

[PATCH] mmc: Fix static checker warnings
by Venkatesh Yadav Abbarapu 25 Oct '22

25 Oct '22

Correct pointer dereferencing check to be more consistent. Eliminate the below smatch warning: drivers/mmc/mmc.c:3118 mmc_init_device() warn: variable dereferenced before check 'm' (see line 3116) Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mmc/mmc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 0b7c0be8cb..210703ea46 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3113,10 +3113,12 @@ int mmc_init_device(int num) } m = mmc_get_mmc_dev(dev); - m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */ - if (!m) return 0; + + /* Initialising user set speed mode */ + m->user_speed_mode = MMC_MODES_END; + if (m->preinit) mmc_start_init(m); -- 2.17.1

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