August 2022 - U-Boot

[PATCH] power: pmic: rk8xx: Remove some ifdefs
by Michal Suchanek 04 Aug '22

04 Aug '22

After adding the poweroff support there are some incorrectly nested ifdefs. Move the poweroff code outside of ifdef and convert it to if. Fixes: ad607512f5 ("power: pmic: rk8xx: Support sysreset shutdown method") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/power/pmic/rk8xx.c | 41 +++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 25ef621f8d..a239a18674 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -129,37 +129,34 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len) return 0; } -#if CONFIG_IS_ENABLED(PMIC_CHILDREN) static int rk8xx_bind(struct udevice *dev) { - ofnode regulators_node; - int children, ret; - - regulators_node = dev_read_subnode(dev, "regulators"); - if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!\n", __func__, - dev->name); - return -ENXIO; + if (CONFIG_IS_ENABLED(SYSRESET)) { + device_bind_driver(dev, "rk8xx_sysreset", + "rk8xx_sysreset", NULL); } - debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + if (CONFIG_IS_ENABLED(PMIC_CHILDREN)) { + ofnode regulators_node; + int children; - if (CONFIG_IS_ENABLED(SYSRESET)) { - ret = device_bind_driver_to_node(dev, "rk8xx_sysreset", - "rk8xx_sysreset", - dev_ofnode(dev), NULL); - if (ret) - return ret; - } + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); - children = pmic_bind_children(dev, regulators_node, pmic_children_info); - if (!children) - debug("%s: %s - no child found\n", __func__, dev->name); + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + } /* Always return success for this device */ return 0; } -#endif static int rk8xx_probe(struct udevice *dev) { @@ -269,9 +266,7 @@ U_BOOT_DRIVER(rockchip_rk805) = { .name = "rockchip_rk805", .id = UCLASS_PMIC, .of_match = rk8xx_ids, -#if CONFIG_IS_ENABLED(PMIC_CHILDREN) .bind = rk8xx_bind, -#endif .priv_auto = sizeof(struct rk8xx_priv), .probe = rk8xx_probe, .ops = &rk8xx_ops, -- 2.37.1

1 0

[PATCH v2] gpio: aspeed: port Linux dt-bindings header file
by Dhananjay Phadke 04 Aug '22

04 Aug '22

Ported as is, makes it easier to add readable GPIO definitions in DTS files. Signed-off-by: Dhananjay Phadke <dphadke(a)linux.microsoft.com> --- include/dt-bindings/gpio/aspeed-gpio.h | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h new file mode 100644 index 0000000000..adab2f56c2 --- /dev/null +++ b/include/dt-bindings/gpio/aspeed-gpio.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for binding aspeed,*-gpio. + * + * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H +#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define ASPEED_GPIO_PORT_A 0 +#define ASPEED_GPIO_PORT_B 1 +#define ASPEED_GPIO_PORT_C 2 +#define ASPEED_GPIO_PORT_D 3 +#define ASPEED_GPIO_PORT_E 4 +#define ASPEED_GPIO_PORT_F 5 +#define ASPEED_GPIO_PORT_G 6 +#define ASPEED_GPIO_PORT_H 7 +#define ASPEED_GPIO_PORT_I 8 +#define ASPEED_GPIO_PORT_J 9 +#define ASPEED_GPIO_PORT_K 10 +#define ASPEED_GPIO_PORT_L 11 +#define ASPEED_GPIO_PORT_M 12 +#define ASPEED_GPIO_PORT_N 13 +#define ASPEED_GPIO_PORT_O 14 +#define ASPEED_GPIO_PORT_P 15 +#define ASPEED_GPIO_PORT_Q 16 +#define ASPEED_GPIO_PORT_R 17 +#define ASPEED_GPIO_PORT_S 18 +#define ASPEED_GPIO_PORT_T 19 +#define ASPEED_GPIO_PORT_U 20 +#define ASPEED_GPIO_PORT_V 21 +#define ASPEED_GPIO_PORT_W 22 +#define ASPEED_GPIO_PORT_X 23 +#define ASPEED_GPIO_PORT_Y 24 +#define ASPEED_GPIO_PORT_Z 25 +#define ASPEED_GPIO_PORT_AA 26 +#define ASPEED_GPIO_PORT_AB 27 +#define ASPEED_GPIO_PORT_AC 28 + +#define ASPEED_GPIO(port, offset) \ + ((ASPEED_GPIO_PORT_##port * 8) + (offset)) + +#endif -- 2.25.1

3 3

[PATCH 1/2] ARM: cache: Allow SPL to build cache-pl310.c
by Philip Oberfichtner 04 Aug '22

04 Aug '22

Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds. After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build. [1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable() Signed-off-by: Philip Oberfichtner <pro(a)denx.de> --- arch/arm/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..ac1d4245bb 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o @@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) -- 2.37.1

2 5

[PATCH v3] Provide more details of exactly how configuration signatures are calculated
by Martin Bonner 04 Aug '22

04 Aug '22

The only changes from [PATCH v2] are 1. It is (I think) a valid patch file 2. It has come from my corporate email address (which surprisingly forces less mangling than gmail). 3. I have extended the commit message slightly Apologies for the irrelevant email footer - it is automatically added by corporate IT. Please apply with: git am --scissors file.eml -- >8 -- Describe exactly which bytes are hashed and in what order so that external tools can calculate a valid signature. Signed-off-by: Martin Bonner <martingreybeard(a)gmail.com> --- doc/uImage.FIT/signature.txt | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index 61a72db3c7..c71280b63b 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -382,6 +382,32 @@ verified later even if the FIT has been signed with other keys in the meantime. +Details +------- +The signature node contains a property ('hashed-nodes') which lists all the +nodes that the signature was made over. The image is walked in order and each +tag processed as follows: +- DTB_BEGIN_NODE: The tag and the following name are included in the signature + if the node or its parent are present in 'hashed-nodes' +- DTB_END_NODE: The tag is included in the signature if the node or its parent + are present in 'hashed-nodes' +- DTB_PROPERTY: The tag, the length word, the offset in the string table, and + the data are all included if the current node is present in 'hashed-nodes' + and the property name is not 'data'. +- DTB_END: The tag is always included in the signature. +- DTB_NOP: The tag is included in the signature if the current node is present + in 'hashed-nodes' + +In addition, the signature contains a property 'hashed-strings' which contains +the offset and length in the string table of the strings that are to be +included in the signature (this is done last). + +IMPORTANT: To verify the signature outside u-boot, it is vital to not only +calculate the hash of the image and verify the signature with that, but also to +calculate the hashes of the kernel, fdt, and ramdisk images and check those +match the hash values in the corresponding 'hash*' subnodes. + + Verification ------------ FITs are verified when loaded. After the configuration is selected a list -- Martin Bonner martin.bonner(a)entrust.com Any email and files/attachments transmitted with it are confidential and are intended solely for the use of the individual or entity to whom they are addressed. If this message has been sent to you in error, you must not copy, distribute or disclose of the information it contains. Please notify Entrust immediately and delete the message from your system.

2 3

[PATCH] arm: bcmbca: add bcm63138 SoC support
by William Zhang 04 Aug '22

04 Aug '22

BCM63138 is an ARM A9 based DSL Broadband SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory, peripheral timer and Broadcom uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are stripped down version of linux copies with mininum blocks needed by u-boot. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there. This patch applies on top of the my previous patch [1] and depends on the timer support from patch [2]. [1] https://lists.denx.de/pipermail/u-boot/2022-August/490597.html [2] https://lists.denx.de/pipermail/u-boot/2022-August/490570.html Signed-off-by: William Zhang <william.zhang(a)broadcom.com> --- MAINTAINERS | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/bcm63138.dtsi | 102 +++++++++++++++++++++++++ arch/arm/dts/bcm963138.dts | 30 ++++++++ arch/arm/mach-bcmbca/Kconfig | 9 +++ arch/arm/mach-bcmbca/Makefile | 1 + arch/arm/mach-bcmbca/bcm63138/Kconfig | 17 +++++ arch/arm/mach-bcmbca/bcm63138/Makefile | 5 ++ board/broadcom/bcmbca/Kconfig | 7 ++ configs/bcm963138_defconfig | 22 ++++++ include/configs/bcm963138.h | 11 +++ 11 files changed, 207 insertions(+) create mode 100644 arch/arm/dts/bcm63138.dtsi create mode 100644 arch/arm/dts/bcm963138.dts create mode 100644 arch/arm/mach-bcmbca/bcm63138/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm63138/Makefile create mode 100644 configs/bcm963138_defconfig create mode 100644 include/configs/bcm963138.h diff --git a/MAINTAINERS b/MAINTAINERS index 8c3a7d77f17d..2a27d15705cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -219,6 +219,7 @@ F: board/broadcom/bcmbca/ F: drivers/timer/bcmbca-timer.c N: bcmbca N: bcm[9]?47622 +N: bcm[9]?63138 N: bcm[9]?63148 N: bcm[9]?63178 N: bcm[9]?6756 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8d136bd129b..f4fa6f517744 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1165,6 +1165,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb dtb-$(CONFIG_BCM47622) += \ bcm947622.dtb +dtb-$(CONFIG_BCM63138) += \ + bcm963138.dtb dtb-$(CONFIG_BCM63148) += \ bcm963148.dtb dtb-$(CONFIG_BCM63178) += \ diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi new file mode 100644 index 000000000000..0665f24e8308 --- /dev/null +++ b/arch/arm/dts/bcm63138.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom BCM63138 DSL SoCs Device Tree + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63138", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + enable-method = "brcm,bcm63138"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <1>; + enable-method = "brcm,bcm63138"; + }; + }; + + clocks { + /* UBUS peripheral clock */ + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x784000>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller@1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <1024>; + cache-line-size = <32>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + scu: scu@1e000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000 0x100>; + }; + + gic: interrupt-controller@1f000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1f000 0x1000 + 0x1e100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + }; + + /* Legacy UBUS base */ + bus@fffe8000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + timer0: timer@80 { + compatible = "brcm,bcm-timers"; + reg = <0x80 0x28>; + clocks = <&periph_clk>; + }; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm963138.dts b/arch/arm/dts/bcm963138.dts new file mode 100644 index 000000000000..6158a8733554 --- /dev/null +++ b/arch/arm/dts/bcm963138.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + model = "Broadcom BCM963138 Reference Board"; + compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 9a29c4186bf0..c33211266a9e 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -12,6 +12,14 @@ config BCM47622 select DM_SERIAL select PL01X_SERIAL +config BCM63138 + bool "Support for Broadcom 63138 Family" + select TIMER + select BCMBCA_TIMER + select CPU_V7A + select DM_SERIAL + select BCM6345_SERIAL + config BCM63148 bool "Support for Broadcom 63148 Family" select SYS_ARCH_TIMER @@ -48,6 +56,7 @@ config BCM6878 select PL01X_SERIAL source "arch/arm/mach-bcmbca/bcm47622/Kconfig" +source "arch/arm/mach-bcmbca/bcm63138/Kconfig" source "arch/arm/mach-bcmbca/bcm63148/Kconfig" source "arch/arm/mach-bcmbca/bcm63178/Kconfig" source "arch/arm/mach-bcmbca/bcm6756/Kconfig" diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile index 8a22f9ad975d..d917615c1669 100644 --- a/arch/arm/mach-bcmbca/Makefile +++ b/arch/arm/mach-bcmbca/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_BCM47622) += bcm47622/ +obj-$(CONFIG_BCM63138) += bcm63138/ obj-$(CONFIG_BCM63148) += bcm63148/ obj-$(CONFIG_BCM63178) += bcm63178/ obj-$(CONFIG_BCM6756) += bcm6756/ diff --git a/arch/arm/mach-bcmbca/bcm63138/Kconfig b/arch/arm/mach-bcmbca/bcm63138/Kconfig new file mode 100644 index 000000000000..a34888d231d3 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63138/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM63138 + +config TARGET_BCM963138 + bool "Broadcom 63138 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm63138" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm63138/Makefile b/arch/arm/mach-bcmbca/bcm63138/Makefile new file mode 100644 index 000000000000..beb979af7520 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63138/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig index d070ebab707e..aefd7372d883 100644 --- a/board/broadcom/bcmbca/Kconfig +++ b/board/broadcom/bcmbca/Kconfig @@ -16,6 +16,13 @@ config SYS_CONFIG_NAME endif +if TARGET_BCM963138 + +config SYS_CONFIG_NAME + default "bcm963138" + +endif + if TARGET_BCM963148 config SYS_CONFIG_NAME diff --git a/configs/bcm963138_defconfig b/configs/bcm963138_defconfig new file mode 100644 index 000000000000..5aec7b896270 --- /dev/null +++ b/configs/bcm963138_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCMBCA=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BCM63138=y +CONFIG_TARGET_BCM963138=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="bcm963138" +CONFIG_IDENT_STRING=" Broadcom BCM63138" +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_CLK=y diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h new file mode 100644 index 000000000000..149a9ba68e8a --- /dev/null +++ b/include/configs/bcm963138.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#ifndef __BCM963138_H +#define __BCM963138_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#endif -- 2.37.1

2 1

[PATCH] binman: Example for csf signing
by Simon Glass 04 Aug '22

04 Aug '22

This is a starting point for running a csf tool to sign some sections of the image and add the signature in. It is missing the test in ftest.py Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/arm/dts/imx8mm-u-boot.dtsi | 96 +++++++++++++++++++++----------- tools/binman/btool/csf.py | 87 +++++++++++++++++++++++++++++ tools/binman/etype/imx8mm_csf.py | 81 +++++++++++++++++++++++++++ 3 files changed, 230 insertions(+), 34 deletions(-) create mode 100644 tools/binman/btool/csf.py create mode 100644 tools/binman/etype/imx8mm_csf.py diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index f792b421e89..8188d4b8db2 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -28,54 +28,82 @@ }; &binman { - u-boot-spl-ddr { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; + secure-boot { + filename = "secure-boot.bin"; + type = "section"; + /* Image Vector Table - not sure what goes in here */ + vector_table: vector-table { + type = "fill"; + size = <0x20>; }; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; + /* Something in here? Fixed size? */ + boot_data: boot-data { + type = "fill"; + size = <0x20>; }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + /* Starts at 0x40 - *entry */ + ddr: u-boot-spl-ddr { + type = "section"; + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; }; - }; - spl { - filename = "spl.bin"; + spl: spl { + type = "section"; + filename = "spl.bin"; + + /* need padding after this entry */ + align-end = <0x10000>; - mkimage { - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; - blob { - filename = "u-boot-spl-ddr.bin"; + blob { + filename = "u-boot-spl-ddr.bin"; + }; }; }; + + imx8mm-csf { + content = <&vector_table &boot_data &ddr &spl>; + align-end = <0x1000>; /* padding? */ + }; }; + itb { filename = "u-boot.itb"; diff --git a/tools/binman/btool/csf.py b/tools/binman/btool/csf.py new file mode 100644 index 00000000000..fc86d1021af --- /dev/null +++ b/tools/binman/btool/csf.py @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2022 Google LLC +# +"""Bintool implementation for csf + +comments here +see 'csv' for what is needed +""" + +from binman import bintool + +class Bintoolcsf(bintool.Bintool): + """Handles the 'csf' tool + + docs here + """ + def __init__(self, name): + super().__init__(name, 'Chromium OS firmware utility') + + def gbb_create(self, fname, sizes): + """Create a new Google Binary Block + + Args: + fname (str): Filename to write to + sizes (list of int): Sizes of each regions: + hwid_size, rootkey_size, bmpfv_size, recoverykey_size + + Returns: + str: Tool output + """ + args = [ + 'gbb_utility', + '-c', + ','.join(['%#x' % size for size in sizes]), + fname + ] + return self.run_cmd(*args) + + def sign_firmware(self, outfile, firmware,): + """Sign firmware to create a csf file + + Args: + outfile (str): Filename to write the csf to + firmware (str): Filename of firmware binary to sign + + Returns: + str: Tool output + """ + # run the command-line tool and get the output + args = [ + 'csf', + '--outfile', outfile, + '--firmware', firmware, + ] + return self.run_cmd(*args) + + def fetch(self, method): + """Fetch handler for csv + + This installs csv using a binary download. + + Args: + method (FETCH_...): Method to use + + Returns: + True if the file was fetched, None if a method other than FETCH_BIN + was requested + + Raises: + Valuerror: Fetching could not be completed + """ + if method != bintool.FETCH_BIN: + return None + fname, tmpdir = self.fetch_from_drive( + 'something here') + return fname, tmpdir + + def version(self): + """Version handler for csv + + Returns: + str: Version string for csv + """ + out = self.run_cmd('version').strip() + if not out: + return super().version() + return out diff --git a/tools/binman/etype/imx8mm_csf.py b/tools/binman/etype/imx8mm_csf.py new file mode 100644 index 00000000000..7c005ed1523 --- /dev/null +++ b/tools/binman/etype/imx8mm_csf.py @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2022 Google LLC +# Test code only, for Marek Vasut +# + +# Support for iMX8mm signing + +from collections import OrderedDict +import os + +from binman.entry import EntryArg +from binman.etype.collection import Entry_collection + +from dtoc import fdt_util +from patman import tools + +class Entry_imx8mm_csf(Entry_collection): + """An entry which contains ... + + Properties / Entry arguments: + - content: List of phandles to entries to sign + - other properties here + + Output files: + - input.<unique_name> - input file passed to csf + - csf.<unique_name> - output file generated by csf_util + + blurb here about what this does + """ + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.csf = None + #(self.arg1, self.arg2) = self.GetEntryArgsOrProps([ + #EntryArg('keydir', str), + #EntryArg('keyblock', str)) + + def GetCsf(self, required): + """Get the contents of this entry + + Args: + required: True if the data must be present, False if it is OK to + return None + + Returns: + bytes content of the entry, which is the signed vblock for the + provided data + """ + # Join up the data files to be signed + input_data = self.GetContents(required) + if input_data is None: + return None + + uniq = self.GetUniqueName() + output_fname = tools.get_output_filename('csf.%s' % uniq) + input_fname = tools.get_output_filename('input.%s' % uniq) + tools.write_file(input_fname, input_data) + stdout = self.csf.sign_firmware( + outfile=output_fname, + firmware=input_fname) + if stdout is not None: + data = tools.read_file(output_fname) + else: + # Bintool is missing; just use 4KB of zero data + self.record_missing_bintool(self.csf) + data = tools.get_bytes(0, 4096) + return data + + def ObtainContents(self): + data = self.GetCsf(False) + if data is None: + return False + self.SetContents(data) + return True + + def ProcessContents(self): + # The blob may have changed due to WriteSymbols() + data = self.GetCsf(True) + return self.ProcessContentsUpdate(data) + + def AddBintools(self, btools): + self.csf = self.AddBintool(btools, 'csf') -- 2.37.1.455.g008518b4e5-goog

1 0

[PATCH] gpio: aspeed: port Linux dt-bindings header file
by Dhananjay Phadke 04 Aug '22

04 Aug '22

Ported as is, makes it easier to add readable GPIO definitions in DTS files. Signed-off-by: Dhananjay Phadke <dphadke(a)linux.microsoft.com> --- include/dt-bindings/gpio/aspeed-gpio.h | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h new file mode 100644 index 0000000000..56fc4889b2 --- /dev/null +++ b/include/dt-bindings/gpio/aspeed-gpio.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for binding aspeed,*-gpio. + * + * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H +#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define ASPEED_GPIO_PORT_A 0 +#define ASPEED_GPIO_PORT_B 1 +#define ASPEED_GPIO_PORT_C 2 +#define ASPEED_GPIO_PORT_D 3 +#define ASPEED_GPIO_PORT_E 4 +#define ASPEED_GPIO_PORT_F 5 +#define ASPEED_GPIO_PORT_G 6 +#define ASPEED_GPIO_PORT_H 7 +#define ASPEED_GPIO_PORT_I 8 +#define ASPEED_GPIO_PORT_J 9 +#define ASPEED_GPIO_PORT_K 10 +#define ASPEED_GPIO_PORT_L 11 +#define ASPEED_GPIO_PORT_M 12 +#define ASPEED_GPIO_PORT_N 13 +#define ASPEED_GPIO_PORT_O 14 +#define ASPEED_GPIO_PORT_P 15 +#define ASPEED_GPIO_PORT_Q 16 +#define ASPEED_GPIO_PORT_R 17 +#define ASPEED_GPIO_PORT_S 18 +#define ASPEED_GPIO_PORT_T 19 +#define ASPEED_GPIO_PORT_U 20 +#define ASPEED_GPIO_PORT_V 21 +#define ASPEED_GPIO_PORT_W 22 +#define ASPEED_GPIO_PORT_X 23 +#define ASPEED_GPIO_PORT_Y 24 +#define ASPEED_GPIO_PORT_Z 25 +#define ASPEED_GPIO_PORT_AA 26 +#define ASPEED_GPIO_PORT_AB 27 +#define ASPEED_GPIO_PORT_AC 28 + +#define ASPEED_GPIO(port, offset) \ + ((ASPEED_GPIO_PORT_##port * 8) + offset) + +#endif -- 2.25.1

3 4

GPIO and PINCTRL drivers question
by Oleh Kravchenko 03 Aug '22

03 Aug '22

Hi all, I'm looking for advice on properly implementing GPIO and PINCTRL drivers. My SoC provides the possibility to enable a pull-up/down resistor for specific GPIO. And drive strength for GPIO can have four possible states. The question is, where should I implement this functionality? I'm confused by dt-bindings/gpio/gpio.h because it has a few macros - GPIO_PULL_UP - GPIO_PULL_DOWN Should I keep everything in the pinctrl driver? Or should I implement pull-up/down in GPIO driver to support these macros and Drive Strength in pinctrl driver? -- Best regards, Oleh Kravchenko

2 1

[PATCH 1/1] doc: man-page for gpio command
by Heinrich Schuchardt 03 Aug '22

03 Aug '22

Provide a man-page for the gpio command. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- doc/usage/cmd/gpio.rst | 90 ++++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 2 files changed, 91 insertions(+) create mode 100644 doc/usage/cmd/gpio.rst diff --git a/doc/usage/cmd/gpio.rst b/doc/usage/cmd/gpio.rst new file mode 100644 index 0000000000..f6a5668388 --- /dev/null +++ b/doc/usage/cmd/gpio.rst @@ -0,0 +1,90 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +gpio command +============ + +Synopsis +-------- + +:: + + gpio <input|set|clear|toggle> <pin> + gpio read <name> <pin> + gpio status [-a] [<bank>|<pin>] + +The gpio command is used to access General Purpose Inputs/Outputs. + +gpio input +---------- + +Switch the GPIO *pin* to input mode. + +gpio set +-------- + +Switch the GPIO *pin* to output mode and set the signal to 1. + +gpio clear +---------- + +Switch the GPIO *pin* to output mode and set the signal to 0. + +gpio toggle +----------- + +Switch the GPIO *pin* to output mode and reverse the signal state. + +gpio read +--------- + +Read the signal state of the GPIO *pin* and save it in environment variable +*name*. + +gpio status +----------- + +Display the status of one or multiple GPIOs. By default only claimed GPIOs +are displayed. + +-a + Display GPIOs irrespective of being claimed. + +bank + Name of a bank of GPIOs to be displayed. + +pin + Name of a single GPIO to be displayed or manipulated. + +Examples +-------- + +Switch the status of a GPIO:: + + => gpio set a5 + gpio: pin a5 (gpio 133) value is 1 + => gpio clear a5 + gpio: pin a5 (gpio 133) value is 0 + => gpio toggle a5 + gpio: pin a5 (gpio 133) value is 1 + => gpio read myvar a5 + gpio: pin a5 (gpio 133) value is 1 + => echo $myvar + 1 + => gpio toggle a5 + gpio: pin a5 (gpio 133) value is 0 + => gpio read myvar a5 + gpio: pin a5 (gpio 133) value is 0 + => echo $myvar + 0 + +Configuration +------------- + +The *gpio* command is only available if CONFIG_CMD_GPIO=y. +The *gpio read* command is only available if CONFIG_CMD_GPIO_READ=y. + +Return value +------------ + +If the command succeds the return value $? is set to 0. If an error occurs, the +return value $? is set to 1. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 16a3db5c00..9ddc7b6cdd 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -45,6 +45,7 @@ Shell commands cmd/fatload cmd/fdt cmd/for + cmd/gpio cmd/load cmd/loadm cmd/loady -- 2.36.1

4 6

imx8mn eMMC boot partition
by Heiko Thiery 03 Aug '22

03 Aug '22

Hi, Does anyone have an idea where to find the definition of the offset used when booting from eMMCs boot partition? I tried to write the flash.bin image to offset 32k (page 0x40) into the boot partition of the eMMC and seledted the bootpartition with "mmc partconfig 2 0 1 0". The board did not start. After writing the flash.bin to offset 0 the board starts. When writing to microSD the offset 32k is ok. I' using an NXP imx8mn evk board. -- Heiko

2 4