July 2022 - U-Boot

[PATCH v8 0/4] Add octal DTR support for Macronix flash
by JaimeLiao 15 Jul '22

15 Jul '22

This series add support for Macronix octal DTR flash, add flag for Softreset with "INVERT" command extension type on boot and follow linux kernel to enable 4byte opcode when possible. v8: Correct spi nor flash information in IDs table. v7: Correct title and description of patchworks. Correct description for spi_nor_macronix_octal_dtr_enable. Add SFDP informations for flashes in commit log. v6: Parcing SCCR 22nd dword for checking Octal DTR mode support v5: Replace SPI_FLASH_MACRONIX_OCTAL with SPI_FLASH_MACRONIX. Remove patch of set_4byte opcode. v4: Add flag SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT to seperate command extension types. Replace ifdef with CONFIG_IS_ENABLED and modify uncorrect descriptions. v3: Add flag SPI_NOR_CMD_EXT_INVERT to seperate command extension types. replace CONFIG_SPI_FLASH_MACRONIX with SPI_FLASH_MACRONIX_OCTAL for spi_nor_macronix_octal_dtr_enable function. v2: add ret checking for write enable in spi_nor_macronix_octal_dtr_enable function. JaimeLiao (4): mtd: spi-nor: add support for Macronix Octal flash mtd: spi-nor-core: Adding different type of command extension in Soft Reset mtd: spi-nor: Parse SFDP SCCR Map mtd: spi-nor-core: Add support for Macronix Octal flash drivers/mtd/spi/Kconfig | 7 ++ drivers/mtd/spi/spi-nor-core.c | 141 ++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi-nor-ids.c | 19 ++++- include/linux/mtd/spi-nor.h | 11 +++ 4 files changed, 176 insertions(+), 2 deletions(-) -- 2.17.1

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[PATCH 0/4] phy: sun4i-usb: Allwinner D1 Support
by Samuel Holland 15 Jul '22

15 Jul '22

This series updates the USB PHY driver to support the Allwinner D1, which is a new RISC-V SoC. First it cleans up a couple of things that tie the driver to the existing ARM port, and then it adds the new PHY variant to the driver. Patches 3-4 are effectively the same as changes made to the Linux driver. After this series, the driver still uses the VBUS and ID pin options from arch/arm/mach-sunxi/Kconfig. Those options will be replaced by devicetree properties in a separate series. Andre Przywara (1): phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling Samuel Holland (3): sunxi: Move INITIAL_USB_SCAN_DELAY to driver Kconfig phy: sun4i-usb: Drop use of arch-specific headers phy: sun4i-usb: Add D1 variant arch/arm/mach-sunxi/Kconfig | 9 ------ drivers/phy/allwinner/Kconfig | 10 ++++++ drivers/phy/allwinner/phy-sun4i-usb.c | 44 +++++++++++++++------------ 3 files changed, 34 insertions(+), 29 deletions(-) -- 2.35.1

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[PATCH 1/2] tools: relocate-rela: Remove guard around R_AARCH64_RELATIVE
by Michal Simek 15 Jul '22

15 Jul '22

In code you can find out this fragment: 19 #ifndef R_AARCH64_RELATIVE 20 #define R_AARCH64_RELATIVE 1027 21 #endif which means that R_AARCH64_RELATIVE is defined all the time that's why ifdef is not needed. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- tools/relocate-rela.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index 090fb1acb20c..13cce24151c7 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -43,10 +43,8 @@ static bool supported_rela(Elf64_Rela *rela) uint32_t type = rela->r_info & mask; switch (type) { -#ifdef R_AARCH64_RELATIVE case R_AARCH64_RELATIVE: return true; -#endif default: fprintf(stderr, "warning: unsupported relocation type %" PRIu32 " at %" PRIx64 "\n", -- 2.36.1

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[PATCH] dt-bindings: versal: Add versal reset IDs
by Michal Simek 15 Jul '22

15 Jul '22

The same file is already the part of Linux kernel that's why add it also to u-boot to be able to use it in source code and DT files. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- .../dt-bindings/reset/xlnx-versal-resets.h | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 include/dt-bindings/reset/xlnx-versal-resets.h diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h new file mode 100644 index 000000000000..895424e9b0e5 --- /dev/null +++ b/include/dt-bindings/reset/xlnx-versal-resets.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_RESETS_H +#define _DT_BINDINGS_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif -- 2.36.1

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[PATCH] xilinx: Remove duplicate PMIO_NODE_ID_BASE macro
by Michal Simek 15 Jul '22

15 Jul '22

PMIO_NODE_ID_BASE is defined twice that's why remove one instance. Fixes: 248fe9f302df ("spi: cadence_qspi: Enable apb linear mode for apb read & write operations") Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- include/zynqmp_firmware.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 6c4fd9a6c5f2..86c14d560e12 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -435,8 +435,6 @@ enum pm_gem_config_type { #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) #define PMIO_NODE_ID_BASE 0x1410801B -#define PMIO_NODE_ID_BASE 0x1410801B - /* * Return payload size * Not every firmware call expects the same amount of return bytes, however the -- 2.36.1

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[PATCH] test/py: Run simple dm commands without checking
by Michal Simek 15 Jul '22

15 Jul '22

From: Michal Simek <michal.simek(a)xilinx.com> Just to make sure that dm commands can operate. This was the problem on Microblaze in past without fixing manual relocation. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- test/py/tests/test_dm.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/test/py/tests/test_dm.py b/test/py/tests/test_dm.py index 97203b536e17..ea93061fdfa8 100644 --- a/test/py/tests/test_dm.py +++ b/test/py/tests/test_dm.py @@ -33,3 +33,11 @@ def test_dm_static(u_boot_console): response = u_boot_console.run_command('dm drivers') for driver in drivers: assert driver in response + +(a)pytest.mark.buildconfigspec("cmd_dm") +def test_dm_uclass(u_boot_console): + response = u_boot_console.run_command("dm uclass") + +(a)pytest.mark.buildconfigspec("cmd_dm") +def test_dm_devres(u_boot_console): + response = u_boot_console.run_command("dm devres") -- 2.36.1

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[PATCH] py: tests: Bind should run only on sandbox
by Michal Simek 15 Jul '22

15 Jul '22

From: Michal Simek <michal.simek(a)xilinx.com> Disable test to run on any other platform than sandbox. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- test/py/tests/test_bind.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py index 8ad277da190b..00f99374195f 100644 --- a/test/py/tests/test_bind.py +++ b/test/py/tests/test_bind.py @@ -24,7 +24,7 @@ def in_tree(response, name, uclass, drv, depth, last_child): return True return False - +(a)pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('cmd_bind') def test_bind_unbind_with_node(u_boot_console): @@ -116,6 +116,7 @@ def get_next_line(tree, name): break return child_line +(a)pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('cmd_bind') def test_bind_unbind_with_uclass(u_boot_console): #bind /bind-test -- 2.36.1

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[PATCH v3 1/3] lmb: Fix lmb property's defination under struct lmb
by Michal Simek 15 Jul '22

15 Jul '22

From: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Under struct lmb {} the lmb property's should be defined only if CONFIG_LMB_MEMORY_REGIONS is defined. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- (no changes since v2) Changes in v2: - Also fix lib/lmb.c include/lmb.h | 2 +- lib/lmb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/lmb.h b/include/lmb.h index ab277ca80004..1476d78c2823 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -68,7 +68,7 @@ struct lmb_region { struct lmb { struct lmb_region memory; struct lmb_region reserved; -#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) +#if IS_ENABLED(CONFIG_LMB_MEMORY_REGIONS) struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS]; struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS]; #endif diff --git a/lib/lmb.c b/lib/lmb.c index f72996a4248e..f21fe672ae96 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -108,7 +108,7 @@ void lmb_init(struct lmb *lmb) #if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) lmb->memory.max = CONFIG_LMB_MAX_REGIONS; lmb->reserved.max = CONFIG_LMB_MAX_REGIONS; -#else +#elif IS_ENABLED(CONFIG_LMB_MEMORY_REGIONS) lmb->memory.max = CONFIG_LMB_MEMORY_REGIONS; lmb->reserved.max = CONFIG_LMB_RESERVED_REGIONS; lmb->memory.region = lmb->memory_regions; -- 2.36.1

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[PATCH] arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED
by Michal Simek 15 Jul '22

15 Jul '22

CONFIG_OF_LIBFDT is used twice for guarding the same code. It is enough to do it once that's why remove additional ifdefs from arm and risc-v code. Fixes: 0c303f9a6628 ("image: Drop IMAGE_ENABLE_OF_LIBFDT") Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/lib/bootm.c | 2 -- arch/riscv/lib/bootm.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index a59a5e6c0ea0..fc22befeac1f 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -200,12 +200,10 @@ static void boot_prep_linux(bootm_headers_t *images) char *commandline = env_get("bootargs"); if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { -#ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { panic("FDT creation failed!"); } -#endif } else if (BOOTM_ENABLE_TAGS) { debug("using: ATAGS\n"); setup_start_tag(gd->bd); diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 2e1e286c8ef6..c1ac339283a6 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -65,13 +65,11 @@ static void announce_and_cleanup(int fake) static void boot_prep_linux(bootm_headers_t *images) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { -#ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { printf("FDT creation failed! hanging..."); hang(); } -#endif } else { printf("Device tree not found or missing FDT support\n"); hang(); -- 2.36.1

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[PATCH] arm64: zynqmp: Enable SLG gpo driver by default
by Michal Simek 15 Jul '22

15 Jul '22

This device is used on SOM CCs that's why enable it by default. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 855a1c97731a..2763346f785f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -138,6 +138,7 @@ CONFIG_FPGA_ZYNQMPPL=y CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y CONFIG_DM_PCA953X=y +CONFIG_SLG7XL45106_I2C_GPO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y -- 2.36.1

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