July 2022 - U-Boot

[RFC PATCH 1/2] spl: enable regulator-boot-on and disable regulator-force-boot-off
by Quentin Schulz 18 Jul '22

18 Jul '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> This makes sure regulators that need to be turned on or off at boot are turned on or off in the SPL. This may be required for the SPL to do some operations, such as finding possible loading media for U-Boot proper. Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- - RFC because only tested on Puma Haikou RK3399 common/spl/spl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index c8c463f80b..762e9918c7 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -37,6 +37,9 @@ #include <fdt_support.h> #include <bootcount.h> #include <wdt.h> +#if CONFIG_IS_ENABLED(DM_REGULATOR) +#include <power/regulator.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -766,6 +769,15 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(GPIO_HOG)) gpio_hog_probe_all(); + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", + __func__); + if (regulators_enable_boot_off(false)) + debug("%s: Cannot enable boot off regulator\n", + __func__); + } + #if CONFIG_IS_ENABLED(BOARD_INIT) spl_board_init(); #endif -- 2.36.1

2 5

[PATCH v2 1/2] rockchip: rk3399: fix incorrect ifdef check on SPL_DM_REGULATOR
by Quentin Schulz 18 Jul '22

18 Jul '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> The check to perform is on CONFIG_SPL_DM_REGULATOR and not SPL_DM_REGULATOR. Also switch to in-code check instead of ifdefs. Fixes: 07586ee4322a ("rockchip: rk3399: Support common spl_board_init") Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- v2: - use IS_ENABLED checks, arch/arm/mach-rockchip/rk3399/rk3399.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index de11a3fa30..920da22307 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -275,13 +275,14 @@ void spl_board_init(void) rk3399_force_power_on_reset(); #endif -#if defined(SPL_DM_REGULATOR) - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - if (regulators_enable_boot_on(false)) - debug("%s: Cannot enable boot on regulator\n", __func__); -#endif + if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) { + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", + __func__); + } } #endif -- 2.36.1

2 4

[PATCH v6 00/13] FWU: Add FWU Multi Bank Update feature support
by Sughosh Ganu 18 Jul '22

18 Jul '22

The patchset adds support for the FWU Multi Bank Update[1] feature. Certain aspects of the Dependable Boot[2] specification have also been implemented. The FWU multi bank update feature is used for supporting multiple sets(also called banks) of firmware image(s), allowing the platform to boot from a different bank, in case it fails to boot from the active bank. This functionality is supported by keeping the relevant information in a structure called metadata, which provides information on the images. Among other parameters, the metadata structure contains information on the currect active bank that is being used to boot image(s). Functionality is being added to work with the UEFI capsule driver in u-boot. The metadata is read to gather information on the update bank, which is the bank to which the firmware images would be flashed to. On a successful completion of the update of all components, the active bank field in the metadata is updated, to reflect the bank from which the platform will boot on the subsequent boots. Currently, the feature is being enabled on the STM32MP157C-DK2 and Synquacer boards. The DK2 board boots a FIP image from a uSD card partitioned with the GPT partioning scheme, while the Synquacer board boots a FIP image from a MTD partitioned SPI NOR flash device. This feature also requires changes in a previous stage of bootloader, which parses the metadata and selects the bank to boot the image(s) from. Support has being added in tf-a(BL2 stage) for the STM32MP157C-DK2 board to boot the active bank images. These changes have been merged to the upstream tf-a repository. The earlier patchset contained patches for both the DK2 and the Synquacer platforms. The handling of review comments for the Synquacer platform is to be taken up by a different engineer, and has not been done yet. After discussion with Tom Rini and Heinrich, it was decided to send the patches for the DK2 platform separately for review. The patch for adding a python test for the feature has been developed, and was sent in the version 5 of the patches[3]. However, the test script depends on adding support for the feature on MTD SPI NOR devices, and that is being done as part of the Synquacer patches. Hence these set of patches do not have the test script for the feature. That will be added through the patches for adding support for the feauture on Synquacer platform. [1] - https://developer.arm.com/documentation/den0118/a [2] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24… [3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html Changes since V5: * Changed to yaml file from txt as per review comment * Change the parameter to the function fwu_plat_get_alt_num to pass the FWU udevice pointer instead of passing the metadata device directly. * Changed the logic to store the GPT partitioned block device through a priv structure as suggested by Patrick * Used dev_read_prop() to get the phandle_p instead of ofnode_get_property() used earlier as suggested by Patrick * Made relevant functions static as suggested by Etienne * Change the mechanism to get the block device descriptor in fwu_plat_get_alt_num() due to introduction of struct fwu_mdata_gpt_blk_priv in the earlier patch. * Shuffled the location of the TAMP_FWU_* macros as suggested by Patrick * Use u"TrialStateCtr" for the EFI variable name as suggested by Patrick * Dropped the call to uclass_get_device() in fwu_boottime_checks() as suggested by Patrick * Pass NULL instead of a pointer to trial_state_ctr variable when deleting the variable as suggested by Etienne * Use u"TrialStateCtr" as suggested by Patrick * Do a metadata validity check by calling fwu_mdata_check() before printing the FWU metadata as suggested by Michal * Use ret and res variables in do_fwu_mdata_read() as suggested by Patrick * Change 'default y if FWU_MULTI_BANK_UPDATE' to default y as suggested by Patrick * Use capsule_type instead of capsule variable that was created earlier to check for the type of capsule * Remove use of payload variable in create_empty_capsule() as suggested by Etienne * Initialise the struct efi_capsule_header as suggested by Etienne * Add some description about the reasoning for accept capsule needing image GUID as suggested by Takahiro Sughosh Ganu (13): dt/bindings: Add bindings for FWU Metadata storage device FWU: Add FWU metadata structure and driver for accessing metadata FWU: Add FWU metadata access driver for GPT partitioned block devices stm32mp1: dk2: Add a node for the FWU metadata device stm32mp1: dk2: Add image information for capsule updates FWU: stm32mp1: Add helper functions for accessing FWU metadata FWU: STM32MP1: Add support to read boot index from backup register FWU: Add boot time checks as highlighted by the FWU specification FWU: Add support for the FWU Multi Bank Update feature FWU: cmd: Add a command to read FWU metadata mkeficapsule: Add support for generating empty capsules mkeficapsule: Add support for setting OEM flags in capsule header FWU: doc: Add documentation for the FWU feature arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 7 + arch/arm/mach-stm32mp/include/mach/stm32.h | 5 + board/st/stm32mp1/stm32mp1.c | 67 +++ cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/fwu_mdata.c | 80 +++ common/board_r.c | 5 + doc/develop/uefi/fwu_updates.rst | 156 ++++++ doc/develop/uefi/index.rst | 1 + doc/develop/uefi/uefi.rst | 2 + .../firmware/fwu-mdata.yaml | 32 ++ doc/mkeficapsule.1 | 33 +- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/fwu-mdata/Kconfig | 16 + drivers/fwu-mdata/Makefile | 7 + drivers/fwu-mdata/fwu-mdata-uclass.c | 458 ++++++++++++++++++ drivers/fwu-mdata/fwu_mdata_gpt_blk.c | 408 ++++++++++++++++ include/configs/stm32mp15_common.h | 4 + include/dm/uclass-id.h | 1 + include/fwu.h | 71 +++ include/fwu_mdata.h | 67 +++ lib/Kconfig | 6 + lib/Makefile | 1 + lib/efi_loader/efi_capsule.c | 231 ++++++++- lib/efi_loader/efi_setup.c | 3 +- lib/fwu_updates/Kconfig | 31 ++ lib/fwu_updates/Makefile | 7 + lib/fwu_updates/fwu.c | 191 ++++++++ lib/fwu_updates/fwu_gpt.c | 88 ++++ tools/eficapsule.h | 8 + tools/mkeficapsule.c | 105 +++- 32 files changed, 2081 insertions(+), 21 deletions(-) create mode 100644 cmd/fwu_mdata.c create mode 100644 doc/develop/uefi/fwu_updates.rst create mode 100644 doc/device-tree-bindings/firmware/fwu-mdata.yaml create mode 100644 drivers/fwu-mdata/Kconfig create mode 100644 drivers/fwu-mdata/Makefile create mode 100644 drivers/fwu-mdata/fwu-mdata-uclass.c create mode 100644 drivers/fwu-mdata/fwu_mdata_gpt_blk.c create mode 100644 include/fwu.h create mode 100644 include/fwu_mdata.h create mode 100644 lib/fwu_updates/Kconfig create mode 100644 lib/fwu_updates/Makefile create mode 100644 lib/fwu_updates/fwu.c create mode 100644 lib/fwu_updates/fwu_gpt.c -- 2.25.1

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[PATCH] efi: test/py: repair authenticated capsules tests
by Vincent Stehlé 18 Jul '22

18 Jul '22

The UEFI console initialisation has been modified by commit 68edbed454b8 ("efi_loader: initialize console size late"). A corresponding workaround is now necessary for the automated tests, as added to some of the tests already by commit e05bd68ed5fc ("test: work around for EFI terminal size probing"). Add the same workaround to the UEFI authenticated capsules tests to repair them. This can be tested with sandbox_defconfig, sandbox64_defconfig or sandbox_flattree_defconfig, plus CONFIG_EFI_CAPSULE_AUTHENTICATE=y. Signed-off-by: Vincent Stehlé <vincent.stehle(a)arm.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- .../tests/test_efi_capsule/test_capsule_firmware_signed_fit.py | 3 +++ .../tests/test_efi_capsule/test_capsule_firmware_signed_raw.py | 2 ++ 2 files changed, 5 insertions(+) diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py index 4400b8f1368..d6ca9b16745 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py @@ -40,6 +40,7 @@ class TestEfiCapsuleFirmwareSignedFit(object): with u_boot_console.log.section('Test Case 1-a, before reboot'): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, + 'printenv -e PlatformLangCodes', # workaround for terminal size determination 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', 'efidebug boot order 1', 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', @@ -115,6 +116,7 @@ class TestEfiCapsuleFirmwareSignedFit(object): with u_boot_console.log.section('Test Case 2-a, before reboot'): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, + 'printenv -e PlatformLangCodes', # workaround for terminal size determination 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', 'efidebug boot order 1', 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', @@ -192,6 +194,7 @@ class TestEfiCapsuleFirmwareSignedFit(object): with u_boot_console.log.section('Test Case 3-a, before reboot'): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, + 'printenv -e PlatformLangCodes', # workaround for terminal size determination 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', 'efidebug boot order 1', 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py index 1b5a1bb42eb..2bbaa9cc55f 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py @@ -112,6 +112,7 @@ class TestEfiCapsuleFirmwareSignedRaw(object): with u_boot_console.log.section('Test Case 2-a, before reboot'): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, + 'printenv -e PlatformLangCodes', # workaround for terminal size determination 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', 'efidebug boot order 1', 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', @@ -189,6 +190,7 @@ class TestEfiCapsuleFirmwareSignedRaw(object): with u_boot_console.log.section('Test Case 3-a, before reboot'): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, + 'printenv -e PlatformLangCodes', # workaround for terminal size determination 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', 'efidebug boot order 1', 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', -- 2.35.1

3 3

[PATCH] sunxi-nand: fix the PIO instead of DMA implementation
by Markus Hoffrogge 18 Jul '22

18 Jul '22

The sunxi nand SPL loader was broken at least for SUN4I, SUN5I and SUN7I SOCs since the implementation change from DMA to PIO usage - commit 6ddbb1e. Root cause for this issue is the NFC control flag NFC_CTL_RAM_METHOD being set by method nand_apply_config. This flag controls the bus being used for the NFCs internal RAM access. It must be set for the DMA use case only. See A33_Nand_Flash_Controller_Specification.pdf page 12. This fix is tested by myself on a Cubietruck A20 board. Others should test it on new generation SOCs as well. Signed-off-by: Markus Hoffrogge <mhoffrogge(a)gmail.com> --- drivers/mtd/nand/raw/sunxi_nand_spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index a29a76c58d..6de0b0a355 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -208,7 +208,7 @@ static void nand_apply_config(const struct nfc_config *conf) val = readl(SUNXI_NFC_BASE + NFC_CTL); val &= ~NFC_CTL_PAGE_SIZE_MASK; - writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size), + writel(val | NFC_CTL_PAGE_SIZE(conf->page_size), SUNXI_NFC_BASE + NFC_CTL); writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT); writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA); --

6 11

[PATCH sunxi/next] spi: sunxi: use XCH status to detect in-progress transfer
by Icenowy Zheng 18 Jul '22

18 Jul '22

The current detection of RX FIFO depth seems to be not reliable, and XCH will self-clear when a transfer is done. Check XCH bit when polling for transfer finish. Signed-off-by: Icenowy Zheng <uwu(a)icenowy.me> --- drivers/spi/spi-sunxi.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 2f33337725..a424c6a98e 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -83,7 +83,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #define SUN4I_SPI_MIN_RATE 3000 #define SUN4I_SPI_DEFAULT_RATE 1000000 -#define SUN4I_SPI_TIMEOUT_US 1000000 +#define SUN4I_SPI_TIMEOUT_MS 1000 #define SPI_REG(priv, reg) ((priv)->base + \ (priv)->variant->regs[reg]) @@ -326,7 +326,6 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); u32 len = bitlen / 8; - u32 rx_fifocnt; u8 nbytes; int ret; @@ -364,13 +363,10 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_XCH)); - /* Wait till RX FIFO to be empty */ - ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR), - rx_fifocnt, - (((rx_fifocnt & - SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >> - SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes), - SUN4I_SPI_TIMEOUT_US); + /* Wait for the transfer to be done */ + ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR), + SPI_BIT(priv, SPI_TCR_XCH), + false, SUN4I_SPI_TIMEOUT_MS, false); if (ret < 0) { printf("ERROR: sun4i_spi: Timeout transferring data\n"); sun4i_spi_set_cs(bus, slave_plat->cs, false); -- 2.36.0

2 3

[PATCH v1] drivers: spi: sunxi: Fix spi speed settting
by qianfanguijin＠163.com 18 Jul '22

18 Jul '22

From: qianfan Zhao <qianfanguijin(a)163.com> dm_spi_claim_bus run spi_set_speed_mode first and then ops->claim_bus, but spi clock is enabled when sun4i_spi_claim_bus, that will make sun4i_spi_set_speed doesn't work. Fix it. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- drivers/spi/spi-sunxi.c | 78 ++++++++++++++++------------------------- 1 file changed, 30 insertions(+), 48 deletions(-) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index b6cd7ddafa..1043cde976 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -224,6 +224,7 @@ err_ahb: static int sun4i_spi_claim_bus(struct udevice *dev) { struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + u32 div, reg; int ret; ret = sun4i_spi_set_clock(dev->parent, true); @@ -233,12 +234,38 @@ static int sun4i_spi_claim_bus(struct udevice *dev) setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP)); + /* Setup clock divider */ + div = SUN4I_SPI_MAX_RATE / (2 * priv->freq); + reg = readl(SPI_REG(priv, SPI_CCR)); + + if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { + if (div > 0) + div--; + + reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); + reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + } else { + div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq); + reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); + reg |= SUN4I_CLK_CTL_CDR1(div); + } + + writel(reg, SPI_REG(priv, SPI_CCR)); + if (priv->variant->has_soft_reset) setbits_le32(SPI_REG(priv, SPI_GCR), SPI_BIT(priv, SPI_GCR_SRST)); - setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) | - SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW)); + /* Setup the transfer control register */ + reg = SPI_BIT(priv, SPI_TCR_CS_MANUAL) | + SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW); + + if (priv->mode & SPI_CPOL) + reg |= SPI_BIT(priv, SPI_TCR_CPOL); + if (priv->mode & SPI_CPHA) + reg |= SPI_BIT(priv, SPI_TCR_CPHA); + + writel(reg, SPI_REG(priv, SPI_TCR)); return 0; } @@ -329,67 +356,22 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed) { struct sun4i_spi_plat *plat = dev_get_plat(dev); struct sun4i_spi_priv *priv = dev_get_priv(dev); - unsigned int div; - u32 reg; if (speed > plat->max_hz) speed = plat->max_hz; if (speed < SUN4I_SPI_MIN_RATE) speed = SUN4I_SPI_MIN_RATE; - /* - * Setup clock divider. - * - * We have two choices there. Either we can use the clock - * divide rate 1, which is calculated thanks to this formula: - * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) - * Or we can use CDR2, which is calculated with the formula: - * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) - * Whether we use the former or the latter is set through the - * DRS bit. - * - * First try CDR2, and if we can't reach the expected - * frequency, fall back to CDR1. - */ - - div = SUN4I_SPI_MAX_RATE / (2 * speed); - reg = readl(SPI_REG(priv, SPI_CCR)); - - if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { - if (div > 0) - div--; - - reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); - reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; - } else { - div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); - reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); - reg |= SUN4I_CLK_CTL_CDR1(div); - } priv->freq = speed; - writel(reg, SPI_REG(priv, SPI_CCR)); - return 0; } static int sun4i_spi_set_mode(struct udevice *dev, uint mode) { struct sun4i_spi_priv *priv = dev_get_priv(dev); - u32 reg; - - reg = readl(SPI_REG(priv, SPI_TCR)); - reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA)); - - if (mode & SPI_CPOL) - reg |= SPI_BIT(priv, SPI_TCR_CPOL); - - if (mode & SPI_CPHA) - reg |= SPI_BIT(priv, SPI_TCR_CPHA); priv->mode = mode; - writel(reg, SPI_REG(priv, SPI_TCR)); - return 0; } @@ -441,7 +423,7 @@ static int sun4i_spi_of_to_plat(struct udevice *bus) plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus); plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", - SUN4I_SPI_DEFAULT_RATE); + SUN4I_SPI_MAX_RATE); if (plat->max_hz > SUN4I_SPI_MAX_RATE) plat->max_hz = SUN4I_SPI_MAX_RATE; -- 2.25.1

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[PATCH 0/7] sunxi: F1C100s: enable MMC and SPI in U-Boot proper
by Andre Przywara 18 Jul '22

18 Jul '22

So far the U-Boot proper support for the Allwinner F1C100 family of SoCs was really limited: we could realistically only deal with FEL booting, as there was no storage or network device acessible from U-Boot proper. This series enables the MMC and SPI controller, to be able to actually load something from the device. This is made possible by the updates to the devicetree in Linux, which now describes those devices. The first patch is taken from George's/Yifan's older series, and adds DM_CLK support for the F1C100s. The DM_PINCTRL support was already added with the DM conversion a few weeks back. Patches 2-4 fix the SPI driver clock setup, and add support for the differing SPI clock on the F1C100. Patch 5 updates the devicetree files, freshly synced from linux-next. Patch 6 reverts a hack we introduced back then to fix the reset functionality, with the DT update this is now no longer needed. The final patch adds SPI flash support to the Licheepi Nano defconfig, as these boards mostly ship with SPI flash soldered. Please have a look and test! Cheers, Andre Andre Przywara (6): spi: sunxi: refactor SPI speed/mode programming spi: sunxi: improve SPI clock calculation spi: sunxi: Add support for F1C100s SPI controller sunxi: F1C100s: update DT files from Linux Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality" sunxi: licheepi_nano: enable SPI flash George Hilliard (1): clk: sunxi: implement clock driver for suniv f1c100s arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 31 ++++++ arch/arm/dts/suniv-f1c100s.dtsi | 104 ++++++++++++++++-- configs/licheepi_nano_defconfig | 4 +- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_f1c100s.c | 74 +++++++++++++ drivers/spi/spi-sunxi.c | 109 +++++++++++-------- 7 files changed, 275 insertions(+), 55 deletions(-) create mode 100644 drivers/clk/sunxi/clk_f1c100s.c -- 2.35.3

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[PATCH] [Meson] add magicbox m16s config, dts and doc
by Zhang Ning 18 Jul '22

18 Jul '22

MagicBox M16S or MagicBox 3Pro is welcome Tv box in China, which is developed by Alibaba at 2016. No schemtics, no vendor source code right now thus no fip blobs to create mainline u-boot. Need to use chainloader to boot a mainline u-boot, then mainline kernel. from pre-installed u-boot log, it's gxm_q201_v1 or its decendent. add a simple dts and config to enable this Tv box. a simple doc for how to enable mainline uboot. Signed-off-by: Zhang Ning <zhangn1985(a)qq.com> --- arch/arm/dts/Makefile | 1 + .../dts/meson-gxm-magicbox-m16s-u-boot.dtsi | 6 + arch/arm/dts/meson-gxm-magicbox-m16s.dts | 24 ++++ configs/magicbox-m16s_defconfig | 68 +++++++++++ doc/board/amlogic/index.rst | 1 + doc/board/amlogic/magicboxm16s.rst | 109 ++++++++++++++++++ 6 files changed, 209 insertions(+) create mode 100644 arch/arm/dts/meson-gxm-magicbox-m16s-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-magicbox-m16s.dts create mode 100644 configs/magicbox-m16s_defconfig create mode 100644 doc/board/amlogic/magicboxm16s.rst diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a7e0d9f6c0..31294c4c18 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -191,6 +191,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxm-khadas-vim2.dtb \ meson-gxm-s912-libretech-pc.dtb \ meson-gxm-wetek-core2.dtb \ + meson-gxm-magicbox-m16s.dtb \ meson-g12a-radxa-zero.dtb \ meson-g12a-sei510.dtb \ meson-g12a-u200.dtb \ diff --git a/arch/arm/dts/meson-gxm-magicbox-m16s-u-boot.dtsi b/arch/arm/dts/meson-gxm-magicbox-m16s-u-boot.dtsi new file mode 100644 index 0000000000..87a6e8525e --- /dev/null +++ b/arch/arm/dts/meson-gxm-magicbox-m16s-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Zhang Ning <zhangn1985(a)qq.com> + */ + +#include "meson-gxl-u-boot.dtsi" diff --git a/arch/arm/dts/meson-gxm-magicbox-m16s.dts b/arch/arm/dts/meson-gxm-magicbox-m16s.dts new file mode 100644 index 0000000000..a382fafc51 --- /dev/null +++ b/arch/arm/dts/meson-gxm-magicbox-m16s.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Zhang Ning <zhangn1985(a)qq.com> + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "magicbox,m16s", "amlogic,s912", "amlogic,meson-gxm"; + model = "Magicbox M16S"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB */ + }; + +}; +&ethmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; diff --git a/configs/magicbox-m16s_defconfig b/configs/magicbox-m16s_defconfig new file mode 100644 index 0000000000..df9a746b65 --- /dev/null +++ b/configs/magicbox-m16s_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-magicbox-m16s" +CONFIG_MESON_GXM=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" magicbox m16s" +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_DEBUG_UART=y +CONFIG_REMAKE_ELF=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +# CONFIG_EFI_LOADER is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SARADC_MESON=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_GXL=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 9c7fadf2c0..2620b38b5d 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -113,3 +113,4 @@ Board Documentation u200 wetek-core2 w400 + magicboxm16s diff --git a/doc/board/amlogic/magicboxm16s.rst b/doc/board/amlogic/magicboxm16s.rst new file mode 100644 index 0000000000..2161fb1d0c --- /dev/null +++ b/doc/board/amlogic/magicboxm16s.rst @@ -0,0 +1,109 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Hacking notes for MagicBox M16S +======================= + +MagicBox M16S or MagicBox 3Pro is popular Tv box in China, which is +manufactured by Alibaba in 2016, with following specifications: + + - Amlogic S912-H (S192 with dolby and DTS) + - 2GB DDR3 SDRAM + - 100M Ethernet + - HDMI 2.0 4K/60Hz display + - 1 x USB 2.0 + - 16G eMMC + - Infrared receiver + - Marvel SD8897 WiFi module + - AV out + - Rest hole + - 5V2A power jack + +No schematics and source code available from vendor. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make magicbox-m16s_defconfig + $ make + +Enable chainloader +-------------- + +Due to no vendor source code, thus not able to create bootable u-boot image as other devices. + +thus only way to run mainline u-boot is chainloader. + +Step1: connect TTL to mainboard. + +Open metal cover, and you will see TTL test points show as below: + + G>--- <<-- gnd + + --- <<-- Tx + + --- <<-- Rx + + --- <<-- pwr + +Connect an USB TTL to these test points. + +Step2: enable chainloader. + +Connect USE TTL to you PC, and open it with any teminal tool, with configure: 115200n8 + +Power on Tv box, and press `enter` on your keyboard. and then you get: + +.. code-block:: bash + gxm_q201_v1# + +If not, power off, and redo this step. + +Type below u-boot command to console: + +.. code-block:: bash + setenv OLDBOOTCMD "set_usb_boot 4;run storeboot" + setenv USBBOOTCMD "usb start;if fatload usb 0 0x1000000 u-boot.bin; then go 0x1000000; fi;" + setenv bootcmd "run USBBOOTCMD; run OLDBOOTCMD; run storeboot" + saveenv + sleep 1 + reboot + +If you reboot to pre-installed OS, there will be a very long boot time, just wait, it's not brick. + +Step2: prepare boot media + +Parition you Usb flash driver to Dos partition table, and first partition to 10M, format it to fat32. + +Copy u-boot.bin to first partition. + +Insert it to Tv box, it will automatically boot to mainline u-boot. + + +Step3: optional boot script for sysboot + +If you want to use u-boot-menu to generate extlinux.conf to make a grub-like OS menu, +a simple boot script is needed. (assume your extlinux.conf is in 2nd partition) + +.. code-block:: + sysboot usb 0:2 any 0x1080000 /boot/extlinux/extlinux.conf + +# use: mkimage -A arm64 -T script -O linux -d boot.cmd boot.scr + +copy boot.scr to first partition, it will automatically load extlinux.conf and boot to OS. + +Status +----------- +Debian sid with kernel 5.19-rc4 +HDMI: OK, sound not test +WIFI: OK +eth: OK +BT: OK +IR: No decoder, keymap + +Issues: Due need to keep vendor u-boot, not able to use internal emmc. + Due to no power key, it will automatically poweron, even after poweroff. + WIFI loss after reboot, need disconnect power to recover. + -- 2.35.1

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[PATCH 0/4] Convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
by Daniel Schwierzeck 18 Jul '22

18 Jul '22

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