May 2022 - U-Boot

[PATCH v4 0/3] Add support for different mediatek pinctrl designs
by Sam Shih 05 May '22

05 May '22

MediaTek SoC's pinconf register usage varies by SoC, So the original code uses V0/V1 to mark different pinconf design. But actually, the real difference is the design of the "pin" itself. Different SoCs will choose specify "pin design", which we call the "io_type" of the pin. For a better understanding of mediatek pinctrl design. and make the driver clear and flexible, this patch series changes common parts of mediatek pinctrl driver to support various pinctrl controller designs. The following mediatek config were tested to ensure the build passed: - mt7622_rfb_defconfig - mt7623a_unielec_u7623_02_defconfig - mt7623n_bpir2_defconfig - mt7629_rfb_defconfig - mt8183_pumpkin_defconfig - mt8512_bm1_emmc_defconfig - mt8516_pumpkin_defconfig - mt8518_ap1_emmc_defconfig --- v4: fix mt8518_ap1_emmc build fail v3: fix v2 patch series misapplied v2: fix build fail caused by patch [2/3] Sam Shih (3): pinctrl: mediatek: rewrite mtk_pinconf_set and related functions pinctrl: mediatek: introduce multiple memory bases support pinctrl: mediatek: add support for different types of IO pins drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 221 ++++++++++++++---- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 78 ++++++- 2 files changed, 248 insertions(+), 51 deletions(-) -- 2.18.0

2 6

[PATCH v1 1/1] gpio: npcm: Add support for Nuvoton NPCM SoCs
by Stanley Chu 05 May '22

05 May '22

Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver Signed-off-by: Stanley Chu <yschu(a)nuvoton.com> --- drivers/gpio/Kconfig | 7 +++ drivers/gpio/Makefile | 1 + drivers/gpio/npcm_gpio.c | 123 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/gpio/npcm_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8d0e47c67d..e1a1f1c4db 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -247,6 +247,13 @@ config MXS_GPIO help Support GPIO controllers on i.MX23 and i.MX28 platforms +config NPCM_GPIO + bool "Nuvoton NPCM GPIO driver" + depends on DM_GPIO + help + Support GPIO controllers on Nuvovon NPCM SoCs. + NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins. + config OMAP_GPIO bool "TI OMAP GPIO driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 63e9be6034..a42ae77285 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o +obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c new file mode 100644 index 0000000000..8afd57fa8e --- /dev/null +++ b/drivers/gpio/npcm_gpio.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <linux/io.h> + +#define NPCM_GPIOS_PER_BANK 32 + +/* Register offsets */ +#define GPIO_DIN 0x4 /* RO - Data In */ +#define GPIO_DOUT 0xC /* RW - Data Out */ +#define GPIO_OE 0x10 /* RW - Output Enable */ +#define GPIO_IEM 0x58 /* RW - Input Enable Mask */ +#define GPIO_OES 0x70 /* WO - Output Enable Register Set */ +#define GPIO_OEC 0x74 /* WO - Output Enable Register Clear */ + +struct npcm_gpio_priv { + void __iomem *base; +}; + +static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + writel(BIT(offset), priv->base + GPIO_OEC); + setbits_le32(priv->base + GPIO_IEM, BIT(offset)); + + return 0; +} + +static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); + writel(BIT(offset), priv->base + GPIO_OES); + + if (value) + setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + else + clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + + return 0; +} + +static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + GPIO_IEM) & BIT(offset)) + return !!(readl(priv->base + GPIO_DIN) & BIT(offset)); + + if (readl(priv->base + GPIO_OE) & BIT(offset)) + return !!(readl(priv->base + GPIO_DOUT) & BIT(offset)); + + return -EINVAL; +} + +static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + if (value) + setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + else + clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + + return 0; +} + +static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + GPIO_IEM) & BIT(offset)) + return GPIOF_INPUT; + + if (readl(priv->base + GPIO_OE) & BIT(offset)) + return GPIOF_OUTPUT; + + return GPIOF_FUNC; +} + +static const struct dm_gpio_ops npcm_gpio_ops = { + .direction_input = npcm_gpio_direction_input, + .direction_output = npcm_gpio_direction_output, + .get_value = npcm_gpio_get_value, + .set_value = npcm_gpio_set_value, + .get_function = npcm_gpio_get_function, +}; + +static int npcm_gpio_probe(struct udevice *dev) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + uc_priv->gpio_count = NPCM_GPIOS_PER_BANK; + uc_priv->bank_name = dev->name; + + return 0; +} + +static const struct udevice_id npcm_gpio_match[] = { + { .compatible = "nuvoton,npcm845-gpio" }, + { .compatible = "nuvoton,npcm750-gpio" }, + { } +}; + +U_BOOT_DRIVER(npcm_gpio) = { + .name = "npcm_gpio", + .id = UCLASS_GPIO, + .of_match = npcm_gpio_match, + .probe = npcm_gpio_probe, + .priv_auto = sizeof(struct npcm_gpio_priv), + .ops = &npcm_gpio_ops, +}; -- 2.17.1

2 1

[PATCH v3 0/4] Add Nuvoton NPCM750 support
by Jim Liu 05 May '22

05 May '22

The patch series add basic supoorts for NPCM750, which is Nuvoton's 3th-generation BMC (Baseboard Management Controller). Add drivers to support Clock,Timer,Uart for NPCM7xx SoC. the NPCM750 computing subsystem comprises a dual-core ARM a9 at 800MHz speed with L1/L2 caches dts,dtsi and npcm7xx-reset.h have been submitted to kernel upstream. the patch is base on top of current master and pass the CI test. https://github.com/u-boot/u-boot/pull/169 Jim Liu (4): arm: nuvoton: Add support for Nuvoton NPCM750 BMC clk: nuvoton: Add support for NPCM750 serial: npcm: Add support for Nuvoton NPCM SoCs timer: npcm: Add NPCM timer support arch/arm/Kconfig | 8 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/nuvoton-common-npcm7xx.dtsi | 1120 +++++++++++++++++ arch/arm/dts/nuvoton-npcm750-evb.dts | 405 ++++++ arch/arm/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++ arch/arm/dts/nuvoton-npcm750.dtsi | 62 + arch/arm/include/asm/arch-npcm7xx/gcr.h | 65 + arch/arm/mach-npcm/Kconfig | 26 + arch/arm/mach-npcm/Makefile | 1 + arch/arm/mach-npcm/npcm7xx/Kconfig | 22 + arch/arm/mach-npcm/npcm7xx/Makefile | 1 + arch/arm/mach-npcm/npcm7xx/cpu.c | 66 + arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c | 29 + .../mach-npcm/npcm7xx/l2_cache_pl310_init.S | 71 ++ board/nuvoton/poleg_evb/Kconfig | 25 + board/nuvoton/poleg_evb/MAINTAINERS | 7 + board/nuvoton/poleg_evb/Makefile | 1 + board/nuvoton/poleg_evb/poleg_evb.c | 48 + configs/poleg_evb_defconfig | 40 + drivers/clk/Makefile | 1 + drivers/clk/nuvoton/Makefile | 2 + drivers/clk/nuvoton/clk_npcm.c | 299 +++++ drivers/clk/nuvoton/clk_npcm.h | 105 ++ drivers/clk/nuvoton/clk_npcm7xx.c | 95 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_npcm.c | 157 +++ drivers/timer/Kconfig | 9 + drivers/timer/Makefile | 1 + drivers/timer/npcm-timer.c | 115 ++ include/configs/poleg.h | 44 + .../dt-bindings/clock/nuvoton,npcm7xx-clock.h | 46 + .../dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 ++ 34 files changed, 3131 insertions(+) create mode 100644 arch/arm/dts/nuvoton-common-npcm7xx.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm750-evb.dts create mode 100644 arch/arm/dts/nuvoton-npcm750-pincfg-evb.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm750.dtsi create mode 100644 arch/arm/include/asm/arch-npcm7xx/gcr.h create mode 100644 arch/arm/mach-npcm/Kconfig create mode 100644 arch/arm/mach-npcm/Makefile create mode 100644 arch/arm/mach-npcm/npcm7xx/Kconfig create mode 100644 arch/arm/mach-npcm/npcm7xx/Makefile create mode 100644 arch/arm/mach-npcm/npcm7xx/cpu.c create mode 100644 arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c create mode 100644 arch/arm/mach-npcm/npcm7xx/l2_cache_pl310_init.S create mode 100644 board/nuvoton/poleg_evb/Kconfig create mode 100644 board/nuvoton/poleg_evb/MAINTAINERS create mode 100644 board/nuvoton/poleg_evb/Makefile create mode 100644 board/nuvoton/poleg_evb/poleg_evb.c create mode 100644 configs/poleg_evb_defconfig create mode 100644 drivers/clk/nuvoton/Makefile create mode 100644 drivers/clk/nuvoton/clk_npcm.c create mode 100644 drivers/clk/nuvoton/clk_npcm.h create mode 100644 drivers/clk/nuvoton/clk_npcm7xx.c create mode 100644 drivers/serial/serial_npcm.c create mode 100644 drivers/timer/npcm-timer.c create mode 100644 include/configs/poleg.h create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h -- 2.17.1

3 9

[PATCH] Makefile: Avoid non-portable GNU sed extension
by Mark Kettenis 05 May '22

05 May '22

Use [:space:] instead of \s and \S in regular expression that determines the sandbox target architecture. Fixes the build failure on OpenBSD introduced with commit 4e65ca00f3a3 ("efi_loader: bootmgr: add booting from removable media"). Fixes: f7691a6d73 ("sandbox: allow cross-compiling sandbox") Signed-off-by: Mark Kettenis <kettenis(a)openbsd.org> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ea80f00716..6eceeb35b4 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ include include/host_arch.h ifeq ("", "$(CROSS_COMPILE)") MK_ARCH="${shell uname -m}" else - MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\s*$[^\/]*\/$*$[^-]*$-\S*/\2/p'}" + MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^[[:space:]]*$[^\/]*\/$*$[^-]*$-[^[:space:]]*/\2/p'}" endif unexport HOST_ARCH ifeq ("x86_64", $(MK_ARCH)) -- 2.36.0

3 3

[PATCH 1/2] usb: host: ehci-generic: Make usage of clock/reset bulk() API
by Patrice Chotard 05 May '22

05 May '22

Make usage of clock and reset bulk API in order to simplify the code Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- drivers/usb/host/ehci-generic.c | 97 ++++++++++----------------------- 1 file changed, 29 insertions(+), 68 deletions(-) diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 4c28a69b98..5856e898a8 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -23,14 +23,12 @@ */ struct generic_ehci { struct ehci_ctrl ctrl; - struct clk *clocks; - struct reset_ctl *resets; + struct clk_bulk clocks; + struct reset_ctl_bulk resets; struct phy phy; #ifdef CONFIG_DM_REGULATOR struct udevice *vbus_supply; #endif - int clock_count; - int reset_count; }; #ifdef CONFIG_DM_REGULATOR @@ -81,68 +79,31 @@ static int ehci_usb_probe(struct udevice *dev) struct generic_ehci *priv = dev_get_priv(dev); struct ehci_hccr *hccr; struct ehci_hcor *hcor; - int i, err, ret, clock_nb, reset_nb; + int err, ret; err = 0; - priv->clock_count = 0; - clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks", - "#clock-cells", 0); - if (clock_nb > 0) { - priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), - GFP_KERNEL); - if (!priv->clocks) - return -ENOMEM; - - for (i = 0; i < clock_nb; i++) { - err = clk_get_by_index(dev, i, &priv->clocks[i]); - - if (err < 0) - break; - err = clk_enable(&priv->clocks[i]); - if (err && err != -ENOSYS) { - dev_err(dev, "failed to enable clock %d\n", i); - clk_free(&priv->clocks[i]); - goto clk_err; - } - priv->clock_count++; - } - } else { - if (clock_nb != -ENOENT) { - dev_err(dev, "failed to get clock phandle(%d)\n", - clock_nb); - return clock_nb; - } + ret = clk_get_bulk(dev, &priv->clocks); + if (ret) { + dev_err(dev, "Failed to get clocks\n"); + return ret; } - priv->reset_count = 0; - reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets", - "#reset-cells", 0); - if (reset_nb > 0) { - priv->resets = devm_kcalloc(dev, reset_nb, - sizeof(struct reset_ctl), - GFP_KERNEL); - if (!priv->resets) - return -ENOMEM; - - for (i = 0; i < reset_nb; i++) { - err = reset_get_by_index(dev, i, &priv->resets[i]); - if (err < 0) - break; - - if (reset_deassert(&priv->resets[i])) { - dev_err(dev, "failed to deassert reset %d\n", - i); - reset_free(&priv->resets[i]); - goto reset_err; - } - priv->reset_count++; - } - } else { - if (reset_nb != -ENOENT) { - dev_err(dev, "failed to get reset phandle(%d)\n", - reset_nb); - goto clk_err; - } + err = clk_enable_bulk(&priv->clocks); + if (err) { + dev_err(dev, "Failed to enable clocks\n"); + goto clk_err; + } + + err = reset_get_bulk(dev, &priv->resets); + if (err) { + dev_err(dev, "Failed to get resets\n"); + goto clk_err; + } + + err = reset_deassert_bulk(&priv->resets); + if (err) { + dev_err(dev, "Failed to get deassert resets\n"); + goto reset_err; } err = ehci_enable_vbus_supply(dev); @@ -174,13 +135,13 @@ regulator_err: dev_err(dev, "failed to disable VBUS supply\n"); reset_err: - ret = reset_release_all(priv->resets, priv->reset_count); + ret = reset_release_bulk(&priv->resets); if (ret) - dev_err(dev, "failed to assert all resets\n"); + dev_err(dev, "failed to release resets\n"); clk_err: - ret = clk_release_all(priv->clocks, priv->clock_count); + ret = clk_release_bulk(&priv->clocks); if (ret) - dev_err(dev, "failed to disable all clocks\n"); + dev_err(dev, "failed to release clocks\n"); return err; } @@ -202,11 +163,11 @@ static int ehci_usb_remove(struct udevice *dev) if (ret) return ret; - ret = reset_release_all(priv->resets, priv->reset_count); + ret = reset_release_bulk(&priv->resets); if (ret) return ret; - return clk_release_all(priv->clocks, priv->clock_count); + return clk_release_bulk(&priv->clocks); } static const struct udevice_id ehci_usb_ids[] = { -- 2.25.1

3 6

[PATCH] w1: w1-gpio: Loosen timings to improve cold boot reliability
by Chris Morgan 05 May '22

05 May '22

From: Chris Morgan <macromorgan(a)hotmail.com> On my NTC CHIP whenever I do a cold boot any attached DIPs cannot be found. Rebooting on the other hand appears to fix the issue. I found that if I modified the timing slightly (but still within spec) the w1 identification on cold boot became far more reliable. Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- drivers/w1/w1-gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c index 9346f810ce..5565de2a92 100644 --- a/drivers/w1/w1-gpio.c +++ b/drivers/w1/w1-gpio.c @@ -22,8 +22,8 @@ #define W1_TIMING_E 9 #define W1_TIMING_F 55 #define W1_TIMING_G 0 -#define W1_TIMING_H 480 -#define W1_TIMING_I 70 +#define W1_TIMING_H 600 +#define W1_TIMING_I 100 #define W1_TIMING_J 410 struct w1_gpio_pdata { -- 2.30.2

3 6

[PATCH 0/7] sunxi: Fix U-Boot proper SPI operation
by Andre Przywara 05 May '22

05 May '22

Hi, despite U-Boot supporting SPI on Allwinner chips and SPI flash in general for a while, it wasn't really working well for many sunxi boards. Booting from SPI is handled by separate SPL code, which works fine, but the "sf" command in U-Boot proper is often just not operational. This series tries to improve the situation, by: - cleaning up the SPI Kconfig situation for sunxi (patch 2) - adding support for environment in SPI flash (patch 3-5) - trying to enable more boards for U-Boot-proper SPI flash (patch 6) As an added bonus there is some whacky code to make the SPI flash usable in Linux on H6 boards. Marking this as RFC. Actually even after this series many boards still miss out, because they are lacking the required "spi0" alias in the DT. We could go with *-u-boot.dtsi fixes for now (as the SoPine does), but even mainline DT support wouldn't help, as we are somewhat stuck with DT updates. But that's a story for another time, let's get this SPI support fixed first. Cheers, Andre Andre Przywara (6): sunxi: Kconfig: Fix up SPI configuration env: sunxi: Define location in SPI flash sunxi: use boot source for determining environment location env: sunxi: enable ENV_IS_IN_SPI_FLASH sunxi: boards: Enable SPI flash support in U-Boot proper sunxi: H6: Enable SPI0 in DT when no eMMC is used Daniel Wagenknecht (1): sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs arch/arm/Kconfig | 2 + arch/arm/mach-sunxi/Kconfig | 13 ++- board/sunxi/board.c | 101 +++++++++++++++++++++-- configs/libretech_all_h3_it_h5_defconfig | 2 - configs/libretech_all_h5_cc_h5_defconfig | 2 - configs/oceanic_5205_5inmfd_defconfig | 1 + configs/orangepi_pc2_defconfig | 2 + configs/orangepi_r1_defconfig | 2 + configs/orangepi_win_defconfig | 2 + configs/orangepi_zero2_defconfig | 2 + configs/orangepi_zero_defconfig | 2 + configs/pine64-lts_defconfig | 2 + configs/pine_h64_defconfig | 3 + configs/pinecube_defconfig | 2 + configs/sopine_baseboard_defconfig | 1 + drivers/spi/spi-sunxi.c | 3 +- env/Kconfig | 7 +- 17 files changed, 131 insertions(+), 18 deletions(-) -- 2.25.1

3 19

[PATCH v3 00/13] Add support for NVMEM API
by Sean Anderson 05 May '22

05 May '22

This adds support for the nvmem-cells properties cropping up in manyb device trees. This is an easy way to load configuration, version information, or calibration data from a non-volatile memory source. For more information, refer to patch 6 ("misc: Add support for nvmem cells"). For the moment I have only added some integration tests using the ethernet addresses. This hits the main code paths (looking up nvmem cells) but doesn't test writing. I can add a few stand-alone tests if desired. The patches are structured in the following manner: 1-7: These are general cleanups, and may be applied independently of the rest of the series. 8-9: Add NVMEM support 10-13: Support reading ethernet addresses using the NVMEM API and add some tests. Changes in v3: - Add aliases for ethernet devices - Add mac address for eth8 to environment - Move patch adding test earlier in the series - Add test for eth8 as well Changes in v2: - Call the appropriate API functions directly from nvmem_cell_(read|write). This means we can drop the nvmem_interface machinery. Sean Anderson (13): sandbox: net: Add aliases for ethernet devices sandbox: net: Add mac address for eth8 to environment test: eth: Add test for ethernet addresses sandbox: net: Remove fake-host-hwaddr sandbox: Remove eth2addr from environment sandbox: Move some mac addresses to device tree misc: i2c_eeprom: Make i2c_eeprom_write use a const buf misc: Add support for nvmem cells sandbox: Enable NVMEM net: Add support for reading mac addresses from nvmem cells test: Load mac address with i2c eeprom test: Load mac address using RTC test: Load mac address using misc device MAINTAINERS | 7 ++ arch/sandbox/dts/sandbox.dts | 1 - arch/sandbox/dts/sandbox64.dts | 1 - arch/sandbox/dts/test.dts | 34 +++++-- board/sandbox/sandbox.env | 4 - configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_noinst_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + doc/api/index.rst | 1 + doc/api/nvmem.rst | 7 ++ drivers/misc/Kconfig | 16 +++ drivers/misc/Makefile | 1 + drivers/misc/i2c_eeprom.c | 3 +- drivers/misc/i2c_eeprom_emul.c | 4 + drivers/misc/misc_sandbox.c | 3 + drivers/misc/nvmem.c | 142 +++++++++++++++++++++++++++ drivers/net/sandbox.c | 10 +- drivers/rtc/i2c_rtc_emul.c | 10 ++ include/i2c_eeprom.h | 3 +- include/nvmem.h | 151 +++++++++++++++++++++++++++++ net/eth-uclass.c | 13 ++- test/dm/eth.c | 29 ++++++ 24 files changed, 419 insertions(+), 26 deletions(-) create mode 100644 doc/api/nvmem.rst create mode 100644 drivers/misc/nvmem.c create mode 100644 include/nvmem.h -- 2.35.1.1320.gc452695387.dirty

3 21

[PATCH 00/17] imx: imx8m: clean up wdog code
by Peng Fan (OSS) 05 May '22

05 May '22

From: Peng Fan <peng.fan(a)nxp.com> Enable pinctrl wdog to clean up board level code imx_watchdog.c already has function of set_wdog_reset, so after watchdog driver enabled, no need that. Note: I only have NXP EVK board, so please help test if possible. Based on: https://patchwork.ozlabs.org/project/uboot/cover/20220430124317.17382-1-pen… Peng Fan (17): imx: imx8mn_evk: enable pinctrl_wdog in SPL imx: imx8mm_evk: enable pinctrl_wdog in SPL imx: imx8mp_evk: enable pinctrl_wdog in SPL imx: imx8mm_beacon: enable pinctrl_wdog in SPL imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL imx: imx8mm-data-modul-edm-sbc: enable pinctrl_wdog in SPL imx: engicam-imx8mm: drop unused macro imx: imx8mm-mx8menlo: drop unneeded watchdog settings imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL imx: imx8mn-beacon: enable pinctrl_wdog in SPL imx: imx8mn_smm_s2: clean up board watchdog code imx: imx8mn_var_som: clean up board watchdog code imx: imx8mp_rsb7320a1: enable wdog driver model in SPL imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL imx: phycore_imx8mm/p: clean up board watchdog code imx: verdin-imx8mm/p: cleanup board watchdog code imx: toradex/verdin-imx8mm/p: cleanup board watchdog code arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4 +++ .../dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-data-modul-edm-sbc.dts | 9 ++++++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 8 +++++ arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4 +++ .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12 -------- board/beacon/imx8mm/spl.c | 19 ------------ board/beacon/imx8mn/spl.c | 10 ------- board/bsh/imx8mn_smm_s2/spl.c | 11 ------- board/compulab/imx8mm-cl-iot-gate/spl.c | 19 ------------ board/data_modul/imx8mm_edm_sbc/spl.c | 17 ----------- board/engicam/imx8mm/spl.c | 2 -- board/freescale/imx8mm_evk/spl.c | 19 ------------ board/freescale/imx8mn_evk/spl.c | 19 ------------ board/freescale/imx8mp_evk/imx8mp_evk.c | 17 ----------- board/freescale/imx8mp_evk/spl.c | 2 -- board/gateworks/venice/spl.c | 30 ------------------- board/kontron/sl-mx8mm/spl.c | 18 ----------- board/menlo/mx8menlo/mx8menlo.c | 12 -------- board/phytec/phycore_imx8mm/spl.c | 19 ------------ board/phytec/phycore_imx8mp/spl.c | 19 ------------ board/toradex/verdin-imx8mm/spl.c | 11 ------- board/toradex/verdin-imx8mp/verdin-imx8mp.c | 11 ------- board/variscite/imx8mn_var_som/spl.c | 11 ------- configs/imx8mp_evk_defconfig | 1 - 33 files changed, 61 insertions(+), 279 deletions(-) -- 2.36.0

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[PATCH V2 0/4] imx: imx8m: simplify code with a common header file
by Peng Fan (OSS) 05 May '22

05 May '22

From: Peng Fan <peng.fan(a)nxp.com> V2: write a cover-letter Typo fix Add T-b tags Peng Fan (4): configs: imx8m: use common imx8m.h for i.MX8MM configs: imx8m: use common imx8m.h for i.MX8MN configs: imx8m: use common imx8m.h for i.MX8MP configs: imx8m: use common imx8m.h for i.MX8MQ include/configs/imx8m.h | 57 +++++++++++++++++++++ include/configs/imx8mm-cl-iot-gate.h | 17 +----- include/configs/imx8mm_beacon.h | 21 +------- include/configs/imx8mm_data_modul_edm_sbc.h | 15 ++---- include/configs/imx8mm_evk.h | 21 +------- include/configs/imx8mm_icore_mx8mm.h | 20 +------- include/configs/imx8mm_venice.h | 18 +------ include/configs/imx8mn_bsh_smm_s2_common.h | 17 +----- include/configs/imx8mn_evk.h | 20 +------- include/configs/imx8mn_var_som.h | 15 +----- include/configs/imx8mn_venice.h | 18 +------ include/configs/imx8mp_evk.h | 17 +----- include/configs/imx8mp_rsb3720.h | 16 +----- include/configs/imx8mp_venice.h | 18 +------ include/configs/imx8mq_cm.h | 24 +-------- include/configs/imx8mq_evk.h | 19 +------ include/configs/imx8mq_phanbell.h | 19 +------ include/configs/kontron-sl-mx8mm.h | 14 +---- include/configs/kontron_pitx_imx8m.h | 19 +------ include/configs/phycore_imx8mm.h | 20 +------- include/configs/phycore_imx8mp.h | 16 +----- include/configs/pico-imx8mq.h | 20 +------- include/configs/verdin-imx8mm.h | 20 +------- include/configs/verdin-imx8mp.h | 16 +----- 24 files changed, 85 insertions(+), 392 deletions(-) create mode 100644 include/configs/imx8m.h -- 2.36.0

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