April 2022 - U-Boot

[PATCH v2 1/2] imx8mn_ddr4_evk: Add USB Mass Storage support
by Fabio Estevam 21 Apr '22

21 Apr '22

From: Fabio Estevam <festevam(a)denx.de> Add USB Mass Storage support, which is a convenient way to flash the eMMC card, for example. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Changes since v1: - None configs/imx8mn_ddr4_evk_defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 917cdb5aa9d9..065f7392b706 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -82,4 +84,14 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y -- 2.25.1

2 2

[PATCH 1/2] imx8mn_ddr4_evk: Add USB Mass Storage support
by Fabio Estevam 21 Apr '22

21 Apr '22

From: Fabio Estevam <festevam(a)denx.de> Add USB Mass Storage support, which is a convenient way to flash the eMMC card, for example. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- configs/imx8mn_ddr4_evk_defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 917cdb5aa9d9..065f7392b706 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -82,4 +84,14 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y -- 2.25.1

5 15

[PATCH v4] bosch: Add initial board support for ACC
by Philip Oberfichtner 21 Apr '22

21 Apr '22

The Bosch ACC (Air Center Control) Board is based on the i.MX6D. Signed-off-by: Philip Oberfichtner <pro(a)denx.de> --- Changes in v4: - Remove obsolete CONFIG_FEC #defines - Sync device tree with Linux Changes in v3: - Rename acc to bosch-acc - Sync device tree with Linux Changes in v2: - Adapt defconfig and device tree to new bootcount driver - Clean up CONFIG_ENV_FLAGS_LIST_STATIC - Fix style issues in device trees - Migrate CONFIG options to Kconfig This board supports depends on: - "Add pmic bootcount driver", patchwork id 291027 - "crypto/fsl: Fallback to SW sha1/256 is misaligned buffers", patchwork id 270524 - Linux Device Tree patch, see below The Device Tree is currently being mainlined into Linux. The DT in this board support patch will be kept in sync as the DT patch for Linux evolves. The Linux patch is tracked under https://lore.kernel.org/linux-devicetree/20220421122619.1913496-2-pro@denx.… The only difference compared to the Linux DT is the removal of usbphynop properties. They are defined in the Linux version of imx6qdl.dtsi, but not in the u-boot version. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi | 80 ++ arch/arm/dts/imx6q-bosch-acc.dts | 967 +++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 15 + board/bosch/acc/Kconfig | 19 + board/bosch/acc/MAINTAINERS | 9 + board/bosch/acc/Makefile | 6 + board/bosch/acc/acc.c | 755 ++++++++++++++++++ configs/imx6q_bosch_acc_defconfig | 110 +++ include/configs/imx6q-bosch-acc.h | 122 +++ 10 files changed, 2084 insertions(+) create mode 100644 arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-bosch-acc.dts create mode 100644 board/bosch/acc/Kconfig create mode 100644 board/bosch/acc/MAINTAINERS create mode 100644 board/bosch/acc/Makefile create mode 100644 board/bosch/acc/acc.c create mode 100644 configs/imx6q_bosch_acc_defconfig create mode 100644 include/configs/imx6q-bosch-acc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 644ba961a2..418e0ee655 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -768,6 +768,7 @@ endif ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),) dtb-y += \ imx6-apalis.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi new file mode 100644 index 0000000000..37c182d318 --- /dev/null +++ b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* Copyright (C) 2022 Denx Software Engineering GmbH + * Philip Oberfichtner <pro(a)denx.de> + */ + +/ { + chosen { + stdout-path = &uart2; + }; + + soc { + u-boot,dm-spl; + + bus@2000000 { + u-boot,dm-spl; + + spba-bus@2000000 { + u-boot,dm-spl; + }; + }; + + bus@2100000 { + u-boot,dm-spl; + }; + }; + + bootcount { + compatible = "u-boot,bootcount-pmic"; + pmic = <&pmic>; + }; +}; + +&uart1 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc4 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6q-bosch-acc.dts b/arch/arm/dts/imx6q-bosch-acc.dts new file mode 100644 index 0000000000..9a05175536 --- /dev/null +++ b/arch/arm/dts/imx6q-bosch-acc.dts @@ -0,0 +1,967 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs(a)denx.de> + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus(a)denx.de> + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker(a)bosch.com> + * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro(a)denx.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + serial0 = &uart2; + serial1 = &uart1; + + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + /* eMMC is connected to USDHC interface 4, but shall get the name 0 */ + mmc0 = &usdhc4; + /* SC-Cards is connected to USDHC interface 2, but shall get the name 1 */ + mmc1 = &usdhc2; + }; + + backlight { + compatible = "pwm-backlight"; + /* The last value is the PWM period in nano-seconds! + * -> 5 kHz = 200 µS = 200.000 ns + */ + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <&reg_lcd0_pwr>; + }; + + refclk: refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + /* Override operating points with board-specific values */ + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_red: led-0 { + color = <LED_COLOR_ID_RED>; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: led-1 { + color = <LED_COLOR_ID_WHITE>; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + led-2 { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 18 0>; + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + supply_5P0: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "5P0"; + }; + + supply_VIN: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + reg_usb_otg_vbus: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + supply_VSNVS_3V0: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + reg_lcd0_pwr: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_usb_h2_vbus: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&supply_5P0> ; + regulator-always-on; + }; + + supply_vref_dac: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <&supply_5P0> ; + regulator-boot-on; + }; + + supply_sw4_3V3: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + supply_SYS_4V2: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + soc { + aips1: bus@2000000 {}; + }; +}; + +&reg_arm { + vin-supply = <&pmic_sw2>; +}; + +&reg_soc { + vin-supply = <&pmic_sw1abc>; +}; + +&reg_vdd1p1 { + vin-supply = <&supply_VSNVS_3V0>; +}; + +&reg_vdd2p5 { + vin-supply = <&supply_VSNVS_3V0>; +}; + +&reg_vdd3p0 { + vin-supply = <&supply_VSNVS_3V0>; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <&supply_sw4_3V3>; + phy-handle = <&ethphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + lm75: sensor@49 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + + compatible = "national,lm75b"; + reg = <0x49>; + }; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + /* + * VDD_CORE is connected to SW1 ABC + * We need to define sw1ab and sw1c, but later it is controlled solely with + * sw1c and therefore only this is named "VDD_SOC". + * See PMIC datasheet Rev. 18, chapter 6.4.4.3.1: "The feedback and all + * other controls are accomplished by use of pin SW1CFB and SW1C control + * registers, respectively." + * Setting min and max according to SOC datasheet + */ + pmic_sw1abc: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + + default-voltage = <1300000>; + }; + + pmic_sw2: sw2 { + regulator-name = "VDD_ARM (sw2)"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + + default-voltage = <1300000>; + }; + + pmic_sw3a: sw3a { + /* U-Boot sets correct voltage, shall not be touched by the OS */ + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + supply_DDR_1V5: sw3b { + /* U-Boot sets correct voltage, shall not be touched by the OS */ + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + supply_AUX_3V15: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + + default-voltage = <3150000>; + + }; + + swbst_reg: swbst { + status = "disabled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + + default-voltage = <3000000>; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + + default-voltage = <675000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + + default-voltage = <1500000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + + default-voltage = <1200000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + default-voltage = <2500000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + default-voltage = <1800000>; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + default-voltage = <2800000>; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + default-voltage = <2800000>; + }; + + }; + }; + + rtc: rtc@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + eeprom_ext: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + exc3000: touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + + usb3503: usb@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + + compatible = "smsc,usb3503"; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + + clocks = <&refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + vcnl4035: light-sensor@60 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + compatible = "vishay,vcnl4035"; + reg = <0x60>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x110b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001B098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001B098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001B098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpio_export_gpio_fixed_in: pinctrl-gpio-export-gpio-fixed-in-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* CLEAR ALL */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* DIG_IN_1 */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x80000000 /* DIG_IN_2 */ + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x80000000 /* PoE */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x80000000 /* PoE T2P */ + >; + }; + + pinctrl_reset_gpio_led: pinctrl-reset-gpio-led-pin { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000 + >; + }; + + pinctrl_gpio_export_gpio_fixed_out: pinctrl-gpio-export-gpio-fixed-out-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x0001B0B0 /* DIG_OUT_1 */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x0001B0B0 /* DIG_OUT_2 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0001B0B0 /* nUART_RESET */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0001B0B0 /* nETH1_RESET */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0001B0B0 /* nETH2_RESET */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001B0B0 /* RS485#1_PWR */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0001B0B0 /* RS485#2_PWR */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0001B0B0 /* RS485#3_PWR */ + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0001B0B0 /* RS485#4_PWR */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x0001B0B0 /* FEC_RESET_B */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001B0B0 /* AN_IN_PWR */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001B0B0 /* AN_OUT_PWR */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001B0B0 /* nUSBH1_PWR */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* not used SD2 and SD3 pins */ + /* [HYS 1] [100K PU] [PU] [PU EN] [CMOS] [Med. Speed] [40R] [Slow SR] */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x0001B0B0 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x0001B0B0 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0000B0B1 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x0001B0B0 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x0001B0B0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001B0B0 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0000B0B1 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0001B0B0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B8B1 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B8B1 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x000138B1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x80000000 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + /* NO SRE | 130 Ohm | SPEED LOW | Open Drain | PKE | PUE | 100k PU | HYS */ + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x80000000 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x80000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000 + >; + }; + + pinctrl_lcd_enable: lcdenablerp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 + >; + }; + + pinctrl_pfid_0_2: pfid-0-2-grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B0B0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B0B0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001B0B0 + >; + }; + + pinctrl_pfid_3_4: pfid-3-4-grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001B0B0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0001B0B0 + >; + }; + + pinctrl_pfid_5_7: pfid-5-7-grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0001B0B0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001B0B0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001B0B0 + >; + }; + + pinctrl_pfid_8_9: pfid-8-9-grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001B0B0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001B0B0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + /* PROXIMITY_INT */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001B0B0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001B0B0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001B0B0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + /* 47K Pull-Up, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: pinctrl_usb3503-grp { + fsl,pins = < + /* USB Hub REFCLK - No pull-up/pull-down, CMOS output, low speed, 90 Ohm */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001B0B0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + /* CMD and DATA0..3 have external pull-up, CLK does not need a pull-up. + * CLK signal is half the speed than the others (52 MHz compared to 104 MHz) + */ + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001B0B0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + /* CMD has external pull-up, DATA0..7 within eMMC, CLK does not need a pull-up. + * CLK signal is half the speed than the others (52 MHz compared to 104 MHz) + */ + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + display-timings { + native-mode = <&lvds0_timing0>; + lvds0_timing0: timing0 { + clock-frequency = <79479000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pmu { + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sdma { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + iram = <&ocram>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + + rts-gpios = <&gpio7 8 0>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <&reg_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + status = "okay"; + + vbus-supply = <&reg_usb_h2_vbus>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen2_reg>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; + + vbus-supply = <&reg_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; +}; + +/* sdcard */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + status = "okay"; + + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + voltage-ranges = <3300 3300>; + vmmc-supply = <&supply_sw4_3V3>; + fsl,wp-controller; +}; + +/* emmc */ +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; + + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <&supply_sw4_3V3>; + fsl,wp-controller; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; + timeout-sec=<10>; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 98df4d4e42..995b4b2426 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -345,6 +345,20 @@ config TARGET_MX6Q_ENGICAM select SUPPORT_SPL imply CMD_DM +config TARGET_MX6Q_ACC + bool "Support for Bosch ACC board" + depends on MX6QDL + select BOARD_LATE_INIT + select OF_CONTROL + select SPL_OF_LIBFDT + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6SABREAUTO bool "mx6sabreauto" depends on MX6QDL @@ -674,6 +688,7 @@ source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" +source "board/bosch/acc/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pcl063/Kconfig" diff --git a/board/bosch/acc/Kconfig b/board/bosch/acc/Kconfig new file mode 100644 index 0000000000..da54d96e40 --- /dev/null +++ b/board/bosch/acc/Kconfig @@ -0,0 +1,19 @@ +if TARGET_MX6Q_ACC + +config SYS_VENDOR + default "bosch" + +config SYS_BOARD + default "acc" + +config SYS_CONFIG_NAME + default "imx6q-bosch-acc" + +config SYS_BOOT_EMMC + bool "Boot from EMMC" + default y + help + Say N here if you want to boot from SD card or microUSB. + Say Y to boot from eMMC. + +endif diff --git a/board/bosch/acc/MAINTAINERS b/board/bosch/acc/MAINTAINERS new file mode 100644 index 0000000000..1b88003712 --- /dev/null +++ b/board/bosch/acc/MAINTAINERS @@ -0,0 +1,9 @@ +MX6Q_ACC +M: Matthias Winker <matthias.winker(a)de.bosch.com> +M: Philip Oberfichtner <pro(a)denx.de> +S: Maintained +F: board/bosch/acc +F: include/configs/imx6q-bosch-acc.h +F: configs/imx6q_bosch_acc_defconfig +F: arch/arm/dts/imx6q-bosch-acc.dts +F: arch/arm/dts/imx6q-bosch-acc-u-boot.dts diff --git a/board/bosch/acc/Makefile b/board/bosch/acc/Makefile new file mode 100644 index 0000000000..d425a677bc --- /dev/null +++ b/board/bosch/acc/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2017 +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := acc.o diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c new file mode 100644 index 0000000000..dbc03c9371 --- /dev/null +++ b/board/bosch/acc/acc.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs(a)denx.de> + * Copyright (c) 2019 Bosch Thermotechnik GmbH + * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro(a)denx.de> + */ + +#include <common.h> +#include <bootstage.h> +#include <dm.h> +#include <dm/platform_data/serial_mxc.h> +#include <dm/device-internal.h> +#include <env.h> +#include <env_internal.h> +#include <hang.h> +#include <init.h> +#include <linux/delay.h> +#include <mmc.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <usb.h> +#include <usb/ehci-ci.h> +#include <fuse.h> + +#include <watchdog.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_ACC_PLAT_DETECT IMX_GPIO_NR(5, 9) +#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0) +#define GPIO_BUZZER IMX_GPIO_NR(1, 18) +#define GPIO_LAN1_RESET IMX_GPIO_NR(4, 27) +#define GPIO_LAN2_RESET IMX_GPIO_NR(4, 19) +#define GPIO_LAN3_RESET IMX_GPIO_NR(4, 18) +#define GPIO_USB_HUB_RESET IMX_GPIO_NR(5, 5) +#define GPIO_EXP_RS485_RESET IMX_GPIO_NR(4, 16) +#define GPIO_TOUCH_RESET IMX_GPIO_NR(1, 20) + +#define BOARD_INFO_MAGIC 0x19730517 + +struct board_info { + int magic; + int board; + int rev; +}; + +static struct board_info *detect_board(void); + +#define PFID_BOARD_ACC 0xe + +static const char * const name_board[] = { + [PFID_BOARD_ACC] = "ACC", +}; + +#define PFID_REV_22 0x8 +#define PFID_REV_21 0x9 +#define PFID_REV_20 0xa +#define PFID_REV_14 0xb +#define PFID_REV_13 0xc +#define PFID_REV_12 0xd +#define PFID_REV_11 0xe +#define PFID_REV_10 0xf + +static const char * const name_revision[] = { + [0 ... PFID_REV_10] = "Unknown", + [PFID_REV_10] = "1.0", + [PFID_REV_11] = "1.1", + [PFID_REV_12] = "1.2", + [PFID_REV_13] = "1.3", + [PFID_REV_14] = "1.4", + [PFID_REV_20] = "2.0", + [PFID_REV_21] = "2.1", + [PFID_REV_22] = "2.2", +}; + +/* + * NXP Reset Default: 0x0001B0B0 + * - Schmitt trigger input (PAD_CTL_HYS) + * - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP) + * - Pull Enabled (PAD_CTL_PUE) + * - Pull/Keeper Enabled (PAD_CTL_PKE) + * - CMOS output (No PAD_CTL_ODE) + * - Medium Speed (PAD_CTL_SPEED_MED) + * - 40 Ohm drive strength (PAD_CTL_DSE_40ohm) + * - Slow (PAD_CTL_SRE_SLOW) + */ + +/* Input, no pull up/down: 0x0x000100B0 */ +#define GPIN_PAD_CTRL (PAD_CTL_HYS \ + | PAD_CTL_SPEED_MED \ + | PAD_CTL_DSE_40ohm \ + | PAD_CTL_SRE_SLOW) + +/* Input, pull up: 0x0x0001B0B0 */ +#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \ + | PAD_CTL_PUS_100K_UP \ + | PAD_CTL_PUE \ + | PAD_CTL_PKE \ + | PAD_CTL_SPEED_MED \ + | PAD_CTL_DSE_40ohm \ + | PAD_CTL_SRE_SLOW) + +/* Input, pull down: 0x0x000130B0 */ +#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \ + | PAD_CTL_PUS_100K_DOWN \ + | PAD_CTL_PUE \ + | PAD_CTL_PKE \ + | PAD_CTL_SPEED_MED \ + | PAD_CTL_DSE_40ohm \ + | PAD_CTL_SRE_SLOW) + +static const iomux_v3_cfg_t board_detect_pads[] = { + /* Platform detect */ + IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* RAM Volt detect */ + IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* PFID 0..9 */ + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* Manufacturer */ + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* Redundant */ + IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL)) +}; + +static int gpio_acc_pfid[] = { + IMX_GPIO_NR(2, 0), + IMX_GPIO_NR(2, 1), + IMX_GPIO_NR(2, 2), + IMX_GPIO_NR(2, 3), + IMX_GPIO_NR(2, 4), + IMX_GPIO_NR(6, 14), + IMX_GPIO_NR(6, 15), + IMX_GPIO_NR(2, 5), + IMX_GPIO_NR(2, 6), + IMX_GPIO_NR(2, 7), + IMX_GPIO_NR(6, 16), + IMX_GPIO_NR(5, 4), +}; + +static int init_gpio(int nr) +{ + int ret; + + ret = gpio_request(nr, ""); + if (ret != 0) { + printf("Could not request gpio nr: %d\n", nr); + hang(); + } + ret = gpio_direction_input(nr); + if (ret != 0) { + printf("Could not set gpio nr: %d to input\n", nr); + hang(); + } + return 0; +} + +/* + * We want to detect the board type only once in SPL, + * so we store the board_info struct at beginning in IRAM. + * + * U-Boot itself can read it also, and do not need again + * to detect board type. + * + */ +static struct board_info *detect_board(void) +{ + struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR; + int i; + + if (binfo->magic == BOARD_INFO_MAGIC) + return binfo; + + puts("Board: "); + SETUP_IOMUX_PADS(board_detect_pads); + init_gpio(GPIO_ACC_PLAT_DETECT); + if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) { + puts("not supported"); + hang(); + } else { + puts("Bosch "); + } + + for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++) + init_gpio(gpio_acc_pfid[i]); + + binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 | + gpio_get_value(gpio_acc_pfid[1]) << 1 | + gpio_get_value(gpio_acc_pfid[2]) << 2 | + gpio_get_value(gpio_acc_pfid[11]) << 3; + printf("%s ", name_board[binfo->board]); + + binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 | + gpio_get_value(gpio_acc_pfid[8]) << 1 | + gpio_get_value(gpio_acc_pfid[9]) << 2 | + gpio_get_value(gpio_acc_pfid[10]) << 3; + printf("rev: %s\n", name_revision[binfo->rev]); + + binfo->magic = BOARD_INFO_MAGIC; + + return binfo; +} + +static void unset_early_gpio(void) +{ + init_gpio(GPIO_LAN1_RESET); + init_gpio(GPIO_LAN2_RESET); + init_gpio(GPIO_LAN3_RESET); + init_gpio(GPIO_USB_HUB_RESET); + init_gpio(GPIO_EXP_RS485_RESET); + init_gpio(GPIO_TOUCH_RESET); + + gpio_set_value(GPIO_LAN1_RESET, 1); + gpio_set_value(GPIO_LAN2_RESET, 1); + gpio_set_value(GPIO_LAN3_RESET, 1); + gpio_set_value(GPIO_USB_HUB_RESET, 1); + gpio_set_value(GPIO_EXP_RS485_RESET, 1); + gpio_set_value(GPIO_TOUCH_RESET, 1); +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_MMC; + + switch (prio) { + case 0: + return ENVL_NOWHERE; + + case 1: + return ENVL_MMC; + } + + return ENVL_UNKNOWN; +} + +int board_late_init(void) +{ + struct board_info *binfo = detect_board(); + + switch (binfo->board) { + case PFID_BOARD_ACC: + env_set("bootconf", "conf-imx6q-bosch-acc.dtb"); + break; + default: + printf("Unknown board %d\n", binfo->board); + break; + } + + unset_early_gpio(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +/* Early + * - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an + * external pull-down resistor) + * - Touch clean reset on every boot + * - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init + */ +static const iomux_v3_cfg_t early_pads[] = { + IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */ + IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */ + IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */ + IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */ + IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */ + IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */ + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */ +}; + +static void setup_iomux_early(void) +{ + SETUP_IOMUX_PADS(early_pads); +} + +static void set_early_gpio(void) +{ + init_gpio(GPIO_BUZZER); + init_gpio(GPIO_LAN1_RESET); + init_gpio(GPIO_LAN2_RESET); + init_gpio(GPIO_LAN3_RESET); + init_gpio(GPIO_USB_HUB_RESET); + init_gpio(GPIO_EXP_RS485_RESET); + init_gpio(GPIO_TOUCH_RESET); + + /* Reset signals are active low */ + gpio_set_value(GPIO_BUZZER, 0); + gpio_set_value(GPIO_LAN1_RESET, 0); + gpio_set_value(GPIO_LAN2_RESET, 0); + gpio_set_value(GPIO_LAN3_RESET, 0); + gpio_set_value(GPIO_USB_HUB_RESET, 0); + gpio_set_value(GPIO_EXP_RS485_RESET, 0); + gpio_set_value(GPIO_TOUCH_RESET, 0); +} + +/* UART */ +#define UART_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#undef UART_PAD_CTRL +#define UART_PAD_CTRL 0x1b0b1 +static const iomux_v3_cfg_t uart2_pads[] = { + IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart2_pads); +} + +void spl_board_init(void) +{ +} + +static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = { + .dram_sdclk_0 = 0x00008038, + .dram_sdclk_1 = 0x00008038, + .dram_cas = 0x00008028, + .dram_ras = 0x00008028, + .dram_reset = 0x00000028, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00008000, + .dram_sdodt0 = 0x00000028, + .dram_sdodt1 = 0x00000028, + .dram_sdqs0 = 0x00008038, + .dram_sdqs1 = 0x00008038, + .dram_sdqs2 = 0x00008038, + .dram_sdqs3 = 0x00008038, + .dram_sdqs4 = 0x00008038, + .dram_sdqs5 = 0x00008038, + .dram_sdqs6 = 0x00008038, + .dram_sdqs7 = 0x00008038, + .dram_dqm0 = 0x00008038, + .dram_dqm1 = 0x00008038, + .dram_dqm2 = 0x00008038, + .dram_dqm3 = 0x00008038, + .dram_dqm4 = 0x00008038, + .dram_dqm5 = 0x00008038, + .dram_dqm6 = 0x00008038, + .dram_dqm7 = 0x00008038, +}; + +static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000028, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000038, + .grp_b1ds = 0x00000038, + .grp_b2ds = 0x00000038, + .grp_b3ds = 0x00000038, + .grp_b4ds = 0x00000038, + .grp_b5ds = 0x00000038, + .grp_b6ds = 0x00000038, + .grp_b7ds = 0x00000038, +}; + +static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = { + .p0_mpwldectrl0 = 0x0020001F, + .p0_mpwldectrl1 = 0x00280021, + .p1_mpwldectrl0 = 0x00120028, + .p1_mpwldectrl1 = 0x000D001F, + .p0_mpdgctrl0 = 0x43340342, + .p0_mpdgctrl1 = 0x03300325, + .p1_mpdgctrl0 = 0x4334033E, + .p1_mpdgctrl1 = 0x03280270, + .p0_mprddlctl = 0x46373B3E, + .p1_mprddlctl = 0x3B383544, + .p0_mpwrdlctl = 0x36383E40, + .p1_mpwrdlctl = 0x4030433A, +}; + +/* Micron MT41K128M16JT-125 (standard - 1600,CL=11) + * !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!! + * So this setting is actually invalid! + * +static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + */ + +/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E) + * Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss + * width set to 64, as four chips are used on acc (4 * 16 = 64) + */ +static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = { + .mem_speed = 1066, + .density = 2, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1313, // 13.125ns + .trcmin = 5063, // 50.625ns + .trasmin = 3750, // 37.5ns + .SRT = 0, // Set to 1 for temperatures above 85°C +}; + +static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = { + .ddr_type = DDR_TYPE_DDR3, + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + .cs_density = 32, /* 32Gb per CS */ + .ncs = 1, /* single chip select */ + .cs1_mirror = 0, + .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x33, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x33, /* 33 cycles, 500us (JEDEC default) */ +}; + +#define ACC_SPREAD_SPECTRUM_STOP 0x0fa +#define ACC_SPREAD_SPECTRUM_STEP 0x001 +#define ACC_SPREAD_SPECTRUM_DENOM 0x190 + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Turn clocks on/off */ + writel(0x00C0000F, &ccm->CCGR0); + writel(0x0030FC00, &ccm->CCGR1); + writel(0x03FF0033, &ccm->CCGR2); + writel(0x3FF3300F, &ccm->CCGR3); + writel(0x0003C300, &ccm->CCGR4); + writel(0x0F3000C3, &ccm->CCGR5); + writel(0x00000FFF, &ccm->CCGR6); + + /* Enable spread spectrum */ + writel(BM_ANADIG_PLL_528_SS_ENABLE | + BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) | + BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP), + &ccm->analog_pll_528_ss); + + writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM), + &ccm->analog_pll_528_denom); +} + +/* MMC board initialization is needed till adding DM support in SPL */ +#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC) +#include <mmc.h> +#include <fsl_esdhc_imx.h> + +static const iomux_v3_cfg_t usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)), /* CD */ +}; + +static const iomux_v3_cfg_t usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 1, 4}, + {USDHC4_BASE_ADDR, 1, 8}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + detect_board(); + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC4_BASE_ADDR: + return 1; /* eMMC always present */ + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + gpio_direction_input(USDHC2_CD_GPIO); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 boot_dev = BOOT_DEVICE_MMC1; + + detect_board(); + + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC1 */ + if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) { + /* + * boot from SD is not allowed, if boot from eMMC is + * configured. + */ + puts("SD boot not allowed\n"); + spl_boot_list[0] = BOOT_DEVICE_NONE; + return; + } + + boot_dev = BOOT_DEVICE_MMC1; + break; + + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC */ + boot_dev = BOOT_DEVICE_MMC2; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + printf("Wrong board boot order\n"); + break; + } + + spl_boot_list[0] = boot_dev; +} + +static void setup_ddr(void) +{ + struct board_info *binfo = detect_board(); + + switch (binfo->rev) { + case PFID_REV_20: + case PFID_REV_21: + case PFID_REV_22: + default: + /* Rev 2 board has i.MX6 Dual with 64-bit RAM */ + mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width, + &acc_mx6d_ddr_ioregs, + &acc_mx6d_grp_ioregs); + mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib, + &acc_mx6d_mem_ddr3_1066); + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_write_level_calibration(&acc_mx6d_ddr_info); + mmdc_do_dqs_calibration(&acc_mx6d_ddr_info); + break; + } +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog power-down counter (only enabled after reset) */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* setup GP timer */ + timer_init(); + + /* Enable device tree and early DM support*/ + spl_early_init(); + + /* Setup early required pinmuxes */ + setup_iomux_early(); + set_early_gpio(); + + /* Setup UART pinmux */ + setup_iomux_uart(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + setup_ddr(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif + +#if IS_ENABLED(CONFIG_USB_EHCI_MX6) +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL BIT(9) + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, "imx6q-bosch-acc")) + return 0; + return -1; +} + +void reset_cpu(ulong addr) +{ + puts("Hanging CPU for watchdog reset!\n"); + hang(); +} + +#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS) +void show_boot_progress(int val) +{ + u32 fuseval; + int ret; + + if (val < 0) + val *= -1; + + switch (val) { + case BOOTSTAGE_ID_ENTER_CLI_LOOP: + printf("autoboot failed, check fuse\n"); + ret = fuse_read(0, 6, &fuseval); + if (ret == 0 && (fuseval & 0x2) == 0x0) { + printf("Enter cmdline, as device not closed\n"); + return; + } + ret = fuse_read(5, 7, &fuseval); + if (ret == 0 && fuseval == 0x0) { + printf("Enter cmdline, as it is a Development device\n"); + return; + } + panic("do not enter cmdline"); + break; + } +} +#endif diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig new file mode 100644 index 0000000000..3c02f0f5dd --- /dev/null +++ b/configs/imx6q_bosch_acc_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17780000 +CONFIG_SYS_MALLOC_LEN=0x01000000 +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x1fe000 +CONFIG_MX6QDL=y +CONFIG_MX6_DDRCAL=y +CONFIG_TARGET_MX6Q_ACC=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-bosch-acc" +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=8 +CONFIG_SPL_SIZE_LIMIT=69632 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x1ff000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_BMODE is not set +# CONFIG_CMD_DEKBLOB is not set +CONFIG_BUILD_TARGET="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run mmc_mmc_fit" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa +# CONFIG_SPL_CRC32 is not set +# CONFIG_SPL_CRYPTO is not set +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_FUSE is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_SLEEP is not set +# CONFIG_CMD_MP is not set +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT4=y +CONFIG_DOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_VERSION_VARIABLE=y +CONFIG_TFTP_BLOCKSIZE=512 +CONFIG_SPL_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +CONFIG_EXT4_WRITE=y +CONFIG_FS_FAT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h new file mode 100644 index 0000000000..6d362557ac --- /dev/null +++ b/include/configs/imx6q-bosch-acc.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs(a)denx.de> + * Copyright (c) 2019 Bosch Thermotechnik GmbH + * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro(a)denx.de> + */ + +#ifndef __IMX6Q_ACC_H +#define __IMX6Q_ACC_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +#ifdef CONFIG_SYS_BOOT_EMMC +#define MMC_ROOTFS_DEV 0 +#define MMC_ROOTFS_PART 2 +#endif + +#ifdef CONFIG_SYS_BOOT_EMMC +/* eMMC Boot */ +#define ENV_EXTRA \ + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ + "fitpart=1\0" \ + "optargs=ro quiet systemd.gpt_auto=false\0" \ + "production=1\0" \ + "mmcautodetect=yes\0" \ + "mmcrootfstype=ext4\0" \ + "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \ + "mmcargs=run finduuid; setenv bootargs " \ + "root=PARTUUID=${uuid} ${optargs} rootfstype=${mmcrootfstype}\0" \ + "mmc_mmc_fit=run env_persist; run setbm; run mmcloadfit; " \ + "run auth_fit_or_reset; run mmcargs addcon; " \ + "bootm ${fit_addr}#${bootconf}\0" \ + "bootset=0\0" \ + "setbm=if test ${bootset} -eq 1; " \ + "then setenv mmcpart 4; setenv fitpart 3; " \ + "else; setenv mmcpart 2; setenv fitpart 1; fi\0" \ + "handle_ustate=if test ${ustate} -eq 2; then setenv ustate 3; fi\0" \ + "switch_bootset=if test ${bootset} -eq 1; then setenv bootset 0; " \ + "else; setenv bootset 1;fi\0" \ + "env_persisted=0\0" \ + "env_persist=if test ${env_persisted} != 1; " \ + "then env set env_persisted 1; run save_env; fi;\0" \ + "save_env=env save; env save\0" \ + "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0" + +#define CONFIG_ENV_FLAGS_LIST_STATIC \ + "bootset:bw," \ + "clone_pending:bw," \ + "endurance_test:bw," \ + "env_persisted:bw," \ + "factory_reset:bw," \ + "fdtcontroladdr:xw," \ + "fitpart:dw," \ + "mmcpart:dw," \ + "production:bw," \ + "ustate:dw" + +#else +/* SD Card boot */ +#define ENV_EXTRA \ + "mmcdev=1\0" \ + "fitpart=1\0" \ + "rootpart=2\0" \ + "optargs=ro systemd.gpt_auto=false\0" \ + "finduuid=part uuid mmc ${mmcdev}:${rootpart} uuid\0" \ + "mmcargs=run finduuid;setenv bootargs root=PARTUUID=${uuid} ${optargs}\0" \ + "mmc_mmc_fit=run mmcloadfit; run auth_fit_or_reset; run mmcargs addcon; " \ + "bootm ${fit_addr}#${bootconf}\0" + +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootconf=conf-imx6q-bosch-acc.dtb\0"\ + "mmcfit_name=fitImage\0" \ + "mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \ + "auth_fit_or_reset=hab_auth_img ${fit_addr} ${filesize} || reset\0" \ + "console=ttymxc0\0" \ + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "fit_addr=19000000\0" \ + ENV_EXTRA + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* SPL */ +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#ifdef CONFIG_SYS_BOOT_EMMC + +/* Boot from eMMC */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 1 + +#else + +/* Boot from SD-card */ +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#endif + +#endif +#endif + +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ + +#endif /* __IMX6Q_ACC_H */ -- 2.34.1

1 0

[PATCH v3] bosch: Add initial board support for ACC
by Philip Oberfichtner 21 Apr '22

21 Apr '22

The Bosch ACC (Air Center Control) Board is based on the i.MX6D. Signed-off-by: Philip Oberfichtner <pro(a)denx.de> --- Changes in v3: - Rename acc to bosch-acc - Sync device tree with Linux Changes in v2: - Adapt defconfig and device tree to new bootcount driver - Clean up CONFIG_ENV_FLAGS_LIST_STATIC - Fix style issues in device trees - Migrate CONFIG options to Kconfig This board supports depends on: - "Add pmic bootcount driver", patchwork id 291027 - "crypto/fsl: Fallback to SW sha1/256 is misaligned buffers", patchwork id 270524 - Linux Device Tree patch, see below The Device Tree is currently being mainlined into Linux. The DT in this board support patch will be kept in sync as the DT patch for Linux evolves. The Linux patch is tracked under http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=294727 The only difference compared to the Linux DT is the removal of usbphynop properties. They are defined in the Linux version of imx6qdl.dtsi, but not in the u-boot version. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi | 80 ++ arch/arm/dts/imx6q-bosch-acc.dts | 1036 ++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 15 + board/bosch/acc/Kconfig | 19 + board/bosch/acc/MAINTAINERS | 9 + board/bosch/acc/Makefile | 6 + board/bosch/acc/acc.c | 755 ++++++++++++++++ configs/imx6q_bosch_acc_defconfig | 110 +++ include/configs/imx6q-bosch-acc.h | 128 +++ 10 files changed, 2159 insertions(+) create mode 100644 arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-bosch-acc.dts create mode 100644 board/bosch/acc/Kconfig create mode 100644 board/bosch/acc/MAINTAINERS create mode 100644 board/bosch/acc/Makefile create mode 100644 board/bosch/acc/acc.c create mode 100644 configs/imx6q_bosch_acc_defconfig create mode 100644 include/configs/imx6q-bosch-acc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 644ba961a2..418e0ee655 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -768,6 +768,7 @@ endif ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),) dtb-y += \ imx6-apalis.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi new file mode 100644 index 0000000000..37c182d318 --- /dev/null +++ b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* Copyright (C) 2022 Denx Software Engineering GmbH + * Philip Oberfichtner <pro(a)denx.de> + */ + +/ { + chosen { + stdout-path = &uart2; + }; + + soc { + u-boot,dm-spl; + + bus@2000000 { + u-boot,dm-spl; + + spba-bus@2000000 { + u-boot,dm-spl; + }; + }; + + bus@2100000 { + u-boot,dm-spl; + }; + }; + + bootcount { + compatible = "u-boot,bootcount-pmic"; + pmic = <&pmic>; + }; +}; + +&uart1 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc4 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6q-bosch-acc.dts b/arch/arm/dts/imx6q-bosch-acc.dts new file mode 100644 index 0000000000..d0f6ba0cc4 --- /dev/null +++ b/arch/arm/dts/imx6q-bosch-acc.dts @@ -0,0 +1,1036 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs(a)denx.de> + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus(a)denx.de> + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker(a)bosch.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + serial0 = &uart2; + serial1 = &uart1; + + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + /* eMMC is connected to USDHC interface 4, but shall get the name 0 */ + mmc0 = &usdhc4; + /* SC-Cards is connected to USDHC interface 2, but shall get the name 1 */ + mmc1 = &usdhc2; + }; + + backlight { + status = "okay"; + + compatible = "pwm-backlight"; + /* The last value is the PWM period in nano-seconds! + * -> 5 kHz = 200 µS = 200.000 ns + */ + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <&reg_lcd0_pwr>; + }; + + usb3503_refclk: usb3503_refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + /* Override operating points with board-specific values */ + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + leds { + compatible = "pwm-leds"; + + led_red: red { + label = "red"; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: white { + label = "white"; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators: regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + supply_5P0: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "5P0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + supply_VIN: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + supply_VSNVS_3V0: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + reg_lcd0_pwr: regulator-lcd0-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_usb_h2_vbus: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&supply_5P0> ; + regulator-always-on; + }; + + supply_vref_dac: vref_dac { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <&supply_5P0> ; + regulator-boot-on; + }; + }; + + reset_gpio_led { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + reset { + label = "red_reset"; + gpios = <&gpio5 18 0>; + default-state = "off"; + }; + }; + + soc { + aips1: bus@2000000 {}; + }; +}; + +&reg_arm { + vin-supply = <&pmic_sw2>; +}; + +&reg_soc { + vin-supply = <&pmic_sw1abc>; +}; + +&reg_vdd1p1 { + vin-supply = <&supply_VSNVS_3V0>; +}; + +&reg_vdd2p5 { + vin-supply = <&supply_VSNVS_3V0>; +}; + +&reg_vdd3p0 { + vin-supply = <&supply_VSNVS_3V0>; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <&supply_sw4_3V3>; + phy-handle = <&ethphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + bytelen = <4096>; + bus-id = <0>; + flags = <0x80>; /* AT24_FLAG_ADDR16 */ + }; + + lm75: lm75@49 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + + compatible = "national,lm75b"; + reg = <0x49>; + + interrupts = <7 0x4>; + interrupt-parent = <&gpio4>; + }; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + uboot,bootcounter; + + VGEN1-supply = <&supply_AUX_3V15>; + VGEN2-supply = <&supply_AUX_3V15>; + VGEN3-supply = <&supply_sw4_3V3>; + VGEN4-supply = <&supply_sw4_3V3>; + VGEN5-supply = <&supply_SYS_4V2>; + VGEN6-supply = <&supply_SYS_4V2>; + + VREFDDR-supply = <&supply_DDR_1V5>; + + SW1AB-supply = <&supply_SYS_4V2>; + SW1C-supply = <&supply_SYS_4V2>; + SW2-supply = <&supply_SYS_4V2>; + SW3A-supply = <&supply_SYS_4V2>; + SW3B-supply = <&supply_SYS_4V2>; + SW4-supply = <&supply_SYS_4V2>; + + regulators { + /* + * VDD_CORE is connected to SW1 ABC + * We need to define sw1ab and sw1c, but later it is controlled solely with + * sw1c and therefore only this is named "VDD_SOC". + * See PMIC datasheet Rev. 18, chapter 6.4.4.3.1: "The feedback and all + * other controls are accomplished by use of pin SW1CFB and SW1C control + * registers, respectively." + * Setting min and max according to SOC datasheet + */ + pmic_sw1abc: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + + default-voltage = <1300000>; + }; + + pmic_sw2: sw2{ + regulator-name = "VDD_ARM (sw2)"; + + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + + default-voltage = <1300000>; + }; + + pmic_sw3a: sw3a { + /* U-Boot sets correct voltage, shall not be touched by the OS */ + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + supply_DDR_1V5: sw3b { + /* U-Boot sets correct voltage, shall not be touched by the OS */ + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + supply_AUX_3V15: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + + default-voltage = <3150000>; + + }; + + swbst_reg: swbst { + status = "disabled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + + default-voltage = <3000000>; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + + default-voltage = <675000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + + default-voltage = <1500000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + + default-voltage = <1200000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + default-voltage = <2500000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + default-voltage = <1800000>; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + default-voltage = <2800000>; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + default-voltage = <2800000>; + }; + + }; + }; + + rtc: rtcpcf8563@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + adc101c: ac101c@54 { + compatible = "ti,adc101c"; + reg = <0x54>; + status = "okay"; + vref-supply = <&supply_vref_dac>; + vcc-supply = <&supply_vref_dac>; + }; + + ad5602: ad5602@c { + compatible = "adi,ad5602"; + reg = <0x0c>; + status = "okay"; + vcc-supply = <&supply_vref_dac>; + }; + + eeprom_ext: eeprom_ext@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + bytelen = <4096>; + bus-id = <1>; + flags = <0x80>; /* AT24_FLAG_ADDR16 */ + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + exc3000: exc3000@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + + status = "okay"; + }; + + usb3503: usb3503@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + status = "okay"; + + compatible = "smsc,usb3503"; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + + clocks = <&usb3503_refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + vcnl4035: vcnl4035@60 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + compatible = "vishay,vcnl4035"; + reg = <0x60>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x110b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001B098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001B098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001B098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpio_export_gpio_fixed_in: pinctrl_gpio_export_gpio_fixed_in_grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* CLEAR ALL */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* DIG_IN_1 */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x80000000 /* DIG_IN_2 */ + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x80000000 /* PoE */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x80000000 /* PoE T2P */ + >; + }; + + pinctrl_reset_gpio_led: pinctrl_reset_gpio_led_pin { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000 + >; + }; + + pinctrl_gpio_export_gpio_fixed_out: pinctrl_gpio_export_gpio_fixed_out_grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x0001B0B0 /* DIG_OUT_1 */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x0001B0B0 /* DIG_OUT_2 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0001B0B0 /* nUART_RESET */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0001B0B0 /* nETH1_RESET */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0001B0B0 /* nETH2_RESET */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001B0B0 /* RS485#1_PWR */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0001B0B0 /* RS485#2_PWR */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0001B0B0 /* RS485#3_PWR */ + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0001B0B0 /* RS485#4_PWR */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x0001B0B0 /* FEC_RESET_B */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001B0B0 /* AN_IN_PWR */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001B0B0 /* AN_OUT_PWR */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001B0B0 /* nUSBH1_PWR */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* not used SD2 and SD3 pins */ + /* [HYS 1] [100K PU] [PU] [PU EN] [CMOS] [Med. Speed] [40R] [Slow SR] */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x0001B0B0 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x0001B0B0 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0000B0B1 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x0001B0B0 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x0001B0B0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001B0B0 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0000B0B1 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0001B0B0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B8B1 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B8B1 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x000138B1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x80000000 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + /* NO SRE | 130 Ohm | SPEED LOW | Open Drain | PKE | PUE | 100k PU | HYS */ + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x80000000 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x80000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000 + >; + }; + + pinctrl_lcd_enable: lcdenablerp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 + >; + }; + + pinctrl_pfid_0_2: pfid_0_2_grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B0B0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B0B0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001B0B0 + >; + }; + + pinctrl_pfid_3_4: pfid_3_4_grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001B0B0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0001B0B0 + >; + }; + + pinctrl_pfid_5_7: pfid_5_7_grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0001B0B0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001B0B0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001B0B0 + >; + }; + + pinctrl_pfid_8_9: pfid_8_9_grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001B0B0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001B0B0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + /* PROXIMITY_INT */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001B0B0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001B0B0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001B0B0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + /* 47K Pull-Up, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: pinctrl_usb3503-grp { + fsl,pins = < + /* USB Hub REFCLK - No pull-up/pull-down, CMOS output, low speed, 90 Ohm */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001B0B0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + /* CMD and DATA0..3 have external pull-up, CLK does not need a pull-up. + * CLK signal is half the speed than the others (52 MHz compared to 104 MHz) + */ + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001B0B0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + /* CMD has external pull-up, DATA0..7 within eMMC, CLK does not need a pull-up. + * CLK signal is half the speed than the others (52 MHz compared to 104 MHz) + */ + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&lvds0_timing0>; + lvds0_timing0: hsd100pxn1 { + clock-frequency = <79479000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pmu { + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; + linux,default-trigger = "heartbeat"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&regulators { + supply_sw4_3V3: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; + + supply_SYS_4V2: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <&supply_5P0>; + }; +}; + +&sdma { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + iram = <&ocram>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + + rts-gpios = <&gpio7 8 0>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <&reg_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + status = "okay"; + + vbus-supply = <&reg_usb_h2_vbus>; + osc-clkgate-delay = <0x3>; + + pad-supply = <&vgen2_reg>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; + + vbus-supply = <&reg_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; +}; + +/* sdcard */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + status = "okay"; + + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + voltage-ranges = <3300 3300>; + vmmc-supply = <&supply_sw4_3V3>; + fsl,wp-controller; +}; + +/* emmc */ +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; + + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <&supply_sw4_3V3>; + fsl,wp-controller; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; + timeout-sec=<10>; +}; + diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 98df4d4e42..995b4b2426 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -345,6 +345,20 @@ config TARGET_MX6Q_ENGICAM select SUPPORT_SPL imply CMD_DM +config TARGET_MX6Q_ACC + bool "Support for Bosch ACC board" + depends on MX6QDL + select BOARD_LATE_INIT + select OF_CONTROL + select SPL_OF_LIBFDT + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6SABREAUTO bool "mx6sabreauto" depends on MX6QDL @@ -674,6 +688,7 @@ source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" +source "board/bosch/acc/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pcl063/Kconfig" diff --git a/board/bosch/acc/Kconfig b/board/bosch/acc/Kconfig new file mode 100644 index 0000000000..da54d96e40 --- /dev/null +++ b/board/bosch/acc/Kconfig @@ -0,0 +1,19 @@ +if TARGET_MX6Q_ACC + +config SYS_VENDOR + default "bosch" + +config SYS_BOARD + default "acc" + +config SYS_CONFIG_NAME + default "imx6q-bosch-acc" + +config SYS_BOOT_EMMC + bool "Boot from EMMC" + default y + help + Say N here if you want to boot from SD card or microUSB. + Say Y to boot from eMMC. + +endif diff --git a/board/bosch/acc/MAINTAINERS b/board/bosch/acc/MAINTAINERS new file mode 100644 index 0000000000..1b88003712 --- /dev/null +++ b/board/bosch/acc/MAINTAINERS @@ -0,0 +1,9 @@ +MX6Q_ACC +M: Matthias Winker <matthias.winker(a)de.bosch.com> +M: Philip Oberfichtner <pro(a)denx.de> +S: Maintained +F: board/bosch/acc +F: include/configs/imx6q-bosch-acc.h +F: configs/imx6q_bosch_acc_defconfig +F: arch/arm/dts/imx6q-bosch-acc.dts +F: arch/arm/dts/imx6q-bosch-acc-u-boot.dts diff --git a/board/bosch/acc/Makefile b/board/bosch/acc/Makefile new file mode 100644 index 0000000000..d425a677bc --- /dev/null +++ b/board/bosch/acc/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2017 +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := acc.o diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c new file mode 100644 index 0000000000..dbc03c9371 --- /dev/null +++ b/board/bosch/acc/acc.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs(a)denx.de> + * Copyright (c) 2019 Bosch Thermotechnik GmbH + * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro(a)denx.de> + */ + +#include <common.h> +#include <bootstage.h> +#include <dm.h> +#include <dm/platform_data/serial_mxc.h> +#include <dm/device-internal.h> +#include <env.h> +#include <env_internal.h> +#include <hang.h> +#include <init.h> +#include <linux/delay.h> +#include <mmc.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <usb.h> +#include <usb/ehci-ci.h> +#include <fuse.h> + +#include <watchdog.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_ACC_PLAT_DETECT IMX_GPIO_NR(5, 9) +#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0) +#define GPIO_BUZZER IMX_GPIO_NR(1, 18) +#define GPIO_LAN1_RESET IMX_GPIO_NR(4, 27) +#define GPIO_LAN2_RESET IMX_GPIO_NR(4, 19) +#define GPIO_LAN3_RESET IMX_GPIO_NR(4, 18) +#define GPIO_USB_HUB_RESET IMX_GPIO_NR(5, 5) +#define GPIO_EXP_RS485_RESET IMX_GPIO_NR(4, 16) +#define GPIO_TOUCH_RESET IMX_GPIO_NR(1, 20) + +#define BOARD_INFO_MAGIC 0x19730517 + +struct board_info { + int magic; + int board; + int rev; +}; + +static struct board_info *detect_board(void); + +#define PFID_BOARD_ACC 0xe + +static const char * const name_board[] = { + [PFID_BOARD_ACC] = "ACC", +}; + +#define PFID_REV_22 0x8 +#define PFID_REV_21 0x9 +#define PFID_REV_20 0xa +#define PFID_REV_14 0xb +#define PFID_REV_13 0xc +#define PFID_REV_12 0xd +#define PFID_REV_11 0xe +#define PFID_REV_10 0xf + +static const char * const name_revision[] = { + [0 ... PFID_REV_10] = "Unknown", + [PFID_REV_10] = "1.0", + [PFID_REV_11] = "1.1", + [PFID_REV_12] = "1.2", + [PFID_REV_13] = "1.3", + [PFID_REV_14] = "1.4", + [PFID_REV_20] = "2.0", + [PFID_REV_21] = "2.1", + [PFID_REV_22] = "2.2", +}; + +/* + * NXP Reset Default: 0x0001B0B0 + * - Schmitt trigger input (PAD_CTL_HYS) + * - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP) + * - Pull Enabled (PAD_CTL_PUE) + * - Pull/Keeper Enabled (PAD_CTL_PKE) + * - CMOS output (No PAD_CTL_ODE) + * - Medium Speed (PAD_CTL_SPEED_MED) + * - 40 Ohm drive strength (PAD_CTL_DSE_40ohm) + * - Slow (PAD_CTL_SRE_SLOW) + */ + +/* Input, no pull up/down: 0x0x000100B0 */ +#define GPIN_PAD_CTRL (PAD_CTL_HYS \ + | PAD_CTL_SPEED_MED \ + | PAD_CTL_DSE_40ohm \ + | PAD_CTL_SRE_SLOW) + +/* Input, pull up: 0x0x0001B0B0 */ +#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \ + | PAD_CTL_PUS_100K_UP \ + | PAD_CTL_PUE \ + | PAD_CTL_PKE \ + | PAD_CTL_SPEED_MED \ + | PAD_CTL_DSE_40ohm \ + | PAD_CTL_SRE_SLOW) + +/* Input, pull down: 0x0x000130B0 */ +#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \ + | PAD_CTL_PUS_100K_DOWN \ + | PAD_CTL_PUE \ + | PAD_CTL_PKE \ + | PAD_CTL_SPEED_MED \ + | PAD_CTL_DSE_40ohm \ + | PAD_CTL_SRE_SLOW) + +static const iomux_v3_cfg_t board_detect_pads[] = { + /* Platform detect */ + IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* RAM Volt detect */ + IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* PFID 0..9 */ + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* Manufacturer */ + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), + /* Redundant */ + IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL)) +}; + +static int gpio_acc_pfid[] = { + IMX_GPIO_NR(2, 0), + IMX_GPIO_NR(2, 1), + IMX_GPIO_NR(2, 2), + IMX_GPIO_NR(2, 3), + IMX_GPIO_NR(2, 4), + IMX_GPIO_NR(6, 14), + IMX_GPIO_NR(6, 15), + IMX_GPIO_NR(2, 5), + IMX_GPIO_NR(2, 6), + IMX_GPIO_NR(2, 7), + IMX_GPIO_NR(6, 16), + IMX_GPIO_NR(5, 4), +}; + +static int init_gpio(int nr) +{ + int ret; + + ret = gpio_request(nr, ""); + if (ret != 0) { + printf("Could not request gpio nr: %d\n", nr); + hang(); + } + ret = gpio_direction_input(nr); + if (ret != 0) { + printf("Could not set gpio nr: %d to input\n", nr); + hang(); + } + return 0; +} + +/* + * We want to detect the board type only once in SPL, + * so we store the board_info struct at beginning in IRAM. + * + * U-Boot itself can read it also, and do not need again + * to detect board type. + * + */ +static struct board_info *detect_board(void) +{ + struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR; + int i; + + if (binfo->magic == BOARD_INFO_MAGIC) + return binfo; + + puts("Board: "); + SETUP_IOMUX_PADS(board_detect_pads); + init_gpio(GPIO_ACC_PLAT_DETECT); + if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) { + puts("not supported"); + hang(); + } else { + puts("Bosch "); + } + + for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++) + init_gpio(gpio_acc_pfid[i]); + + binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 | + gpio_get_value(gpio_acc_pfid[1]) << 1 | + gpio_get_value(gpio_acc_pfid[2]) << 2 | + gpio_get_value(gpio_acc_pfid[11]) << 3; + printf("%s ", name_board[binfo->board]); + + binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 | + gpio_get_value(gpio_acc_pfid[8]) << 1 | + gpio_get_value(gpio_acc_pfid[9]) << 2 | + gpio_get_value(gpio_acc_pfid[10]) << 3; + printf("rev: %s\n", name_revision[binfo->rev]); + + binfo->magic = BOARD_INFO_MAGIC; + + return binfo; +} + +static void unset_early_gpio(void) +{ + init_gpio(GPIO_LAN1_RESET); + init_gpio(GPIO_LAN2_RESET); + init_gpio(GPIO_LAN3_RESET); + init_gpio(GPIO_USB_HUB_RESET); + init_gpio(GPIO_EXP_RS485_RESET); + init_gpio(GPIO_TOUCH_RESET); + + gpio_set_value(GPIO_LAN1_RESET, 1); + gpio_set_value(GPIO_LAN2_RESET, 1); + gpio_set_value(GPIO_LAN3_RESET, 1); + gpio_set_value(GPIO_USB_HUB_RESET, 1); + gpio_set_value(GPIO_EXP_RS485_RESET, 1); + gpio_set_value(GPIO_TOUCH_RESET, 1); +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_MMC; + + switch (prio) { + case 0: + return ENVL_NOWHERE; + + case 1: + return ENVL_MMC; + } + + return ENVL_UNKNOWN; +} + +int board_late_init(void) +{ + struct board_info *binfo = detect_board(); + + switch (binfo->board) { + case PFID_BOARD_ACC: + env_set("bootconf", "conf-imx6q-bosch-acc.dtb"); + break; + default: + printf("Unknown board %d\n", binfo->board); + break; + } + + unset_early_gpio(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +/* Early + * - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an + * external pull-down resistor) + * - Touch clean reset on every boot + * - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init + */ +static const iomux_v3_cfg_t early_pads[] = { + IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */ + IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */ + IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */ + IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */ + IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */ + IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */ + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */ +}; + +static void setup_iomux_early(void) +{ + SETUP_IOMUX_PADS(early_pads); +} + +static void set_early_gpio(void) +{ + init_gpio(GPIO_BUZZER); + init_gpio(GPIO_LAN1_RESET); + init_gpio(GPIO_LAN2_RESET); + init_gpio(GPIO_LAN3_RESET); + init_gpio(GPIO_USB_HUB_RESET); + init_gpio(GPIO_EXP_RS485_RESET); + init_gpio(GPIO_TOUCH_RESET); + + /* Reset signals are active low */ + gpio_set_value(GPIO_BUZZER, 0); + gpio_set_value(GPIO_LAN1_RESET, 0); + gpio_set_value(GPIO_LAN2_RESET, 0); + gpio_set_value(GPIO_LAN3_RESET, 0); + gpio_set_value(GPIO_USB_HUB_RESET, 0); + gpio_set_value(GPIO_EXP_RS485_RESET, 0); + gpio_set_value(GPIO_TOUCH_RESET, 0); +} + +/* UART */ +#define UART_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#undef UART_PAD_CTRL +#define UART_PAD_CTRL 0x1b0b1 +static const iomux_v3_cfg_t uart2_pads[] = { + IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart2_pads); +} + +void spl_board_init(void) +{ +} + +static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = { + .dram_sdclk_0 = 0x00008038, + .dram_sdclk_1 = 0x00008038, + .dram_cas = 0x00008028, + .dram_ras = 0x00008028, + .dram_reset = 0x00000028, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00008000, + .dram_sdodt0 = 0x00000028, + .dram_sdodt1 = 0x00000028, + .dram_sdqs0 = 0x00008038, + .dram_sdqs1 = 0x00008038, + .dram_sdqs2 = 0x00008038, + .dram_sdqs3 = 0x00008038, + .dram_sdqs4 = 0x00008038, + .dram_sdqs5 = 0x00008038, + .dram_sdqs6 = 0x00008038, + .dram_sdqs7 = 0x00008038, + .dram_dqm0 = 0x00008038, + .dram_dqm1 = 0x00008038, + .dram_dqm2 = 0x00008038, + .dram_dqm3 = 0x00008038, + .dram_dqm4 = 0x00008038, + .dram_dqm5 = 0x00008038, + .dram_dqm6 = 0x00008038, + .dram_dqm7 = 0x00008038, +}; + +static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000028, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000038, + .grp_b1ds = 0x00000038, + .grp_b2ds = 0x00000038, + .grp_b3ds = 0x00000038, + .grp_b4ds = 0x00000038, + .grp_b5ds = 0x00000038, + .grp_b6ds = 0x00000038, + .grp_b7ds = 0x00000038, +}; + +static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = { + .p0_mpwldectrl0 = 0x0020001F, + .p0_mpwldectrl1 = 0x00280021, + .p1_mpwldectrl0 = 0x00120028, + .p1_mpwldectrl1 = 0x000D001F, + .p0_mpdgctrl0 = 0x43340342, + .p0_mpdgctrl1 = 0x03300325, + .p1_mpdgctrl0 = 0x4334033E, + .p1_mpdgctrl1 = 0x03280270, + .p0_mprddlctl = 0x46373B3E, + .p1_mprddlctl = 0x3B383544, + .p0_mpwrdlctl = 0x36383E40, + .p1_mpwrdlctl = 0x4030433A, +}; + +/* Micron MT41K128M16JT-125 (standard - 1600,CL=11) + * !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!! + * So this setting is actually invalid! + * +static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + */ + +/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E) + * Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss + * width set to 64, as four chips are used on acc (4 * 16 = 64) + */ +static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = { + .mem_speed = 1066, + .density = 2, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1313, // 13.125ns + .trcmin = 5063, // 50.625ns + .trasmin = 3750, // 37.5ns + .SRT = 0, // Set to 1 for temperatures above 85°C +}; + +static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = { + .ddr_type = DDR_TYPE_DDR3, + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + .cs_density = 32, /* 32Gb per CS */ + .ncs = 1, /* single chip select */ + .cs1_mirror = 0, + .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x33, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x33, /* 33 cycles, 500us (JEDEC default) */ +}; + +#define ACC_SPREAD_SPECTRUM_STOP 0x0fa +#define ACC_SPREAD_SPECTRUM_STEP 0x001 +#define ACC_SPREAD_SPECTRUM_DENOM 0x190 + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Turn clocks on/off */ + writel(0x00C0000F, &ccm->CCGR0); + writel(0x0030FC00, &ccm->CCGR1); + writel(0x03FF0033, &ccm->CCGR2); + writel(0x3FF3300F, &ccm->CCGR3); + writel(0x0003C300, &ccm->CCGR4); + writel(0x0F3000C3, &ccm->CCGR5); + writel(0x00000FFF, &ccm->CCGR6); + + /* Enable spread spectrum */ + writel(BM_ANADIG_PLL_528_SS_ENABLE | + BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) | + BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP), + &ccm->analog_pll_528_ss); + + writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM), + &ccm->analog_pll_528_denom); +} + +/* MMC board initialization is needed till adding DM support in SPL */ +#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC) +#include <mmc.h> +#include <fsl_esdhc_imx.h> + +static const iomux_v3_cfg_t usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)), + IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)), /* CD */ +}; + +static const iomux_v3_cfg_t usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 1, 4}, + {USDHC4_BASE_ADDR, 1, 8}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + detect_board(); + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC4_BASE_ADDR: + return 1; /* eMMC always present */ + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + gpio_direction_input(USDHC2_CD_GPIO); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 boot_dev = BOOT_DEVICE_MMC1; + + detect_board(); + + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC1 */ + if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) { + /* + * boot from SD is not allowed, if boot from eMMC is + * configured. + */ + puts("SD boot not allowed\n"); + spl_boot_list[0] = BOOT_DEVICE_NONE; + return; + } + + boot_dev = BOOT_DEVICE_MMC1; + break; + + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC */ + boot_dev = BOOT_DEVICE_MMC2; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + printf("Wrong board boot order\n"); + break; + } + + spl_boot_list[0] = boot_dev; +} + +static void setup_ddr(void) +{ + struct board_info *binfo = detect_board(); + + switch (binfo->rev) { + case PFID_REV_20: + case PFID_REV_21: + case PFID_REV_22: + default: + /* Rev 2 board has i.MX6 Dual with 64-bit RAM */ + mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width, + &acc_mx6d_ddr_ioregs, + &acc_mx6d_grp_ioregs); + mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib, + &acc_mx6d_mem_ddr3_1066); + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_write_level_calibration(&acc_mx6d_ddr_info); + mmdc_do_dqs_calibration(&acc_mx6d_ddr_info); + break; + } +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog power-down counter (only enabled after reset) */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* setup GP timer */ + timer_init(); + + /* Enable device tree and early DM support*/ + spl_early_init(); + + /* Setup early required pinmuxes */ + setup_iomux_early(); + set_early_gpio(); + + /* Setup UART pinmux */ + setup_iomux_uart(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + setup_ddr(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif + +#if IS_ENABLED(CONFIG_USB_EHCI_MX6) +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL BIT(9) + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, "imx6q-bosch-acc")) + return 0; + return -1; +} + +void reset_cpu(ulong addr) +{ + puts("Hanging CPU for watchdog reset!\n"); + hang(); +} + +#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS) +void show_boot_progress(int val) +{ + u32 fuseval; + int ret; + + if (val < 0) + val *= -1; + + switch (val) { + case BOOTSTAGE_ID_ENTER_CLI_LOOP: + printf("autoboot failed, check fuse\n"); + ret = fuse_read(0, 6, &fuseval); + if (ret == 0 && (fuseval & 0x2) == 0x0) { + printf("Enter cmdline, as device not closed\n"); + return; + } + ret = fuse_read(5, 7, &fuseval); + if (ret == 0 && fuseval == 0x0) { + printf("Enter cmdline, as it is a Development device\n"); + return; + } + panic("do not enter cmdline"); + break; + } +} +#endif diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig new file mode 100644 index 0000000000..3c02f0f5dd --- /dev/null +++ b/configs/imx6q_bosch_acc_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17780000 +CONFIG_SYS_MALLOC_LEN=0x01000000 +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x1fe000 +CONFIG_MX6QDL=y +CONFIG_MX6_DDRCAL=y +CONFIG_TARGET_MX6Q_ACC=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-bosch-acc" +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=8 +CONFIG_SPL_SIZE_LIMIT=69632 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x1ff000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_BMODE is not set +# CONFIG_CMD_DEKBLOB is not set +CONFIG_BUILD_TARGET="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run mmc_mmc_fit" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa +# CONFIG_SPL_CRC32 is not set +# CONFIG_SPL_CRYPTO is not set +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_FUSE is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_SLEEP is not set +# CONFIG_CMD_MP is not set +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT4=y +CONFIG_DOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_VERSION_VARIABLE=y +CONFIG_TFTP_BLOCKSIZE=512 +CONFIG_SPL_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +CONFIG_EXT4_WRITE=y +CONFIG_FS_FAT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h new file mode 100644 index 0000000000..686d5f007f --- /dev/null +++ b/include/configs/imx6q-bosch-acc.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs(a)denx.de> + * Copyright (c) 2019 Bosch Thermotechnik GmbH + * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro(a)denx.de> + */ + +#ifndef __IMX6Q_ACC_H +#define __IMX6Q_ACC_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +#ifdef CONFIG_SYS_BOOT_EMMC +#define MMC_ROOTFS_DEV 0 +#define MMC_ROOTFS_PART 2 +#endif + +#ifdef CONFIG_SYS_BOOT_EMMC +/* eMMC Boot */ +#define ENV_EXTRA \ + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ + "fitpart=1\0" \ + "optargs=ro quiet systemd.gpt_auto=false\0" \ + "production=1\0" \ + "mmcautodetect=yes\0" \ + "mmcrootfstype=ext4\0" \ + "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \ + "mmcargs=run finduuid; setenv bootargs " \ + "root=PARTUUID=${uuid} ${optargs} rootfstype=${mmcrootfstype}\0" \ + "mmc_mmc_fit=run env_persist; run setbm; run mmcloadfit; " \ + "run auth_fit_or_reset; run mmcargs addcon; " \ + "bootm ${fit_addr}#${bootconf}\0" \ + "bootset=0\0" \ + "setbm=if test ${bootset} -eq 1; " \ + "then setenv mmcpart 4; setenv fitpart 3; " \ + "else; setenv mmcpart 2; setenv fitpart 1; fi\0" \ + "handle_ustate=if test ${ustate} -eq 2; then setenv ustate 3; fi\0" \ + "switch_bootset=if test ${bootset} -eq 1; then setenv bootset 0; " \ + "else; setenv bootset 1;fi\0" \ + "env_persisted=0\0" \ + "env_persist=if test ${env_persisted} != 1; " \ + "then env set env_persisted 1; run save_env; fi;\0" \ + "save_env=env save; env save\0" \ + "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0" + +#define CONFIG_ENV_FLAGS_LIST_STATIC \ + "bootset:bw," \ + "clone_pending:bw," \ + "endurance_test:bw," \ + "env_persisted:bw," \ + "factory_reset:bw," \ + "fdtcontroladdr:xw," \ + "fitpart:dw," \ + "mmcpart:dw," \ + "production:bw," \ + "ustate:dw" + +#else +/* SD Card boot */ +#define ENV_EXTRA \ + "mmcdev=1\0" \ + "fitpart=1\0" \ + "rootpart=2\0" \ + "optargs=ro systemd.gpt_auto=false\0" \ + "finduuid=part uuid mmc ${mmcdev}:${rootpart} uuid\0" \ + "mmcargs=run finduuid;setenv bootargs root=PARTUUID=${uuid} ${optargs}\0" \ + "mmc_mmc_fit=run mmcloadfit; run auth_fit_or_reset; run mmcargs addcon; " \ + "bootm ${fit_addr}#${bootconf}\0" + +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootconf=conf-imx6q-bosch-acc.dtb\0"\ + "mmcfit_name=fitImage\0" \ + "mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \ + "auth_fit_or_reset=hab_auth_img ${fit_addr} ${filesize} || reset\0" \ + "console=ttymxc0\0" \ + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "fit_addr=19000000\0" \ + ENV_EXTRA + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RMII +#endif + +/* SPL */ +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#ifdef CONFIG_SYS_BOOT_EMMC + +/* Boot from eMMC */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 1 + +#else + +/* Boot from SD-card */ +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#endif + +#endif +#endif + +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ + +#endif /* __IMX6Q_ACC_H */ -- 2.34.1

3 2

[PATCH v2] treewide: Enable SPL_SEPARATE_BSS if SPL_BSS_START_ADDR is used
by Sean Anderson 21 Apr '22

21 Apr '22

If .bss does not immediately follow the end of the image, then CONFIG_SPL_SEPARATE_BSS must be selected. Typically, the location of bss is specified by using CONFIG_SPL_BSS_START_ADDR in a linker script. On these arches, CONFIG_SPL_SEPARATE_BSS should be enabled. If there is an option to use an alternate boot script (e.g. CONFIG_SPL_LDSCRIPT is just a default), just imply. If there is not, select. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- Changes in v2: - Add "if SPL" to selects to avoid config error arch/Kconfig | 2 ++ arch/arm/Kconfig | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index bc31e5ad50..8a63adcfd8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -85,6 +85,7 @@ config MIPS select HAVE_ARCH_IOREMAP select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL + select SPL_SEPARATE_BSS if SPL config NDS32 bool "NDS32 architecture" @@ -112,6 +113,7 @@ config RISCV select SUPPORT_OF_CONTROL select OF_CONTROL select DM + select SPL_SEPARATE_BSS if SPL imply DM_SERIAL imply DM_ETH imply DM_EVENT diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f277929c99..92bd189c95 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -8,6 +8,7 @@ config ARM64 bool select PHYS_64BIT select SYS_CACHE_SHIFT_6 + imply SPL_SEPARATE_BSS config ARM64_CRC32 bool "Enable support for CRC32 instruction" @@ -267,6 +268,7 @@ config CPU_ARM926EJS bool select SYS_CACHE_SHIFT_5 imply SYS_ARM_MMU + imply SPL_SEPARATE_BSS config CPU_ARM946ES bool @@ -277,6 +279,7 @@ config CPU_ARM1136 bool select SYS_CACHE_SHIFT_5 imply SYS_ARM_MMU + imply SPL_SEPARATE_BSS config CPU_ARM1176 bool @@ -624,6 +627,7 @@ config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS select GPIO_EXTRA_HEADER + select SPL_SEPARATE_BSS if SPL config TARGET_STV0991 bool "Support stv0991" @@ -814,6 +818,7 @@ config ARCH_OMAP2PLUS imply TI_SYSC if DM && OF_CONTROL imply FIT imply DM_EVENT + imply SPL_SEPARATE_BSS config ARCH_MESON bool "Amlogic Meson" @@ -954,6 +959,7 @@ config ARCH_MX6 select SYS_FSL_SEC_LE imply MXC_GPIO imply SYS_THUMB_BUILD + imply SPL_SEPARATE_BSS if ARCH_MX6 config SPL_LDSCRIPT -- 2.35.1.1320.gc452695387.dirty

2 1

[PATCH 1/3] arm: dts: Resync dts for BeagleBone and derivatives
by Paul Barker 21 Apr '22

21 Apr '22

Sync BeagleBone dts files & TPS dtsi files with Linux v5.17 and include the SanCloud BBE Extended WiFi dts added in v5.18-rc1. Also pull in changes to am33xx-l4.dtsi needed to support the BeagleBone Blue. The change to use the cpsw switch driver (commit c477358e66a3 in Linux) is excluded from the sync as u-boot does not recognise the new compatible string. Signed-off-by: Paul Barker <paul.barker(a)sancloud.com> --- arch/arm/dts/Makefile | 5 + arch/arm/dts/am335x-bone-common.dtsi | 5 + arch/arm/dts/am335x-boneblack-common.dtsi | 139 ---- ...common.dtsi => am335x-boneblack-hdmi.dtsi} | 28 - arch/arm/dts/am335x-boneblack-wireless.dts | 111 ++++ arch/arm/dts/am335x-boneblack.dts | 1 + arch/arm/dts/am335x-boneblue.dts | 617 ++++++++++++++++++ arch/arm/dts/am335x-bonegreen-wireless.dts | 127 ++++ ...be.dts => am335x-sancloud-bbe-common.dtsi} | 74 +-- .../dts/am335x-sancloud-bbe-extended-wifi.dts | 113 ++++ arch/arm/dts/am335x-sancloud-bbe-lite.dts | 50 ++ arch/arm/dts/am335x-sancloud-bbe.dts | 96 +-- arch/arm/dts/am33xx-l4.dtsi | 27 + arch/arm/dts/tps6507x.dtsi | 5 +- arch/arm/dts/tps65217.dtsi | 20 +- arch/arm/dts/tps65910.dtsi | 5 +- 16 files changed, 1082 insertions(+), 341 deletions(-) copy arch/arm/dts/{am335x-boneblack-common.dtsi => am335x-boneblack-hdmi.dtsi} (90%) create mode 100644 arch/arm/dts/am335x-boneblack-wireless.dts create mode 100644 arch/arm/dts/am335x-boneblue.dts create mode 100644 arch/arm/dts/am335x-bonegreen-wireless.dts copy arch/arm/dts/{am335x-sancloud-bbe.dts => am335x-sancloud-bbe-common.dtsi} (60%) create mode 100644 arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts create mode 100644 arch/arm/dts/am335x-sancloud-bbe-lite.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cd9a820f9569..47a2b6e39f85 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -375,6 +375,8 @@ dtb-$(CONFIG_AM33XX) += \ am335x-baltos.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ + am335x-boneblack-wireless.dtb \ + am335x-boneblue.dtb \ am335x-brppt1-mmc.dtb \ am335x-brppt1-nand.dtb \ am335x-brppt1-spi.dtb \ @@ -384,11 +386,14 @@ dtb-$(CONFIG_AM33XX) += \ am335x-evm.dtb \ am335x-evmsk.dtb \ am335x-bonegreen.dtb \ + am335x-bonegreen-wireless.dtb \ am335x-icev2.dtb \ am335x-pocketbeagle.dtb \ am335x-pxm50.dtb \ am335x-rut.dtb \ am335x-sancloud-bbe.dtb \ + am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ am335x-shc.dtb \ am335x-pdu001.dtb \ am335x-chiliboard.dtb \ diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 35ec1a8df870..43fe03d096ac 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -397,4 +397,9 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; + system-power-controller; +}; + +&pruss_tm { + status = "okay"; }; diff --git a/arch/arm/dts/am335x-boneblack-common.dtsi b/arch/arm/dts/am335x-boneblack-common.dtsi index 64c3e9269f40..a7a8c61ef9b2 100644 --- a/arch/arm/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/dts/am335x-boneblack-common.dtsi @@ -3,9 +3,6 @@ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <dt-bindings/display/tda998x.h> -#include <dt-bindings/interrupt-controller/irq.h> - &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -25,145 +22,9 @@ non-removable; }; -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; -}; - -&lcdc { - status = "okay"; - - /* If you want to get 24 bit RGB and 16 BGR mode instead of - * current 16 bit RGB and 24 BGR modes, set the propety - * below to "crossed" and uncomment the video-ports -property - * in tda19988 node. - */ - blue-and-red-wiring = "straight"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - nxp,calib-gpios = <&gpio1 25 0>; - interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ - /* video-ports = <0x234501>; */ - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - ports { - port@0 { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - }; -}; - -&rtc { - system-power-controller; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - / { memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; - - clk_mcasp0_fixed: clk_mcasp0_fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk_mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; }; diff --git a/arch/arm/dts/am335x-boneblack-common.dtsi b/arch/arm/dts/am335x-boneblack-hdmi.dtsi similarity index 90% copy from arch/arm/dts/am335x-boneblack-common.dtsi copy to arch/arm/dts/am335x-boneblack-hdmi.dtsi index 64c3e9269f40..7cfddada9348 100644 --- a/arch/arm/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/dts/am335x-boneblack-hdmi.dtsi @@ -6,25 +6,6 @@ #include <dt-bindings/display/tda998x.h> #include <dt-bindings/interrupt-controller/irq.h> -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; - non-removable; -}; - &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < @@ -113,10 +94,6 @@ }; }; -&rtc { - system-power-controller; -}; - &mcasp0 { #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -132,11 +109,6 @@ }; / { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - clk_mcasp0_fixed: clk_mcasp0_fixed { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/dts/am335x-boneblack-wireless.dts b/arch/arm/dts/am335x-boneblack-wireless.dts new file mode 100644 index 000000000000..8b2b24c80670 --- /dev/null +++ b/arch/arm/dts/am335x-boneblack-wireless.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM335x BeagleBone Black Wireless"; + compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us= <70000>; + + /* WL_EN */ + gpio = <&gpio3 9 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: pinmux_wl18xx_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ + >; + }; +}; + +&mac { + status = "disabled"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio3 { + ls-buf-en-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LS_BUF_EN"; + }; +}; diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts index e2ee8b8c07bc..9312197316f0 100644 --- a/arch/arm/dts/am335x-boneblack.dts +++ b/arch/arm/dts/am335x-boneblack.dts @@ -7,6 +7,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" / { model = "TI AM335x BeagleBone Black"; diff --git a/arch/arm/dts/am335x-boneblue.dts b/arch/arm/dts/am335x-boneblue.dts new file mode 100644 index 000000000000..856fdf58b0f4 --- /dev/null +++ b/arch/arm/dts/am335x-boneblue.dts @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM335x BeagleBone Blue"; + compatible = "ti,am335x-bone-blue", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + usr_0_led { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + usr_1_led { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + usr_2_led { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + usr_3_led { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + wifi_led { + label = "wifi"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "phy0assoc"; + }; + + red_led { + label = "red"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green_led { + label = "green"; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_1_led { + label = "bat25"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_2_led { + label = "bat50"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_3_led { + label = "bat75"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_4_led { + label = "bat100"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us= <70000>; + + /* WL_EN */ + gpio = <&gpio3 9 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ + + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + >; + }; + + /* UT0 */ + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + /* UT1 */ + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + /* GPS */ + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ + >; + }; + + /* DSM2 */ + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + >; + }; + + /* UT5 */ + uart5_pins: pinmux_uart5_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: pinmux_wl18xx_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ + >; + }; + + /* DCAN */ + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + >; + }; + + /* E1 */ + eqep0_pins: pinmux_eqep0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ + >; + }; + + /* E2 */ + eqep1_pins: pinmux_eqep1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ + >; + }; + + /* E3 */ + eqep2_pins: pinmux_eqep2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&i2c0 { + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + + #address-cells = <1>; + #size-cells = <1>; + baseboard_data: baseboard_data@0 { + reg = <0 0x100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; + + mpu9250@68 { + compatible = "invensense,mpu9250"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ax8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + }; + }; + }; + + pressure@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + /delete-property/ ti,pmic-shutdown-controller; + + charger { + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; + status = "okay"; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&rtc { + system-power-controller; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + "UART3_CTS", /* M17 */ + "UART3_RTS", /* M18 */ + "UART2_RX", /* A17 */ + "UART2_TX", /* B17 */ + "I2C1_SDA", /* B16 */ + "I2C1_SCL", /* A16 */ + "MMC0_CD", /* C15 */ + "SPI1_SS2", /* C18 */ + "EQEP_1A", /* V2 */ + "EQEP_1B", /* V3 */ + "MDIR_2B", /* V4 */ + "BATT_LED_2", /* T5 */ + "I2C2_SDA", /* D18 */ + "I2C2_SCL", /* D17 */ + "UART1_RX", /* D16 */ + "UART1_TX", /* D15 */ + "MMC2_DAT1", /* J18 */ + "MMC2_DAT2", /* K15 */ + "NC", /* F16 */ + "WIFI_LED", /* A15 */ + "MOT_STBY", /* D14 */ + "WLAN_IRQ", /* K16 */ + "PWM_2A", /* U10 */ + "PWM_2B", /* T10 */ + "", + "", + "BATT_LED_4", /* T11 */ + "BATT_LED_1", /* U12 */ + "BT_EN", /* K17 */ + "SPI1_SS1", /* H18 */ + "UART4_RX", /* T17 */ + "MDIR_1B"; /* U17 */ +}; + +&gpio1 { + gpio-line-names = + "MMC1_DAT0", /* U7 */ + "MMC1_DAT1", /* V7 */ + "MMC1_DAT2", /* R8 */ + "MMC1_DAT3", /* T8 */ + "MMC1_DAT4", /* U8 */ + "MMC1_DAT5", /* V8 */ + "MMC1_DAT6", /* R9 */ + "MMC1_DAT7", /* T9 */ + "DCAN1_TX", /* E18 */ + "DCAN1_RX", /* E17 */ + "UART0_RX", /* E15 */ + "UART0_TX", /* E16 */ + "EQEP_2A", /* T12 */ + "EQEP_2B", /* R12 */ + "PRU_E_A", /* V13 */ + "PRU_E_B", /* U13 */ + "MDIR_2A", /* R13 */ + "GPIO1_17", /* V14 */ + "PWM_1A", /* U14 */ + "PWM_1B", /* T14 */ + "EMMC_RST", /* R14 */ + "USR_LED_0", /* V15 */ + "USR_LED_1", /* U15 */ + "USR_LED_2", /* T15 */ + "USR_LED_3", /* V16 */ + "GPIO1_25", /* U16 */ + "MCASP0_AXR0", /* T16 */ + "MCASP0_AXR1", /* V17 */ + "MCASP0_ACLKR", /* U18 */ + "BATT_LED_3", /* V6 */ + "MMC1_CLK", /* U9 */ + "MMC1_CMD"; /* V9 */ +}; + +&gpio2 { + gpio-line-names = + "MDIR_1A", /* T13 */ + "MCASP0_FSR", /* V12 */ + "LED_RED", /* R7 */ + "LED_GREEN", /* T7 */ + "MODE_BTN", /* U6 */ + "PAUSE_BTN", /* T6 */ + "MDIR_4A", /* R1 */ + "MDIR_4B", /* R2 */ + "MDIR_3B", /* R3 */ + "MDIR_3A", /* R4 */ + "SVO7", /* T1 */ + "SVO8", /* T2 */ + "SVO5", /* T3 */ + "SVO6", /* T4 */ + "UART5_TX", /* U1 */ + "UART5_RX", /* U2 */ + "SERVO_EN", /* U3 */ + "NC", /* U4 */ + "UART3_RX", /* L17 */ + "UART3_TX", /* L16 */ + "MMC2_CLK", /* L15 */ + "DCAN1_SILENT", /* M16 */ + "SVO1", /* U5 */ + "SVO3", /* R5 */ + "SVO2", /* V5 */ + "SVO4", /* R6 */ + "MMC0_DAT3", /* F17 */ + "MMC0_DAT2", /* F18 */ + "MMC0_DAT1", /* G15 */ + "MMC0_DAT0", /* G16 */ + "MMC0_CLK", /* G17 */ + "MMC0_CMD"; /* G18 */ +}; + +&gpio3 { + gpio-line-names = + "MMC2_DAT3", /* H16 */ + "GPIO3_1", /* H17 */ + "GPIO3_2", /* J15 */ + "MMC2_CMD", /* J16 */ + "MMC2_DAT0", /* J17 */ + "I2C0_SDA", /* C17 */ + "I2C0_SCL", /* C16 */ + "EMU1", /* C14 */ + "EMU0", /* B14 */ + "WL_EN", /* K18 */ + "WL_BT_OE", /* L18 */ + "", + "", + "NC", /* F15 */ + "SPI1_SCK", /* A13 */ + "SPI1_MISO", /* B13 */ + "SPI1_MOSI", /* D12 */ + "GPIO3_17", /* C12 */ + "EQEP_0A", /* B12 */ + "EQEP_0B", /* C13 */ + "GPIO3_20", /* D13 */ + "IMU_INT", /* A14 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + + ls-buf-en-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&eqep0 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep0_pins>; + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&eqep1 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep1_pins>; + status = "okay"; +}; + +&epwmss2 { + status = "okay"; +}; + +&eqep2 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep2_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-bonegreen-wireless.dts b/arch/arm/dts/am335x-bonegreen-wireless.dts new file mode 100644 index 000000000000..74db0fc39397 --- /dev/null +++ b/arch/arm/dts/am335x-bonegreen-wireless.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-bonegreen-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM335x BeagleBone Green Wireless"; + compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us= <70000>; + + /* WL_EN */ + gpio = <&gpio0 26 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: pinmux_wl18xx_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ + >; + }; +}; + +&mac { + status = "disabled"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio1 { + ls-buf-en-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LS_BUF_EN"; + }; +}; + +/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/ +/* in case it isn't, wilink8 ends up in one of the test modes that */ +/* intruces various issues (elp wkaeup timeouts etc.) */ +/* On the BBGW this pin is routed through the level shifter (U21) that */ +/* introduces a pullup on the line and wilink8 ends up in a bad state. */ +/* use a gpio hog to force this pin low. An alternative may be adding */ +/* an external pulldown on U21 pin 4. */ + +&gpio3 { + bt-aud-in-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "MCASP0_AHCLKR"; + }; +}; diff --git a/arch/arm/dts/am335x-sancloud-bbe.dts b/arch/arm/dts/am335x-sancloud-bbe-common.dtsi similarity index 60% copy from arch/arm/dts/am335x-sancloud-bbe.dts copy to arch/arm/dts/am335x-sancloud-bbe-common.dtsi index 275ba339adf4..21b601fa4c12 100644 --- a/arch/arm/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/dts/am335x-sancloud-bbe-common.dtsi @@ -2,21 +2,8 @@ /* * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "SanCloud BeagleBone Enhanced"; - compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; &am33xx_pinmux { - pinctrl-names = "default"; - cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -53,85 +40,28 @@ >; }; - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - usb_hub_ctrl: usb_hub_ctrl { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ >; }; - - mpu6050_pins: pinmux_mpu6050_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - >; - }; - - lps3331ap_pins: pinmux_lps3331ap_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; }; &mac { - pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; }; &cpsw_emac0 { - phy-handle = <&ethphy0>; phy-mode = "rgmii-id"; }; &i2c0 { - lps331ap: barometer@5c { - compatible = "st,lps331ap-press"; - st,drdy-int-pin = <1>; - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - }; - - mpu6050: accelerometer@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - orientation = <0xff 0 0 0 1 0 0 0 0xff>; - }; - usb2512b: usb-hub@2c { + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_ctrl>; compatible = "microchip,usb2512b"; reg = <0x2c>; reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - /* wifi on port 4 */ }; }; diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts new file mode 100644 index 000000000000..246a1a9b3e44 --- /dev/null +++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Sancloud Ltd + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "SanCloud BeagleBone Enhanced Extended WiFi"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us= <100000>; + }; +}; + +&am33xx_pinmux { + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + /* gpmc_a9.gpio1_25: RADIO_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) + + /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_clk.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + bluetooth_pins: pinmux_bluetooth_pins { + pinctrl-single,pins = < + /* event_intr0.gpio0_19 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + /* uart1_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + + /* uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + + /* uart1_ctsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&mmc3 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + ti,needs-special-hs-handling; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + clock-frequency = <50000000>; + max-frequency = <50000000>; +}; + +&uart1 { + status = "okay"; + + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins &bluetooth_pins>; + compatible = "qcom,qca6174-bt"; + enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; + interrupt-parent = <&gpio0>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + }; +}; diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/dts/am335x-sancloud-bbe-lite.dts new file mode 100644 index 000000000000..d6ef19311a91 --- /dev/null +++ b/arch/arm/dts/am335x-sancloud-bbe-lite.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 SanCloud Ltd + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" + +/ { + model = "SanCloud BeagleBone Enhanced Lite"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; +}; + +&am33xx_pinmux { + bb_spi0_pins: pinmux_bb_spi0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) + >; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bb_spi0_pins>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "micron,spi-authenta"; + + reg = <0>; + spi-max-frequency = <16000000>; + spi-cpha; + }; +}; diff --git a/arch/arm/dts/am335x-sancloud-bbe.dts b/arch/arm/dts/am335x-sancloud-bbe.dts index 275ba339adf4..efbe93135dbe 100644 --- a/arch/arm/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/dts/am335x-sancloud-bbe.dts @@ -7,6 +7,8 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" #include <dt-bindings/interrupt-controller/irq.h> / { @@ -15,66 +17,6 @@ }; &am33xx_pinmux { - pinctrl-names = "default"; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb_hub_ctrl: usb_hub_ctrl { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ - >; - }; - mpu6050_pins: pinmux_mpu6050_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ @@ -88,31 +30,10 @@ }; }; -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <&ethphy0>; - phy-mode = "rgmii-id"; -}; - &i2c0 { lps331ap: barometer@5c { + pinctrl-names = "default"; + pinctrl-0 = <&lps3331ap_pins>; compatible = "st,lps331ap-press"; st,drdy-int-pin = <1>; reg = <0x5c>; @@ -121,17 +42,12 @@ }; mpu6050: accelerometer@68 { + pinctrl-names = "default"; + pinctrl-0 = <&mpu6050_pins>; compatible = "invensense,mpu6050"; reg = <0x68>; interrupt-parent = <&gpio0>; interrupts = <2 IRQ_TYPE_EDGE_RISING>; orientation = <0xff 0 0 0 1 0 0 0 0xff>; }; - - usb2512b: usb-hub@2c { - compatible = "microchip,usb2512b"; - reg = <0x2c>; - reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - /* wifi on port 4 */ - }; }; diff --git a/arch/arm/dts/am33xx-l4.dtsi b/arch/arm/dts/am33xx-l4.dtsi index e678673317af..5892612efa80 100644 --- a/arch/arm/dts/am33xx-l4.dtsi +++ b/arch/arm/dts/am33xx-l4.dtsi @@ -1810,6 +1810,15 @@ status = "disabled"; }; + eqep0: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <79>; + status = "disabled"; + }; + ehrpwm0: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; @@ -1862,6 +1871,15 @@ status = "disabled"; }; + eqep1: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <88>; + status = "disabled"; + }; + ehrpwm1: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; @@ -1914,6 +1932,15 @@ status = "disabled"; }; + eqep2: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <89>; + status = "disabled"; + }; + ehrpwm2: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; diff --git a/arch/arm/dts/tps6507x.dtsi b/arch/arm/dts/tps6507x.dtsi index 4c326e591e5a..db4809d308f9 100644 --- a/arch/arm/dts/tps6507x.dtsi +++ b/arch/arm/dts/tps6507x.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /* diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi index a63272422d76..0d463de5650f 100644 --- a/arch/arm/dts/tps65217.dtsi +++ b/arch/arm/dts/tps65217.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /* @@ -13,6 +10,21 @@ &tps { compatible = "ti,tps65217"; + interrupt-controller; + #interrupt-cells = <1>; + + charger { + compatible = "ti,tps65217-charger"; + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; + status = "disabled"; + }; + + pwrbutton { + compatible = "ti,tps65217-pwrbutton"; + interrupts = <2>; + status = "disabled"; + }; regulators { #address-cells = <1>; diff --git a/arch/arm/dts/tps65910.dtsi b/arch/arm/dts/tps65910.dtsi index b0ac6657a170..a941d1e62328 100644 --- a/arch/arm/dts/tps65910.dtsi +++ b/arch/arm/dts/tps65910.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /* -- 2.32.0

2 5

[PATCH] fs: Allow to compile FS_SQUASHFS only for proper U-Boot
by Pali Rohár 21 Apr '22

21 Apr '22

CONFIG_SPL_FS_SQUASHFS cannot be disabled when CONFIG_FS_SQUASHFS is enabled. Fix it. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- fs/fs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fs.c b/fs/fs.c index 7bf8c440886a..b4306cf8499e 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -286,7 +286,7 @@ static struct fstype_info fstypes[] = { .ln = fs_ln_unsupported, }, #endif -#if IS_ENABLED(CONFIG_FS_SQUASHFS) +#if CONFIG_IS_ENABLED(FS_SQUASHFS) { .fstype = FS_TYPE_SQUASHFS, .name = "squashfs", -- 2.20.1

2 1

[PATCH 1/3] env: Implement lower priority arch_env_get_location()
by Marek Vasut 21 Apr '22

21 Apr '22

Currently there is only one way to override desired environment location, by implementing env_get_location(). This is increasingly being conflated both on board level and architecture level, which leads to a problem on boards where this function is already implemented on architecture level, since those boards have no way to override this environment location on board level anymore. Implement arch_env_get_location() function which is architecture specific and should only ever be implemented in architecture code. This function has lower priority than env_get_location(), which should only ever be implemented in board code, and which overrides the arch_env_get_location() architecture environment selection. This way, architecture can define its default environment chooser, while board can now override it as needed at all times. There is no functional change, since env_get_location() simply returns arch_env_get_location(), and arch_env_get_location() implements the current env_get_location() default content. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Adam Ford <aford173(a)gmail.com> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Marek Behún <marek.behun(a)nic.cz> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Tommaso Merciai <tomm.merciai(a)gmail.com> Cc: Vladimir Oltean <vladimir.oltean(a)nxp.com> --- env/env.c | 29 ++++++++++++++++++++++++++--- include/env_internal.h | 16 ++++++++++++++++ 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/env/env.c b/env/env.c index e4dfb92e154..69848fb0608 100644 --- a/env/env.c +++ b/env/env.c @@ -110,13 +110,14 @@ static void env_set_inited(enum env_location location) } /** - * env_get_location() - Returns the best env location for a board + * arch_env_get_location() - Returns the best env location for an arch * @op: operations performed on the environment * @prio: priority between the multiple environments, 0 being the * highest priority * * This will return the preferred environment for the given priority. - * This is overridable by boards if they need to. + * This is overridable by architectures if they need to and has lower + * priority than board side env_get_location() override. * * All implementations are free to use the operation, the priority and * any other data relevant to their choice, but must take into account @@ -127,7 +128,7 @@ static void env_set_inited(enum env_location location) * Returns: * an enum env_location value on success, a negative error code otherwise */ -__weak enum env_location env_get_location(enum env_operation op, int prio) +__weak enum env_location arch_env_get_location(enum env_operation op, int prio) { if (prio >= ARRAY_SIZE(env_locations)) return ENVL_UNKNOWN; @@ -135,6 +136,28 @@ __weak enum env_location env_get_location(enum env_operation op, int prio) return env_locations[prio]; } +/** + * env_get_location() - Returns the best env location for a board + * @op: operations performed on the environment + * @prio: priority between the multiple environments, 0 being the + * highest priority + * + * This will return the preferred environment for the given priority. + * This is overridable by boards if they need to. + * + * All implementations are free to use the operation, the priority and + * any other data relevant to their choice, but must take into account + * the fact that the lowest prority (0) is the most important location + * in the system. The following locations should be returned by order + * of descending priorities, from the highest to the lowest priority. + * + * Returns: + * an enum env_location value on success, a negative error code otherwise + */ +__weak enum env_location env_get_location(enum env_operation op, int prio) +{ + return arch_env_get_location(op, prio); +} /** * env_driver_lookup() - Finds the most suited environment location diff --git a/include/env_internal.h b/include/env_internal.h index 07c227ecc03..14f4c696785 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -234,10 +234,26 @@ const char *env_ext4_get_intf(void); */ const char *env_ext4_get_dev_part(void); +/** + * arch_env_get_location()- Provide the best location for the U-Boot environment + * + * It is a weak function allowing board to overidde the environment location + * on architecture level. This has lower priority than env_get_location(), + * which can be defined on board level. + * + * @op: operations performed on the environment + * @prio: priority between the multiple environments, 0 being the + * highest priority + * Return: an enum env_location value on success, or -ve error code. + */ +enum env_location arch_env_get_location(enum env_operation op, int prio); + /** * env_get_location()- Provide the best location for the U-Boot environment * * It is a weak function allowing board to overidde the environment location + * on board level. This has higher priority than arch_env_get_location(), + * which can be defined on architecture level. * * @op: operations performed on the environment * @prio: priority between the multiple environments, 0 being the -- 2.35.1

2 5

ipq40xx SPI and/or SPI flash driver not working.
by Florence Riker 21 Apr '22

21 Apr '22

Hello everyone, recently I'm trying to port U-Boot 2022.01 to my ipq4019 development board, but I can't get the SPI flash working, when I send the command sf probe, it returns this: drivers/core/uclass.c:325-uclass_find_device_by_seq() 0 drivers/core/uclass.c:333-uclass_find_device_by_seq() - 0 'spi@78b5000' drivers/core/uclass.c:336-uclass_find_device_by_seq() - found drivers/spi/spi-uclass.c:282-spi_find_chip_select() spi_qup spi@78b5000: spi_find_chip_select: plat=bfd95318, cs=0 drivers/core/uclass.c:325-uclass_find_device_by_seq() 0 drivers/core/uclass.c:333-uclass_find_device_by_seq() - 0 'spi@78b5000' drivers/core/uclass.c:336-uclass_find_device_by_seq() - found drivers/spi/spi-uclass.c:282-spi_find_chip_select() spi_qup spi@78b5000: spi_find_chip_select: plat=bfd95318, cs=0 drivers/mtd/spi/spi-nor-core.c:1350- spi_nor_read_id() jedec_spi_nor m25p16@0: unrecognized JEDEC id bytes: ff, ff, ff drivers/spi/spi-uclass.c:439- spi_get_bus_and_cs() spi_get_bus_and_cs: Error path, created=0, device 'm25p16@0' Failed to initialize SPI flash at 0:0 (error -2) Which is not correct because the JEDEC id shouldn't be all Fs, I can't figure out whether it's the SPI driver or SPI flash driver is not working, or I just not doing it right. Any suggestions? Thanks.

1 0

[PATCH 1/2] arm: layerscape: Add sfp driver
by Sean Anderson 21 Apr '22

21 Apr '22

This adds a driver for the Security Fuse Processor (SFP) present on LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and other "security" related fuses. Similar devices (sharing the same name) are present on other processors, but for the moment this just supports the LS2 variants. The mirror registers are loaded during power-on reset. All mirror registers must be programmed or read at once. Because of this, `fuse prog` will program all fuses, even though only one might be specified. To prevent accidentally burning through all your fuse programming cycles with something like `fuse prog 0 0 A B C D`, we limit ourselves to one programming cycle per reset. Fuses are numbered based on their address. The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc. The TA_PROG_SFP supply must be enabled when programming fuses, but must be disabled when reading them. Typically this supply is enabled by inserting a jumper or by setting a register in the board's FPGA. I've also added support for using a regulator. This could be helpful for automatically issuing the FPGA write, or for toggling a GPIO controlling the supply. I suggest using the following procedure for programming: 1. Override the fuses you wish to program => fuse override 0 2 A B C D 2. Inspect the values and ensure that they are what you expect => fuse sense 0 2 4 3. Enable TA_PROG_SFP 4. Issue a program command using OSPR0 as a dummy. Since it contains the write-protect bit you will usually want to write it last anyway. => fuse prog 0 0 0 5. Disable TA_PROG_SFP 6. Read back the fuses and ensure they are correct => fuse read 0 2 4 Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- MAINTAINERS | 5 + drivers/misc/Kconfig | 14 ++ drivers/misc/Makefile | 1 + drivers/misc/ls2_sfp.c | 350 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 370 insertions(+) create mode 100644 drivers/misc/ls2_sfp.c diff --git a/MAINTAINERS b/MAINTAINERS index 7a9e3156f4..6a302b35e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -271,6 +271,11 @@ F: drivers/spi/spi-qup.c F: drivers/net/mdio-ipq4019.c F: drivers/rng/msm_rng.c +ARM LAYERSCAPE SFP +M: Sean Anderson <sean.anderson(a)seco.com> +S: Maintained +F: drivers/misc/ls2_sfp.c + ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese <sr(a)denx.de> S: Maintained diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 7029bb7b5c..2a86c42017 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -224,6 +224,20 @@ config JZ4780_EFUSE help This selects support for the eFUSE on Ingenic JZ4780 SoCs. +config LS2_SFP + bool "Layerscape Security Fuse Processor" + depends on FSL_LSCH2 || ARCH_LS1021A + depends on MISC + imply DM_REGULATOR + help + This adds support for the Security Fuse Processor found on Layerscape + SoCs. It contains various fuses related to secure boot, including the + Super Root Key hash, One-Time-Programmable Master Key, Debug + Challenge/Response values, and others. Fuses are numbered according + to their four-byte offset from the start of the bank. + + If you don't need to read/program fuses, say 'n'. + config MXC_OCOTP bool "Enable MXC OCOTP Driver" depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b7a8ef68ab..4926671833 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o +obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c new file mode 100644 index 0000000000..df54b0c89e --- /dev/null +++ b/drivers/misc/ls2_sfp.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson <sean.anderson(a)seco.com> + * + * This driver supports the Security Fuse Processor device found on some + * Layerscape processors. At the moment, we only support a few processors. + * This driver was written with reference to the Layerscape SDK User + * Guide [1] and the ATF SFP driver [2]. + * + * [1] https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/… + * [2] https://source.codeaurora.org/external/qoriq/qoriq-components/atf/tree/driv… + */ + +#define LOG_CATEGORY UCLASS_MISC +#include <common.h> +#include <clk.h> +#include <fuse.h> +#include <misc.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/read.h> +#include <linux/bitfield.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SFP_INGR 0x20 +#define SFP_SVHESR 0x24 +#define SFP_SFPCR 0x28 + +#define SFP_START 0x200 +#define SFP_END 0x284 +#define SFP_SIZE (SFP_END - SFP_START + 4) + +#define SFP_INGR_ERR BIT(8) +#define SFP_INGR_INST GENMASK(7, 0) + +#define SFP_INGR_READFB 0x01 +#define SFP_INGR_PROGFB 0x02 + +#define SFP_SFPCR_PPW GENMASK(15, 0) + +enum ls2_sfp_ioctl { + LS2_SFP_IOCTL_READ, + LS2_SFP_IOCTL_PROG, +}; + +/** + * struct ls2_sfp_priv - private data for LS2 SFP + * @base: Base address of SFP + * @supply: The (optional) supply for TA_PROG_SFP + * @programmed: Whether we've already programmed the fuses since the last + * reset. The SFP has a *very* limited amount of programming + * cycles (two to six, depending on the model), so we try and + * prevent accidentally performing additional programming + * cycles. + * @dirty: Whether the mirror registers have been written to (overridden) + * since we've last read the fuses (either as part of the reset + * process or using a READFB instruction). There is a much larger, + * but still finite, limit on the number of SFP read cycles (around + * 300,000), so we try and minimize reads as well. + */ +struct ls2_sfp_priv { + void __iomem *base; + struct udevice *supply; + bool programmed, dirty; +}; + +static u32 ls2_sfp_readl(struct ls2_sfp_priv *priv, ulong off) +{ + u32 val = be32_to_cpu(readl(priv->base + off)); + + log_debug("%08x = readl(%p)\n", val, priv->base + off); + return val; +} + +static void ls2_sfp_writel(struct ls2_sfp_priv *priv, ulong val, ulong off) +{ + log_debug("writel(%08lx, %p)\n", val, priv->base + off); + writel(cpu_to_be32(val), priv->base + off); +} + +static bool ls2_sfp_validate(struct udevice *dev, int offset, int size) +{ + if (offset < 0 || size < 0) { + dev_notice(dev, "size and offset must be positive\n"); + return false; + } + + if (offset & 3 || size & 3) { + dev_notice(dev, "size and offset must be multiples of 4\n"); + return false; + } + + if (offset + size > SFP_SIZE) { + dev_notice(dev, "size + offset must be <= %#x\n", SFP_SIZE); + return false; + } + + return true; +} + +static int ls2_sfp_read(struct udevice *dev, int offset, void *buf_bytes, + int size) +{ + int i; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + u32 *buf = buf_bytes; + + if (!ls2_sfp_validate(dev, offset, size)) + return -EINVAL; + + for (i = 0; i < size; i += 4) + buf[i >> 2] = ls2_sfp_readl(priv, SFP_START + offset + i); + + return size; +} + +static int ls2_sfp_write(struct udevice *dev, int offset, + const void *buf_bytes, int size) +{ + int i; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + const u32 *buf = buf_bytes; + + if (!ls2_sfp_validate(dev, offset, size)) + return -EINVAL; + + for (i = 0; i < size; i += 4) + ls2_sfp_writel(priv, buf[i >> 2], SFP_START + offset + i); + + priv->dirty = true; + return size; +} + +static int ls2_sfp_check_secret(struct udevice *dev) +{ + struct ls2_sfp_priv *priv = dev_get_priv(dev); + u32 svhesr = ls2_sfp_readl(priv, SFP_SVHESR); + + if (svhesr) { + dev_warn(dev, "secret value hamming error not zero: %08x\n", + svhesr); + return -EIO; + } + return 0; +} + +static int ls2_sfp_transaction(struct ls2_sfp_priv *priv, ulong inst) +{ + u32 ingr; + + ls2_sfp_writel(priv, inst, SFP_INGR); + + do { + ingr = ls2_sfp_readl(priv, SFP_INGR); + } while (FIELD_GET(SFP_INGR_INST, ingr)); + + return FIELD_GET(SFP_INGR_ERR, ingr) ? -EIO : 0; +} + +static int ls2_sfp_ioctl(struct udevice *dev, unsigned long request, void *buf) +{ + int ret; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + + switch (request) { + case LS2_SFP_IOCTL_READ: + if (!priv->dirty) { + dev_dbg(dev, "ignoring read request, since fuses are not dirty\n"); + return 0; + } + + ret = ls2_sfp_transaction(priv, SFP_INGR_READFB); + if (ret) { + dev_err(dev, "error reading fuses\n"); + return ret; + } + + ls2_sfp_check_secret(dev); + priv->dirty = false; + return 0; + case LS2_SFP_IOCTL_PROG: + if (priv->programmed) { + dev_warn(dev, "fuses already programmed\n"); + return -EPERM; + } + + ret = ls2_sfp_check_secret(dev); + if (ret) + return ret; + + if (priv->supply) { + ret = regulator_set_enable(priv->supply, true); + if (ret) + return ret; + } + + ret = ls2_sfp_transaction(priv, SFP_INGR_PROGFB); + priv->programmed = true; + if (priv->supply) + regulator_set_enable(priv->supply, false); + + if (ret) + dev_err(dev, "error programming fuses\n"); + return ret; + default: + dev_dbg(dev, "unknown ioctl %lu\n", request); + return -EINVAL; + } +} + +static const struct misc_ops ls2_sfp_ops = { + .read = ls2_sfp_read, + .write = ls2_sfp_write, + .ioctl = ls2_sfp_ioctl, +}; + +static int ls2_sfp_probe(struct udevice *dev) +{ + int ret; + struct clk clk; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + ulong rate; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) { + dev_dbg(dev, "could not read register base\n"); + return -EINVAL; + } + + ret = device_get_supply_regulator(dev, "ta-sfp-prog", &priv->supply); + if (ret && ret != -ENODEV && ret != -ENOSYS) { + dev_dbg(dev, "problem getting supply (err %d)\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "ipg", &clk); + if (ret == -ENOSYS) { + rate = gd->bus_clk; + } else if (ret) { + dev_dbg(dev, "could not get clock (err %d)\n", ret); + return ret; + } else { + ret = clk_enable(&clk); + if (ret) { + dev_dbg(dev, "could not enable clock (err %d)\n", ret); + return ret; + } + + rate = clk_get_rate(&clk); + clk_free(&clk); + if (!rate || IS_ERR_VALUE(rate)) { + ret = rate ? rate : -ENOENT; + dev_dbg(dev, "could not get clock rate (err %d)\n", + ret); + return ret; + } + } + + /* platform clock in MHz / 4 * 12 */ + ls2_sfp_writel(priv, FIELD_PREP(SFP_SFPCR_PPW, rate * 3 / 1000000), + SFP_SFPCR); + + ls2_sfp_check_secret(dev); + return 0; +} + +static const struct udevice_id ls2_sfp_ids[] = { + { .compatible = "fsl,ls1021a-sfp" }, + { } +}; + +U_BOOT_DRIVER(ls2_sfp) = { + .name = "ls2_sfp", + .id = UCLASS_MISC, + .of_match = ls2_sfp_ids, + .probe = ls2_sfp_probe, + .ops = &ls2_sfp_ops, + .priv_auto = sizeof(struct ls2_sfp_priv), +}; + +static int ls2_sfp_device(struct udevice **dev) +{ + int ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(ls2_sfp), dev); + + if (ret) + log_debug("device not found (err %d)\n", ret); + return ret; +} + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_ioctl(dev, LS2_SFP_IOCTL_READ, NULL); + if (ret) + return ret; + + ret = misc_read(dev, word << 2, val, sizeof(*val)); + return ret < 0 ? ret : 0; +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_read(dev, word << 2, val, sizeof(*val)); + return ret < 0 ? ret : 0; +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_write(dev, word << 2, &val, sizeof(val)); + if (ret < 0) + return ret; + + return misc_ioctl(dev, LS2_SFP_IOCTL_PROG, NULL); +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_write(dev, word << 2, &val, sizeof(val)); + return ret < 0 ? ret : 0; +} -- 2.35.1.1320.gc452695387.dirty

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