February 2022 - U-Boot

[PATCH] mxs: power: Change sequence of enabling DCDC switches
by Lukasz Majewski 05 Feb '22

05 Feb '22

The imx28 uses following voltage supplies hierarchy: VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM \-----> VDDD One shall first enable DCDC on the parent source (VDDIO) and then follow with its children. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 35ea71a5ba8..c33170f06d3 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -627,11 +627,11 @@ static void mxs_power_enable_4p2(void) mxs_power_init_dcdc_4p2_source(); - writel(vdddctrl, &power_regs->hw_power_vdddctrl); + writel(vddioctrl, &power_regs->hw_power_vddioctrl); early_delay(20); writel(vddactrl, &power_regs->hw_power_vddactrl); early_delay(20); - writel(vddioctrl, &power_regs->hw_power_vddioctrl); + writel(vdddctrl, &power_regs->hw_power_vdddctrl); /* * Check if FET is enabled on either powerout and if so, -- 2.20.1

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[PATCH] smegw01: Update DDR initialization
by Fabio Estevam 05 Feb '22

05 Feb '22

Sync with the latest DDR initialization from Phytec, which uses version 1.2 of NXP's i.MX7D DRAM Register Programming Aid spreadsheet. This updated DDR initialization fixes occasional system freeze. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- board/storopack/smegw01/imximage.cfg | 55 ++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/board/storopack/smegw01/imximage.cfg b/board/storopack/smegw01/imximage.cfg index c7fa06996cce..5ebeea56a772 100644 --- a/board/storopack/smegw01/imximage.cfg +++ b/board/storopack/smegw01/imximage.cfg @@ -44,57 +44,80 @@ BOOT_FROM sd /* DDR initialization came from Phytec */ DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ DATA 4 0x30360388 0x40000000 DATA 4 0x30360384 0x40000000 + +/* deassert presetn */ DATA 4 0x30391000 0x00000002 + +/* DDR Controller Regs */ DATA 4 0x307a0000 0x01040001 -DATA 4 0x307a01a0 0x80400003 -DATA 4 0x307a01a4 0x00100020 -DATA 4 0x307a01a8 0x80100004 -DATA 4 0x307a0064 0x0040002b +DATA 4 0x307a0064 0x00400046 DATA 4 0x307a0490 0x00000001 -DATA 4 0x307a00d0 0x00020083 DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00d0 0x00020083 DATA 4 0x307a00dc 0x09300004 -DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e0 0x04480000 DATA 4 0x307a00e4 0x00100004 DATA 4 0x307a00f4 0x0000033f -DATA 4 0x307a0100 0x090b1109 -DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0100 0x090e110a +DATA 4 0x307a0104 0x0007020e DATA 4 0x307a0108 0x03040407 DATA 4 0x307a010c 0x00002006 -DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0110 0x04020304 DATA 4 0x307a0114 0x03030202 -DATA 4 0x307a0120 0x00000802 +DATA 4 0x307a0120 0x00000803 DATA 4 0x307a0180 0x00800020 -DATA 4 0x307a0184 0x02000100 DATA 4 0x307a0190 0x02098204 DATA 4 0x307a0194 0x00030303 -DATA 4 0x307a0200 0x00001f15 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0200 0x0000001f DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a020c 0x00000000 DATA 4 0x307a0210 0x00000f0f DATA 4 0x307a0214 0x07070707 -DATA 4 0x307a0218 0x0f0f0707 +DATA 4 0x307a0218 0x0f070707 DATA 4 0x307a0240 0x06000604 DATA 4 0x307a0244 0x00000001 + +/* deassert presetn */ DATA 4 0x30391000 0x00000000 + +/* PHY Controller Regs */ DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 DATA 4 0x307900b0 0x1010007e DATA 4 0x3079009c 0x00000d6e -DATA 4 0x30790020 0x0a0a0a0a -DATA 4 0x30790030 0x06060606 +/* write leveling values for each byte lane */ +DATA 4 0x3079006c 0x06090108 +/* write leveling resync cycle */ +DATA 4 0x30790078 0x00000001 +DATA 4 0x30790078 0x00000000 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790020 0x08080808 DATA 4 0x30790050 0x01000010 DATA 4 0x30790050 0x00000010 +DATA 4 0x30790018 0x0000000f + +/* start manual ZQ */ DATA 4 0x307900c0 0x0e407304 DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e447306 -CHECK_BITS_SET 4 0x307900c4 0x1 DATA 4 0x307900c0 0x0e447304 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +/* end manual ZQ */ DATA 4 0x307900c0 0x0e407304 + +/* final init sequence */ DATA 4 0x30384130 0x00000000 DATA 4 0x30340020 0x00000178 DATA 4 0x30384130 0x00000002 DATA 4 0x30790018 0x0000000f + CHECK_BITS_SET 4 0x307a0004 0x1 -- 2.25.1

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[PATCH] imx: imx8mn_beacon: Enable TrustZone
by Adam Ford 05 Feb '22

05 Feb '22

When the board was added, enabling tzc380 was left off by mistake. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index b5263ccfd7..bb51be01c5 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -122,6 +122,8 @@ void board_init_f(ulong dummy) hang(); } + enable_tzc380(); + /* DDR initialization */ spl_dram_init(); -- 2.32.0

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[PATCH v2] imx: Enable ACTLR.SMP in SPL for i.MX6/7
by Sven Schwermer 05 Feb '22

05 Feb '22

Similar to what has been done before with c5437e5b for u-boot proper, we enable the SMP bit for SPL as well. This is necessary when SDP booting straight into Linux, i.e. falcon boot. When SDP boot mode is active, the ROM code does not set this bit which makes the caches not work once activated in Linux. On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into an initramfs shell from ~6.1s down to ~1.2s. Signed-off-by: Sven Schwermer <sven(a)svenschwermer.de> --- Changes in v2: - Apply fix for i.MX7(ULP) as well - Document quantitive improvement in boot time arch/arm/include/asm/mach-imx/sys_proto.h | 5 +++++ arch/arm/mach-imx/cache.c | 2 +- arch/arm/mach-imx/mx6/soc.c | 3 +++ arch/arm/mach-imx/mx7/soc.c | 3 +++ arch/arm/mach-imx/mx7ulp/soc.c | 2 ++ 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 444834995e..3f66d225c8 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -236,4 +236,9 @@ unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, unsigned long reg3); void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) +void enable_ca7_smp(void); +#endif + #endif diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index 4e3b49a3fd..ab9b621a2a 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -11,7 +11,7 @@ #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> -static void enable_ca7_smp(void) +void enable_ca7_smp(void) { u32 val; diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index aacfc854a2..41f1a6e64e 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -487,6 +487,9 @@ int arch_cpu_init(void) if (is_mx6dqp()) noc_setup(); #endif + + enable_ca7_smp(); + return 0; } diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 21690072e1..f6aec5a3aa 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -14,6 +14,7 @@ #include <asm/mach-imx/rdc-sema.h> #include <asm/arch/imx-rdc.h> #include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/bootm.h> #include <dm.h> @@ -323,6 +324,8 @@ int arch_cpu_init(void) imx_gpcv2_init(); + enable_ca7_smp(); + return 0; } #else diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index c90ce22404..bc41cbc687 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -13,6 +13,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/hab.h> +#include <asm/mach-imx/sys_proto.h> #include <asm/setup.h> #include <linux/bitops.h> @@ -77,6 +78,7 @@ enum bt_mode get_boot_mode(void) int arch_cpu_init(void) { + enable_ca7_smp(); return 0; } -- 2.34.1

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[PATCH] regulator: bd718x7: Bypass bogus warnings
by Marek Vasut 05 Feb '22

05 Feb '22

When regulator consumer attempts to set enabled DVS regulator voltage, the driver aborts with "Only DVS bucks can be changed when enabled". In case the regulator is already set to specified voltage, do nothing instead of failing outright. When regulator consumer attempts to set enables regulator which cannot be controlled because it is already always enabled, the driver aborts with -EINVAL. Again, do nothing in such case and return 0, because the request is really fulfilled, the regulator is enabled. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Matti Vaittinen <matti.vaittinen(a)fi.rohmeurope.com> --- drivers/power/regulator/bd71837.c | 69 ++++++++++++++++--------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/drivers/power/regulator/bd71837.c b/drivers/power/regulator/bd71837.c index 74011d62985..d4f8da80ad7 100644 --- a/drivers/power/regulator/bd71837.c +++ b/drivers/power/regulator/bd71837.c @@ -306,7 +306,7 @@ static int bd71837_set_enable(struct udevice *dev, bool enable) * reseted to snvs state. Hence we can't set the state here. */ if (plat->enablemask == HW_STATE_CONTROL) - return -EINVAL; + return enable ? 0 : -EINVAL; if (enable) val = plat->enablemask; @@ -315,6 +315,38 @@ static int bd71837_set_enable(struct udevice *dev, bool enable) val); } +static int bd71837_get_value(struct udevice *dev) +{ + unsigned int reg, range; + unsigned int tmp; + struct bd71837_plat *plat = dev_get_plat(dev); + int i; + + reg = pmic_reg_read(dev->parent, plat->volt_reg); + if (((int)reg) < 0) + return reg; + + range = reg & plat->rangemask; + + reg &= plat->volt_mask; + reg >>= ffs(plat->volt_mask) - 1; + + for (i = 0; i < plat->numranges; i++) { + struct bd71837_vrange *r = &plat->ranges[i]; + + if (plat->rangemask && ((plat->rangemask & range) != + r->rangeval)) + continue; + + if (!vrange_find_value(r, reg, &tmp)) + return tmp; + } + + pr_err("Unknown voltage value read from pmic\n"); + + return -EINVAL; +} + static int bd71837_set_value(struct udevice *dev, int uvolt) { unsigned int sel; @@ -330,6 +362,9 @@ static int bd71837_set_value(struct udevice *dev, int uvolt) */ if (!plat->dvs) if (bd71837_get_enable(dev)) { + /* If the value is already set, skip the warning. */ + if (bd71837_get_value(dev) == uvolt) + return 0; pr_err("Only DVS bucks can be changed when enabled\n"); return -EINVAL; } @@ -365,38 +400,6 @@ static int bd71837_set_value(struct udevice *dev, int uvolt) plat->rangemask, sel); } -static int bd71837_get_value(struct udevice *dev) -{ - unsigned int reg, range; - unsigned int tmp; - struct bd71837_plat *plat = dev_get_plat(dev); - int i; - - reg = pmic_reg_read(dev->parent, plat->volt_reg); - if (((int)reg) < 0) - return reg; - - range = reg & plat->rangemask; - - reg &= plat->volt_mask; - reg >>= ffs(plat->volt_mask) - 1; - - for (i = 0; i < plat->numranges; i++) { - struct bd71837_vrange *r = &plat->ranges[i]; - - if (plat->rangemask && ((plat->rangemask & range) != - r->rangeval)) - continue; - - if (!vrange_find_value(r, reg, &tmp)) - return tmp; - } - - pr_err("Unknown voltage value read from pmic\n"); - - return -EINVAL; -} - static int bd71837_regulator_probe(struct udevice *dev) { struct bd71837_plat *plat = dev_get_plat(dev); -- 2.34.1

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[PATCH] mx6: Use imx6_src_get_boot_mode() to check boot device
by Harald Seiler 05 Feb '22

05 Feb '22

Use imx6_src_get_boot_mode() instead of manually reading SBMR1. The existing function has proper handling for software overrides of the bootdevice which can happen, for example, when booting from an alternate source using `bmode`. Signed-off-by: Harald Seiler <hws(a)denx.de> --- arch/arm/mach-imx/mx6/soc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index aacfc854a2f8..bc56ef2b0b20 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -498,8 +498,7 @@ __weak int board_mmc_get_env_dev(int devno) static int mmc_get_boot_dev(void) { - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 soc_sbmr = readl(&src_regs->sbmr1); + u32 soc_sbmr = imx6_src_get_boot_mode(); u32 bootsel; int devno; -- 2.31.1

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[PATCH 0/1] configs: imx8mm-cl-iot-gate: update dfu_alt_info for single flash.bin
by Ying-Chun Liu 05 Feb '22

05 Feb '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> imx8mm generate a single bootable flash.bin again. Previous it is flash.bin and u-boot.itb. So we need to modify dfu_alt_info for single flash.bin. Ying-Chun Liu (PaulLiu) (1): configs: imx8mm-cl-iot-gate: update dfu_alt_info for single flash.bin include/configs/imx8mm-cl-iot-gate.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.34.1

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[PATCH 1/3] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy
by Marek Vasut 05 Feb '22

05 Feb '22

From: Richard Zhu <hongxing.zhu(a)nxp.com> Add binding for reference clock PAD modes of the i.MX8 PCIe PHY. Signed-off-by: Richard Zhu <hongxing.zhu(a)nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Reviewed-by: Tim Harvey <tharvey(a)gateworks.com> Tested-by: Tim Harvey <tharvey(a)gateworks.com> Reviewed-by: Rob Herring <robh(a)kernel.org> Link: https://lore.kernel.org/r/1638432158-4119-2-git-send-email-hongxing.zhu@nxp… Signed-off-by: Vinod Koul <vkoul(a)kernel.org> Signed-off-by: Marek Vasut <marex(a)denx.de> # Pick from Linux f6f787874aa5 ("dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy") --- include/dt-bindings/phy/phy-imx8-pcie.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/phy/phy-imx8-pcie.h diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h new file mode 100644 index 00000000000..8bbe2d6538d --- /dev/null +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * This header provides constants for i.MX8 PCIe. + */ + +#ifndef _DT_BINDINGS_IMX8_PCIE_H +#define _DT_BINDINGS_IMX8_PCIE_H + +/* Reference clock PAD mode */ +#define IMX8_PCIE_REFCLK_PAD_UNUSED 0 +#define IMX8_PCIE_REFCLK_PAD_INPUT 1 +#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 + +#endif /* _DT_BINDINGS_IMX8_PCIE_H */ -- 2.34.1

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[RESEND PATCH 1/2] imx: mx6ull: fix REFTOP_VBGADJ setting
by Dario Binacchi 05 Feb '22

05 Feb '22

The previous code wrote the contents of the fuse as is in the REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of the table in the code comment. This table is also different from the table in the commit description. But then, which of the two is correct? If it is assumed that an unprogrammed fuse has a value of 0 then for backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to 6 (b'110). Therefore, the table in the code comment can be considered correct as well as this patch. Fixes: 97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting") Signed-off-by: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> --- arch/arm/mach-imx/mx6/soc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index aacfc854a2f8..099cb5b12d77 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -366,11 +366,13 @@ static void init_bandgap(void) * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, */ if (is_mx6ull()) { + static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7}; + val = readl(&fuse->mem0); val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT; val &= 0x7; - writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, + writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, &anatop->ana_misc0_set); } } -- 2.32.0

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[PATCH] imx8mq_evk: configs: add/cleanup variables for distro boot
by Andrey Zhizhikin 05 Feb '22

05 Feb '22

Add fdt_addr_r fdtfile which used by distro boot, and cleanup legacy environment variables. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin(a)leica-geosystems.com> --- include/configs/imx8mq_evk.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 49a9526d96..63539c7649 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -63,13 +63,13 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=0x43500000\0" \ - "kernel_addr_r=0x40880000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "image=Image\0" \ "console=ttymxc0,115200\0" \ - "fdt_addr=0x43000000\0" \ + "fdt_addr_r=0x43000000\0" \ "boot_fdt=try\0" \ - "fdt_file=imx8mq-evk.dtb\0" \ + "fdtfile=imx8mq-evk.dtb\0" \ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ base-commit: 558002a0f2230bedf6b38716f3ed86a92fc9010b prerequisite-patch-id: 59faad9613725a42a9057aba206b92cf084dd1c1 -- 2.25.1

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