February 2022 - U-Boot

[PATCH v1 1/2] imx: imx8qm_rom7720: Increase CONFIG_SYS_BOOTM_LEN to 64MB
by Oliver Graute 05 Feb '22

05 Feb '22

Increase CONFIG_SYS_BOOTM_LEN to 64MB Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- include/configs/imx8qm_rom7720.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 666e497b0b..31d861481f 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -21,6 +21,8 @@ #define USDHC2_BASE_ADDR 0x5B020000 #define USDHC3_BASE_ADDR 0x5B030000 +#define CONFIG_SYS_BOOTM_LEN SZ_64M + /* FUSE command */ /* Boot M4 */ -- 2.17.1

2 1

[PATCH v2] arm: dts: imx8mq kernel dts updates
by Angus Ainslie 05 Feb '22

05 Feb '22

Update to the 5.16 imx8mq dts files and dt bindings Changes since v1: Dropped rfkill.h that is not in linux mainline yet. Signed-off-by: Angus Ainslie <angus(a)akkea.ca> --- arch/arm/dts/imx8mq.dtsi | 203 ++++++++++++++++++++-- include/dt-bindings/interconnect/imx8mq.h | 48 +++++ 2 files changed, 238 insertions(+), 13 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mq.h diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index a44f729d0e..71bf497f99 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -11,6 +11,7 @@ #include "dt-bindings/input/input.h" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/interconnect/imx8mq.h> #include "imx8mq-pinfunc.h" / { @@ -39,8 +40,6 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; - usb0 = &usb_dwc3_0; - usb1 = &usb_dwc3_1; }; ckil: clock-ckil { @@ -194,7 +193,6 @@ compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; psci { @@ -288,11 +286,13 @@ }; soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -557,9 +557,17 @@ #address-cells = <1>; #size-cells = <1>; + imx8mq_uid: soc-uid@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@90 { + reg = <0x90 6>; + }; }; anatop: syscon@30360000 { @@ -828,6 +836,8 @@ clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, <&clk IMX8MQ_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -840,6 +850,8 @@ clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, <&clk IMX8MQ_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -852,6 +864,8 @@ clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, <&clk IMX8MQ_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1018,9 +1032,14 @@ reg = <0x30a00300 0x100>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; #phy-cells = <0>; power-domains = <&pgc_mipi>; status = "disabled"; @@ -1077,6 +1096,110 @@ status = "disabled"; }; + mipi_csi1: csi@30a70000 { + compatible = "fsl,imx8mq-mipi-csi2"; + reg = <0x30a70000 0x1000>; + clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, + <&clk IMX8MQ_CLK_CSI1_ESC>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>; + clock-names = "core", "esc", "ui"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>, + <&clk IMX8MQ_CLK_CSI1_ESC>; + assigned-clock-rates = <266000000>, <333000000>, <66000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_1000M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + power-domains = <&pgc_mipi_csi1>; + resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, + <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, + <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; + fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; + interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; + interconnect-names = "dram"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi1_mipi_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + }; + + csi1: csi@30a90000 { + compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; + clock-names = "mclk"; + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; + }; + + mipi_csi2: csi@30b60000 { + compatible = "fsl,imx8mq-mipi-csi2"; + reg = <0x30b60000 0x1000>; + clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_ESC>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>; + clock-names = "core", "esc", "ui"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>, + <&clk IMX8MQ_CLK_CSI2_ESC>; + assigned-clock-rates = <266000000>, <333000000>, <66000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_1000M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + power-domains = <&pgc_mipi_csi2>; + resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, + <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, + <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; + fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; + interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; + interconnect-names = "dram"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2_mipi_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; + }; + }; + + csi2: csi@30b80000 { + compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + reg = <0x30b80000 0x10000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; + clock-names = "mclk"; + status = "disabled"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; + }; + mu: mailbox@30aa0000 { compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; reg = <0x30aa0000 0x10000>; @@ -1154,12 +1277,50 @@ <&clk IMX8MQ_CLK_ENET_PHY_REF>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, + <&clk IMX8MQ_CLK_ENET_TIMER>, + <&clk IMX8MQ_CLK_ENET_REF>, + <&clk IMX8MQ_CLK_ENET_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_125M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + fsl,stop-mode = <&iomuxc_gpr 0x10 3>; status = "disabled"; }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MQ_CLK_NOC>; + fsl,ddrc = <&ddrc>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + + opp-400M { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; @@ -1304,10 +1465,9 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; - num-viewport = <4>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1317,11 +1477,20 @@ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; + linux,pci-domain = <0>; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; @@ -1333,10 +1502,9 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; - num-viewport = <4>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1346,11 +1514,20 @@ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; + linux,pci-domain = <1>; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h new file mode 100644 index 0000000000..1a4cae7f8b --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H + +#define IMX8MQ_ICN_NOC 1 +#define IMX8MQ_ICS_DRAM 2 +#define IMX8MQ_ICS_OCRAM 3 +#define IMX8MQ_ICM_A53 4 + +#define IMX8MQ_ICM_VPU 5 +#define IMX8MQ_ICN_VIDEO 6 + +#define IMX8MQ_ICM_GPU 7 +#define IMX8MQ_ICN_GPU 8 + +#define IMX8MQ_ICM_DCSS 9 +#define IMX8MQ_ICN_DCSS 10 + +#define IMX8MQ_ICM_USB1 11 +#define IMX8MQ_ICM_USB2 12 +#define IMX8MQ_ICN_USB 13 + +#define IMX8MQ_ICM_CSI1 14 +#define IMX8MQ_ICM_CSI2 15 +#define IMX8MQ_ICM_LCDIF 16 +#define IMX8MQ_ICN_DISPLAY 17 + +#define IMX8MQ_ICM_SDMA2 18 +#define IMX8MQ_ICN_AUDIO 19 + +#define IMX8MQ_ICN_ENET 20 +#define IMX8MQ_ICM_ENET 21 + +#define IMX8MQ_ICM_SDMA1 22 +#define IMX8MQ_ICM_NAND 23 +#define IMX8MQ_ICM_USDHC1 24 +#define IMX8MQ_ICM_USDHC2 25 +#define IMX8MQ_ICM_PCIE1 26 +#define IMX8MQ_ICM_PCIE2 27 +#define IMX8MQ_ICN_MAIN 28 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ -- 2.25.1

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[PATCH 00/20] i.MX8ULP misc update
by Peng Fan (OSS) 05 Feb '22

05 Feb '22

From: Peng Fan <peng.fan(a)nxp.com> This is to upstream NXP downstream i.MX8ULP patches including ADC/DRAM/LPAV/FUSE/ENET update/fix Alice Guo (3): imx8ulp: clock: Support to enable/disable the ADC1 clock imx8ulp: measure die temperature using PMC Temperature Sensor imx8ulp: implement to obtain the SoC current temperature Jacky Bai (1): imx8ulp:ddr: saving the dram config timing data into sram Peng Fan (1): imx8ulp: assign PXP/HIFI4/EPDC to APD domain Ye Li (15): imx8ulp: soc: Check the DBD_EN fuse before setting RDC arm: imx8ulp: Allocate LPAV resources to AP domain imx8ulp: clock: Support LPAV clocks in cgc and pcc imx8ulp: clock: Add MIPI DSI clock and DCNano clock imx8ulp: rdc: allow A35 access flexspi0 mem imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest imx8ulp: Fix DCNANO QoS setting imx8ulp: Remove freescale name from CPU revision imx8ulp: Workaround LPOSC_TRIM fuse load issue imx8ulp: clock: Reset DDR controller before clock enable imx8ulp: clock: Support to reset DCNano and MIPI DSI imx8ulp: Update ethernet mac to get from fuse imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock imx8ulp: ddr: Fix DDR frequency request issue arch/arm/include/asm/arch-imx8ulp/cgc.h | 37 +- arch/arm/include/asm/arch-imx8ulp/clock.h | 4 + arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 63 +++- .../include/asm/arch-imx8ulp/imx8ulp-pins.h | 4 + arch/arm/include/asm/arch-imx8ulp/pcc.h | 70 +++- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 + arch/arm/mach-imx/imx8ulp/cgc.c | 325 +++++++++++++++--- arch/arm/mach-imx/imx8ulp/clock.c | 156 ++++++++- arch/arm/mach-imx/imx8ulp/pcc.c | 158 ++++++++- arch/arm/mach-imx/imx8ulp/soc.c | 117 ++++++- board/freescale/imx8ulp_evk/imx8ulp_evk.c | 56 +++ board/freescale/imx8ulp_evk/spl.c | 9 + drivers/ddr/imx/imx8ulp/Kconfig | 7 + drivers/ddr/imx/imx8ulp/ddr_init.c | 55 ++- drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/imx_pmc_temperature.c | 174 ++++++++++ 17 files changed, 1148 insertions(+), 97 deletions(-) create mode 100644 drivers/thermal/imx_pmc_temperature.c -- 2.30.0

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[PATCH 1/2] ARM: imx: imx8m: Align PLL 1.2 GHz option with Linux
by Marek Vasut 05 Feb '22

05 Feb '22

Linux uses slightly different divider settings for the 1.2 GHz PLL configuration, adjust the coefficients to match Linux. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index f8e4ec0d905..2ca3bf68e74 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -244,9 +244,9 @@ int intpll_configure(enum pll_clocks pll, ulong freq) INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); break; case MHZ(1200): - /* 24 * 0xc8 / 2 / 2 ^ 1 */ - pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) | - INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1); + /* 24 * 0x12c / 3 / 2 ^ 1 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); break; case MHZ(2000): /* 24 * 0xfa / 3 / 2 ^ 0 */ -- 2.34.1

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[PATCH v7 0/2] arm: imx8m: add support for Advantech RSB-3720
by Ying-Chun Liu 05 Feb '22

05 Feb '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console v2: update dts v3: remove unnecessary code. move board code to board/advantech v4: rebase to latest master branch. v5: fix commit description v6: update dts v7: remove redefined configs for latest master branch. Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mp-rsb3720-a1 dts file arm: imx8m: add support for Advantech RSB-3720 arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 161 ++ arch/arm/dts/imx8mp-rsb3720-a1.dts | 805 +++++++ arch/arm/mach-imx/imx8m/Kconfig | 15 + board/advantech/imx8mp_rsb3720a1/Kconfig | 14 + board/advantech/imx8mp_rsb3720a1/MAINTAINERS | 7 + board/advantech/imx8mp_rsb3720a1/Makefile | 24 + .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 213 ++ .../imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg | 11 + .../lpddr4_timing_rsb3720a1_4G.c | 1848 ++++++++++++++++ .../lpddr4_timing_rsb3720a1_6G.c | 1875 +++++++++++++++++ board/advantech/imx8mp_rsb3720a1/spl.c | 260 +++ configs/imx8mp_rsb3720a1_4G_defconfig | 167 ++ configs/imx8mp_rsb3720a1_6G_defconfig | 168 ++ include/configs/imx8mp_rsb3720.h | 223 ++ 15 files changed, 5794 insertions(+) create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1.dts create mode 100644 board/advantech/imx8mp_rsb3720a1/Kconfig create mode 100644 board/advantech/imx8mp_rsb3720a1/MAINTAINERS create mode 100644 board/advantech/imx8mp_rsb3720a1/Makefile create mode 100644 board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c create mode 100644 board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/spl.c create mode 100644 configs/imx8mp_rsb3720a1_4G_defconfig create mode 100644 configs/imx8mp_rsb3720a1_6G_defconfig create mode 100644 include/configs/imx8mp_rsb3720.h -- 2.34.1

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[PATCH] imx8mn-ddr4-evk: generate single bootable image
by Andrey Zhizhikin 05 Feb '22

05 Feb '22

As suggested in commit 028abfd9b157 ("imx8mm-evk: Generate a single bootable flash.bin again") for imx8mm_evk, it is possible to produce single bootable image via binman. This restores the original behavior in distros, where only one boot container is used to create target image. Perform similar adaptions in order to provide single bootable image for imx8mn-ddr4-evk derivate. Update documentation to drop additional step of copying u-boot.itb Fixes: 353dfe4b4359 ("imx8mn-ddr4-evk: switch to use binman") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin(a)leica-geosystems.com> --- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++- .../imx8mn_evk/imximage-8mn-ddr4.cfg | 2 +- doc/board/nxp/imx8mn_evk.rst | 1 - 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 1d3844437d..2e39790766 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -157,7 +157,9 @@ }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; @@ -224,4 +226,19 @@ }; }; }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "spl.bin"; + }; + + uboot: blob-ext@2 { + offset = <0x58000>; + filename = "u-boot.itb"; + }; + }; }; diff --git a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg index 22aec26da7..7286b26494 100644 --- a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg +++ b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg @@ -7,4 +7,4 @@ ROM_VERSION v2 BOOT_FROM sd -LOADER mkimage.flash.mkimage 0x912000 +LOADER u-boot-spl-ddr.bin 0x912000 diff --git a/doc/board/nxp/imx8mn_evk.rst b/doc/board/nxp/imx8mn_evk.rst index 9fbb947032..711545af89 100644 --- a/doc/board/nxp/imx8mn_evk.rst +++ b/doc/board/nxp/imx8mn_evk.rst @@ -50,7 +50,6 @@ Burn the flash.bin to MicroSD card offset 32KB: .. code-block:: bash $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc - $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc Boot ---- base-commit: 4e81f3be340072ad2c0aac093677333702f14f22 -- 2.25.1

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[PATCH 1/3] doc: imx8mm_evk: Remove ATF_LOAD_ADDR export
by Fabio Estevam 05 Feb '22

05 Feb '22

imx8mm-u-boot.dtsi passes the ATF load address via the 'entry' and 'load' properties. Remove the step that performs the ATF_LOAD_ADDR export, which is now unneeded. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- doc/board/nxp/imx8mm_evk.rst | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/board/nxp/imx8mm_evk.rst b/doc/board/nxp/imx8mm_evk.rst index b377c4de276d..b9e67b954fc2 100644 --- a/doc/board/nxp/imx8mm_evk.rst +++ b/doc/board/nxp/imx8mm_evk.rst @@ -42,7 +42,6 @@ Build U-Boot $ export CROSS_COMPILE=aarch64-poky-linux- $ make imx8mm_evk_defconfig - $ export ATF_LOAD_ADDR=0x920000 $ make Burn the flash.bin to MicroSD card offset 33KB: -- 2.25.1

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[PATCH 1/2] clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imxrt10{20|50}
by Heiko Thiery 05 Feb '22

05 Feb '22

The clock composite is required when using the clock framework. So select it automatically. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- drivers/clk/imx/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index a2cd0347c3..cdd348020b 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -76,6 +76,7 @@ config SPL_CLK_IMXRT1020 depends on ARCH_IMXRT && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MXRT1020 @@ -84,6 +85,7 @@ config CLK_IMXRT1020 depends on ARCH_IMXRT select CLK select CLK_CCF + select CLK_COMPOSITE_CCF help This enables support clock driver for i.MXRT1020 platforms. @@ -92,6 +94,7 @@ config SPL_CLK_IMXRT1050 depends on ARCH_IMXRT && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MXRT1050 @@ -100,5 +103,6 @@ config CLK_IMXRT1050 depends on ARCH_IMXRT select CLK select CLK_CCF + select CLK_COMPOSITE_CCF help This enables support clock driver for i.MXRT1050 platforms. -- 2.30.2

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[PATCH] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board
by Marek Vasut 05 Feb '22

05 Feb '22

From: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> The PDK2 board is capable of running both 100M and 1G ethernet. However, the i.MX6 has only one ethernet MAC, so it is possible to configure either 100M or 1G Ethernet. In case of 100M option, the PHY is on the SoM and the signals are routed to a RJ45 port. For 1G the PHY is on the PDK2 board with another RJ45 port. 100M and 1G ethernet use different signal pins from the i.MX6, but share the MDIO bus. This SoM board combination is used to demonstrate how to enable 1G ethernet configuration. Signed-off-by: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Stefano Babic <sbabic(a)denx.de> --- NOTE: Adapted from Linux 298591bf725a ("ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board") --- arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi | 2 +- arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi | 50 +++++++++++++++++++-- include/configs/dh_imx6.h | 4 +- 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi index 32128d4d2ab..a1ffb1d6fc5 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi @@ -15,7 +15,7 @@ }; &fec { - phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; phy-reset-post-delay = <10>; diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi index af4719aaeba..d8772a98966 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi @@ -38,6 +38,45 @@ status = "okay"; }; +/* 1G ethernet */ +/delete-node/ &ethphy0; +&fec { + phy-mode = "rgmii"; + phy-handle = <&ethphy7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1G>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy7: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy7>; + pinctrl-names = "default"; + reg = <7>; + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + &hdmi { ddc-i2c-bus = <&i2c2>; status = "okay"; @@ -113,9 +152,14 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1 + >; + }; + + pinctrl_ethphy7: ethphy7-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ >; }; diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 8183e7debd4..3cf0578b5e1 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -32,9 +32,9 @@ /* FEC ethernet */ #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_MXC_PHYADDR 7 #define CONFIG_ARP_TIMEOUT 200UL /* MMC Configs */ -- 2.33.0

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[PATCH v2 4/4] arm64: dts: imx8mq-u-boot.dtsi: improve odd blob-ext naming
by sbabic＠denx.de 05 Feb '22

05 Feb '22

> Rather than using odd implicit blob-ext naming, explicitly specify the > type to be of blob-ext and therefore also simplify the node naming. > Signed-off-by: Patrick Wildt <patrick(a)blueri.se> > Reviewed-by: Fabio Estevam <festevam(a)denx.de> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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