November 2022 - U-Boot

[PATCH v1 0/2] i2c: microchip: misc minor fixes
by Conor Dooley 14 Nov '22

14 Nov '22

Hey all, Pair of fixes here for some of the logic in the microchip i2c driver. Both were reported against the Linux driver, which formed the basis for the U-Boot driver & the issues are present here too. Thanks, Conor. Conor Dooley (2): i2c: microchip: fix ack sending logic i2c: microchip: fix erroneous late ack send drivers/i2c/i2c-microchip.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) -- 2.38.0

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[PATCH] i2c: i2c-gpio: add newline
by Sergei Antonov 14 Nov '22

14 Nov '22

Add newline at the end of the printed string. Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- drivers/i2c/i2c-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index 1aedad5c8ede..4ed9e9e7cddd 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -362,7 +362,7 @@ static int i2c_gpio_of_to_plat(struct udevice *dev) return 0; error: - pr_err("Can't get %s gpios! Error: %d", dev->name, ret); + pr_err("Can't get %s gpios! Error: %d\n", dev->name, ret); return ret; } -- 2.34.1

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Changing eMMC boot partition size
by Philip Oberfichtner 14 Nov '22

14 Nov '22

Hi everybody, I have a question regarding changing the eMMC boot partition size. According the the JEDEC eMMC spec it is read-only (BOOT_SIZE_MULT register). But we still have mmc_boot_partition_size_change() in drivers/mmc/mmc_boot.c. It contains the comment /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ What is moviNAND? My research pointed me to Samsung products only. So is changing the boot partition size vendor specific or can it be used more generally? To be specific, I use the Kioxia THGBMJG6C1LBAB7 eMMC chip. Thanks and best regards, Philip Oberfichtner

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[PATCH v2] riscv: Fix detecting FPU support in standard extension
by Yu Chien Peter Lin 14 Nov '22

14 Nov '22

We should check the string until it hits underscore, in case it searches for the letters in the custom extension. For example, "rv64imac_xandes" will be treated as D extension support since there is a "d" in "andes", resulting illegal instruction caused by initializing FCSR. Signed-off-by: Yu Chien Peter Lin <peterlin(a)andestech.com> --- arch/riscv/cpu/cpu.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 52ab02519f..d34c8efce0 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -36,6 +36,7 @@ static inline bool supports_extension(char ext) #ifdef CONFIG_CPU struct udevice *dev; char desc[32]; + int i; uclass_find_first_device(UCLASS_CPU, &dev); if (!dev) { @@ -43,9 +44,16 @@ static inline bool supports_extension(char ext) return false; } if (!cpu_get_desc(dev, desc, sizeof(desc))) { - /* skip the first 4 characters (rv32|rv64) */ - if (strchr(desc + 4, ext)) - return true; + /* + * skip the first 4 characters (rv32|rv64) and + * check until underscore + */ + for (i = 4; i < sizeof(desc); i++) { + if (desc[i] == '_' || desc[i] == '\0') + break; + if (desc[i] == ext) + return true; + } } return false; -- 2.34.1

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[PATCH] efi_loader: add missing EFI_CALL when closing a file
by Ilias Apalodimas 14 Nov '22

14 Nov '22

Closing the files uses the EFI protocol and specifically it's .close callback. This needs to be wrapped on an EFI_CALL() Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- lib/efi_loader/efi_file.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 9e6c2b118900..750d380ad967 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -1131,7 +1131,7 @@ struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp) if (!EFI_DP_TYPE(fp, MEDIA_DEVICE, FILE_PATH)) { printf("bad file path!\n"); - f->close(f); + EFI_CALL(f->close(f)); return NULL; } -- 2.38.1

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[PATCH] efi_loader: replace a u16_strdup with alloc + memcpy
by Ilias Apalodimas 14 Nov '22

14 Nov '22

Heinrich reports that on RISC-V unaligned access is emulated by OpenSBI which is very slow. Performance wise it's better if we skip the calls to u16_strdup() -- which in turn calls u16_strsize() and just allocate/copy the memory directly. The access to dp.length may still be unaligned, but that's way less than what u16_strsize() would do Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- lib/efi_loader/efi_file.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 750d380ad967..ff731db6cb8c 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -1128,6 +1128,7 @@ struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp) container_of(fp, struct efi_device_path_file_path, dp); struct efi_file_handle *f2; u16 *filename; + size_t filename_sz; if (!EFI_DP_TYPE(fp, MEDIA_DEVICE, FILE_PATH)) { printf("bad file path!\n"); @@ -1140,9 +1141,14 @@ struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp) * protocol member functions to be aligned. So memcpy it * unconditionally */ - filename = u16_strdup(fdp->str); + if (fdp->dp.length <= offsetof(struct efi_device_path_file_path, str)) + return NULL; + filename_sz = fdp->dp.length - + offsetof(struct efi_device_path_file_path, str); + filename = calloc(1, filename_sz); if (!filename) return NULL; + memcpy(filename, fdp->str, filename_sz); EFI_CALL(ret = f->open(f, &f2, filename, EFI_FILE_MODE_READ, 0)); free(filename); -- 2.38.1

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[PATCH v8 0/5] eficonfig: add UEFI Secure Boot key maintenance interface
by Masahisa Kojima 14 Nov '22

14 Nov '22

This series adds the UEFI Secure Boot key maintenance interface to the eficonfig command. User can enroll PK, KEK, db and dbx. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/eficonfig_sbkey_v8 Masahisa Kojima (5): eficonfig: refactor file selection handling eficonfig: expose append entry function eficonfig: refactor change boot order implementation eficonfig: add UEFI Secure Boot Key enrollment interface eficonfig: add "Show Signature Database" menu entry cmd/Makefile | 5 + cmd/eficonfig.c | 201 ++++---- cmd/eficonfig_sbkey.c | 480 ++++++++++++++++++ include/efi_config.h | 12 +- .../py/tests/test_eficonfig/test_eficonfig.py | 1 + 5 files changed, 595 insertions(+), 104 deletions(-) create mode 100644 cmd/eficonfig_sbkey.c -- 2.17.1

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[PATCH 1/5] arm: socfpga: Add F2SDRAM_MANAGER base address
by Jit Loon Lim 13 Nov '22

13 Nov '22

From: Ley Foon Tan <ley.foon.tan(a)intel.com> HSD #1508586908-1: Add F2SDRAM Manager base address. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- .../include/mach/reset_manager_soc64.h | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2..ca5739c30c 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> */ #ifndef _RESET_MANAGER_SOC64_H_ @@ -12,15 +12,33 @@ void print_reset_info(void); void socfpga_bridges_reset(int enable); #define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_HDSKEN 0x10 +#define RSTMGR_SOC64_HDSKREQ 0x14 +#define RSTMGR_SOC64_HDSKACK 0x18 #define RSTMGR_SOC64_MPUMODRST 0x20 #define RSTMGR_SOC64_PER0MODRST 0x24 #define RSTMGR_SOC64_PER1MODRST 0x28 #define RSTMGR_SOC64_BRGMODRST 0x2c -#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 +#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0) +#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1) +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2) +#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3) +#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) +#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) +#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) + +#define BRGMODRST_SOC2FPGA_BRIDGES (RSTMGR_BRGMODRST_SOC2FPGA_MASK | \ + RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) +#define BRGMODRST_FPGA2SOC_BRIDGES (RSTMGR_BRGMODRST_FPGA2SOC_MASK | \ + RSTMGR_BRGMODRST_F2SDRAM0_MASK | \ + RSTMGR_BRGMODRST_F2SDRAM1_MASK | \ + RSTMGR_BRGMODRST_F2SDRAM2_MASK) + +#define RSTMGR_HDSKEN_FPGAHSEN BIT(2) +#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) /* SDM, Watchdogs and MPU warm reset mask */ #define RSTMGR_STAT_SDMWARMRST BIT(1) -- 2.26.2

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[PATCH 1/4] makefile: tools: socfpgaimage: update padding flow
by Jit Loon Lim 13 Nov '22

13 Nov '22

From: Ley Foon Tan <ley.foon.tan(a)intel.com> HSD #1508690657-2: The existing socfpgaimage always pads the image to the maximum size of OCRAM size. This will break in the encryption flow where it expects the image to be un-padded. The encryption tool will do the encryption for the whole image and append the signature key at end of the image. The signature key will append to beyond the size of OCRAM if the image is padded with the maximum size before encryption. Move the padding step from socfpgaimage to Makefile and pads with objcopy command. socfpgaimage will pad the image with 16 bytes aligned (including CRC word), this is a requirement in encryption flow. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- Makefile | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index ff25f92974..04914a8bec 100644 --- a/Makefile +++ b/Makefile @@ -1606,8 +1606,14 @@ spl/u-boot-splx4.sfp: spl/u-boot-spl.sfp FORCE $(call if_changed,gensplx4) quiet_cmd_socboot = SOCBOOT $@ -cmd_socboot = cat spl/u-boot-splx4.sfp u-boot.img > $@ || { rm -f $@; false; } -u-boot-with-spl.sfp: spl/u-boot-splx4.sfp u-boot.img FORCE +cmd_socboot = $(OBJCOPY) -I binary -O binary --gap-fill=0x0 \ + --pad-to=$(CONFIG_SPL_PAD_TO) \ + spl/u-boot-spl.sfp spl/u-boot-spl.sfp && \ + cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ + spl/u-boot-spl.sfp \ + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \ + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@ +u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) quiet_cmd_gensplpadx4 = GENSPLPADX4 $@ -- 2.26.2

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[PATCH 1/2] mach-snapdragon/mach-ipq40xx: fix, merge and refactoring
by Andrey Volkov 12 Nov '22

12 Nov '22

SoC: qcom: Add missing Qualcomm's SOCs definitions to the arch KConfig From: Andrey VOLKOV <andrey(a)volkov.fr> Add APQ8016/APQ8096/QCS40X decls to the KConfig, convert SDM845 declaration to the hidden one (selected by target), and update mach-snapdragon/Makefile accordingly. Also move 'CONFIG_ARM64' choice to the new declarations, since 'Snapdragon' contains Cortex A7A members too. Signed-off-by: Andrey VOLKOV <andrey(a)volkov.fr> --- arch/arm/Kconfig | 1 - arch/arm/mach-snapdragon/Kconfig | 23 +++++++++++++++++-- arch/arm/mach-snapdragon/Makefile | 31 ++++++++++++++----------- arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 2 +- drivers/reset/reset-qcom.c | 2 +- 5 files changed, 40 insertions(+), 19 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e83394052..a25b7f6d99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1098,7 +1098,6 @@ config ARCH_RMOBILE config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" - select ARM64 select DM select DM_GPIO select DM_SERIAL diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0927333306..83dd2c07a1 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,10 +9,27 @@ config SYS_MALLOC_F_LEN config SPL_SYS_MALLOC_F_LEN default 0x2000 +config APQ8016 + bool + select ARM64 + default n + +config APQ8096 + bool + select ARM64 + default n + config SDM845 - bool "Qualcomm Snapdragon 845 SoC" + bool + select ARM64 + select LINUX_KERNEL_IMAGE_HEADER default n + +config QCS40X + bool + select ARM64 select LINUX_KERNEL_IMAGE_HEADER + default n config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 @@ -23,6 +40,7 @@ choice config TARGET_DRAGONBOARD410C bool "96Boards Dragonboard 410C" select BOARD_LATE_INIT + select APQ8016 select ENABLE_ARM_SOC_BOOT0_HOOK help Support for 96Boards Dragonboard 410C. This board complies with @@ -37,6 +55,7 @@ config TARGET_DRAGONBOARD410C config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C" + select APQ8096 help Support for 96Boards Dragonboard 820C. This board complies with 96Board Open Platform Specifications. Features: @@ -71,7 +90,7 @@ config TARGET_STARQLTECHN config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" - select LINUX_KERNEL_IMAGE_HEADER + select QCS40X help Support for Qualcomm Technologies, Inc. QCS404 evaluation board. Features: diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index cbaaf23f6b..00997196ab 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,20 +2,23 @@ # # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> +obj-y += clock-snapdragon.o +obj-y += pinctrl-snapdragon.o + obj-$(CONFIG_SDM845) += clock-sdm845.o obj-$(CONFIG_SDM845) += sysmap-sdm845.o obj-$(CONFIG_SDM845) += init_sdm845.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-y += misc.o -obj-y += clock-snapdragon.o -obj-y += dram.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-apq8016.o -obj-y += pinctrl-apq8096.o -obj-y += pinctrl-qcs404.o -obj-y += pinctrl-sdm845.o -obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o -obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o + +obj-$(CONFIG_APQ8096) += clock-apq8096.o +obj-$(CONFIG_APQ8096) += sysmap-apq8096.o +obj-$(CONFIG_APQ8096) += pinctrl-apq8096.o + +obj-$(CONFIG_APQ8016) += clock-apq8016.o +obj-$(CONFIG_APQ8016) += sysmap-apq8016.o +obj-$(CONFIG_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_APQ8016) += misc.o dram.o + +obj-$(CONFIG_QCS40X) += clock-qcs404.o +obj-$(CONFIG_QCS40X) += sysmap-qcs404.o +obj-$(CONFIG_QCS40X) += pinctrl-qcs404.o diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index ab884ab6bf..4ed4ab4d4c 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -149,7 +149,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { { } }; -U_BOOT_DRIVER(pinctrl_snapdraon) = { +U_BOOT_DRIVER(pinctrl_snapdragon) = { .name = "pinctrl_msm", .id = UCLASS_PINCTRL, .of_match = msm_pinctrl_ids, diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 94315e76d5..2c61d6a6dc 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,7 +102,7 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { }; #endif -#ifdef CONFIG_TARGET_QCS404EVB +#ifdef CONFIG_QCS40X #include <dt-bindings/clock/qcom,gcc-qcs404.h> static const struct qcom_reset_map gcc_qcom_resets[] = { [GCC_GENI_IR_BCR] = { 0x0F000 },

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