November 2022 - U-Boot

Netgear RN102 U-Boot Nand Driver Modification
by Abdus Rainey 06 Jan '23

06 Jan '23

I have recently modded a Netgear RN102 NAND flash from 128 MB to 4096 MB (Samsung k9gbg08u0a) but i have a problem with NAND initialization. I can boot with kwboot which is unique for Armada CPU's. Here is my log from kwboot with my stock mtd0: root@whitepawnxeon:/home/jigsaw/Downloads# kwboot -t -B 115200 /dev/ttyUSB0 -b mtd0stockuboot.img -p Sending boot message. Please reboot the target...- Sending boot image... 0 % [......................................................................] 0 % [......................................................................] 1 % [......................................................................] 1 % [......................................................................] 2 % [......................................................................] 2 % [......................................................................] 3 % [......................................................................] 3 % [......................................................................] 4 % [......................................................................] 5 % [......... General initialization - Version: 1.0.0 High speed PHY - Version: 2.1.4 (COM-PHY-V20) Update PEX Device ID 0x6710 High speed PHY - Ended Successfully 0000 DDR3 Training Sequence - Ver 5.7.1 DDR3 Training Sequence - Run without PBS. DDR3 Training Sequence - Ended Successfully .............................................................] 5 % [......................................................................] 6 % [......................................................................] 6 % [......................................................................] 7 % [......................................................................] 7 % [......................................................................] 8 % [......................................................................] 9 % [......................................................................] 9 % [......................................................................] 10 % [......................................................................] 10 % [......................................................................] 11 % [......................................................................] 11 % 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| __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,52 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] As you can see u-boot sees device id and manufacturer id but cannot recognize it.My stock u-boot is very old and i get u-boot source code from Netgear GPL.(ReadyNASOS_V6.6.0_WW_src.zip) In here https://forum.doozan.com/read.php?2,106589,108204#msg-108204 you can see my whole story about this device. Can someone suggest any solution?

2 1

[PATCH 00/17] Support android boot image v3/v4
by Safae Ouajih 06 Jan '23

06 Jan '23

Hello everyone, * This is based on Roman Stratiienko's work to support boot image header version 3 and 4. * This supports the new boot image headers v3, v4 and bootconfig feature. https://source.android.com/docs/core/architecture/bootloader/boot-image-hea… https://source.android.com/docs/core/architecture/bootloader/implementing-b… - Tested on Amlogic Khadas vim3l, a reference board for Android Open Source Project https://www.khadas.com/vim3l And on AM625 Texas Instruments board with 5.10 linux kernel Main changes : - New partition : vendor boot, with a specific vendor ramdisk - DTB is stored in the vendor boot partition - The generic ramdisk is placed after the vendor ramdisk - Bootconfig feature support Here is a link to see the related android boot flow changes on KHADAS vim3l as an example: https://gitlab.baylibre.com/baylibre/amlogic/atv/u-boot/-/commits/souajih/B… Safae Ouajih (17): android: boot: rename andr_img_hdr -> andr_boot_img_hdr_v0_v1_v2 android: boot: support vendor boot image in abootimg android: boot: replace android_image_check_header android: boot: add boot image header v3 and v4 structures android: boot: add documentation for boot image header v3/v4 structure android: boot: kcomp: support andr_image_data android: boot: move to andr_image_data structure android: boot: content print is not supported for v3,v4 header version android: boot: boot image header v3,v4 do not support recovery DTBO android: boot: add vendor boot image to prepare for v3,v4 support android: boot: update android_image_get_data to support v3,v4 android: boot: ramdisk: support vendor ramdisk android: boot: support extra command line drivers: fastboot: zImage flashing is not supported for v3,v4 android: boot: support boot image header version 3 and 4 lib: support libxbc android: boot: support bootconfig boot/bootm.c | 29 ++- boot/image-android.c | 367 ++++++++++++++++++++++++++++++-------- boot/image-board.c | 15 +- boot/image-fdt.c | 5 +- cmd/abootimg.c | 66 ++++--- drivers/fastboot/fb_mmc.c | 19 +- include/android_image.h | 220 ++++++++++++++++++++++- include/image.h | 37 ++-- include/xbc.h | 1 + lib/Kconfig | 12 ++ lib/Makefile | 1 + lib/libxbc/Makefile | 1 + lib/libxbc/libxbc.c | 112 ++++++++++++ lib/libxbc/libxbc.h | 54 ++++++ 14 files changed, 806 insertions(+), 133 deletions(-) create mode 100644 include/xbc.h create mode 100644 lib/libxbc/Makefile create mode 100644 lib/libxbc/libxbc.c create mode 100644 lib/libxbc/libxbc.h -- 2.25.1

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[PATCH] rockchip: rk3328: Set VOP QoS to high priority
by Nicolas Frattaroli 05 Jan '23

05 Jan '23

The default priority for the quality of service for the video output results in unsightly glitches on the output whenever there is memory pressure on the system, which happens a lot. This sets the VOP QoS to high priority, which fixes this issue. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas(a)gmail.com> --- arch/arm/mach-rockchip/rk3328/rk3328.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index de17b88682..2373586b14 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -19,6 +19,8 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xFF100000 #define UART2_BASE 0xFF130000 #define FW_DDR_CON_REG 0xFF7C0040 +#define QOS_VOP_OFFSET 0xFF760080 +#define QOS_VOP_PRIORITY 0x8 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", @@ -54,6 +56,9 @@ int arch_cpu_init(void) /* Disable the ddr secure region setting to make it non-secure */ rk_setreg(FW_DDR_CON_REG, 0x200); +#else + printf("Setting VOP QoS\n"); + rk_setreg(QOS_VOP_OFFSET + QOS_VOP_PRIORITY, 0x2); #endif return 0; } -- 2.37.1

4 6

[PATCH 1/2] clk: Allow clk_get_by_name() with NULL name
by Samuel Holland 04 Jan '23

04 Jan '23

This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- drivers/clk/clk-uclass.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 2f9635524cf..bfacafb2eef 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -399,13 +399,14 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) { - int index; + int index = 0; debug("%s(node=%p, name=%s, clk=%p)\n", __func__, ofnode_get_name(node), name, clk); clk->dev = NULL; - index = ofnode_stringlist_search(node, "clock-names", name); + if (name) + index = ofnode_stringlist_search(node, "clock-names", name); if (index < 0) { debug("fdt_stringlist_search() failed: %d\n", index); return index; -- 2.37.4

3 5

[PATCH] clk: sunxi: Add an A31/A23/A33 legacy PRCM MFD driver
by Samuel Holland 04 Jan '23

04 Jan '23

When the CCU binding and driver for the PRCM were written, it seems the intention was to convert the A31 and A23/A33 devicetrees to use them. However, that never happened, so those SoCs still use the old binding, with an MFD for the PRCM, and separate DT nodes for clocks and resets. The specifier in the legacy clock/reset bindings is the register bit offset, so the drivers are trivial. Only the outer PRCM node has a reg property, so the clock/reset drivers use the parent device's MMIO base. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- I didn't reuse the sunxi gate/reset ops, because the driver is actually smaller without them. I tested this driver on an A33 tablet. drivers/clk/sunxi/Kconfig | 13 +++- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_sun6i_prcm.c | 104 +++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/sunxi/clk_sun6i_prcm.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index bf11fad6eef..759ef410b66 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -39,11 +39,20 @@ config CLK_SUN6I_A31 on Allwinner A31/A31s SoC. config CLK_SUN6I_A31_R - bool "Clock driver for Allwinner A31 generation PRCM" + bool "Clock driver for Allwinner A31 generation PRCM (CCU)" default SUNXI_GEN_SUN6I help This enables common clock driver support for the PRCM - in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs. + in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs using + the CCU binding. + +config CLK_SUN6I_PRCM + bool "Clock driver for Allwinner A31 generation PRCM (legacy)" + default MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 + help + This enables common clock driver support for the PRCM + in Allwinner A31/A31s/A23/A33 SoCs using the legacy PRCM + MFD binding. config CLK_SUN8I_A23 bool "Clock driver for Allwinner A23/A33" diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 895da02ebea..3266409cc7a 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o +obj-$(CONFIG_CLK_SUN6I_PRCM) += clk_sun6i_prcm.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o diff --git a/drivers/clk/sunxi/clk_sun6i_prcm.c b/drivers/clk/sunxi/clk_sun6i_prcm.c new file mode 100644 index 00000000000..488b47e77a7 --- /dev/null +++ b/drivers/clk/sunxi/clk_sun6i_prcm.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Samuel Holland <samuel(a)sholland.org> + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <reset-uclass.h> +#include <asm/io.h> +#include <linux/bitops.h> + +struct sun6i_prcm_plat { + void *base; +}; + +static int sun6i_prcm_set_field(struct udevice *dev, uint reg, + u32 mask, bool set) +{ + struct sun6i_prcm_plat *plat = dev_get_plat(dev->parent); + + clrsetbits_le32(plat->base + reg, mask, set ? mask : 0); + + return 0; +} + +static int sun6i_prcm_clk_enable(struct clk *clk) +{ + return sun6i_prcm_set_field(clk->dev, 0x28, BIT(clk->id), true); +} + +static int sun6i_prcm_clk_disable(struct clk *clk) +{ + return sun6i_prcm_set_field(clk->dev, 0x28, BIT(clk->id), false); +} + +static const struct clk_ops sun6i_prcm_clk_ops = { + .enable = sun6i_prcm_clk_enable, + .disable = sun6i_prcm_clk_disable, +}; + +static const struct udevice_id sun6i_prcm_clk_ids[] = { + { .compatible = "allwinner,sun6i-a31-apb0-gates-clk" }, + { .compatible = "allwinner,sun8i-a23-apb0-gates-clk" }, + { } +}; + +U_BOOT_DRIVER(sun6i_prcm_clk) = { + .name = "sun6i_prcm_clk", + .id = UCLASS_CLK, + .of_match = sun6i_prcm_clk_ids, + .ops = &sun6i_prcm_clk_ops, +}; + +static int sun6i_prcm_reset_assert(struct reset_ctl *reset) +{ + return sun6i_prcm_set_field(reset->dev, 0xb0, BIT(reset->id), false); +} + +static int sun6i_prcm_reset_deassert(struct reset_ctl *reset) +{ + return sun6i_prcm_set_field(reset->dev, 0xb0, BIT(reset->id), true); +} + +static const struct reset_ops sun6i_prcm_reset_ops = { + .rst_assert = sun6i_prcm_reset_assert, + .rst_deassert = sun6i_prcm_reset_deassert, +}; + +static const struct udevice_id sun6i_prcm_reset_ids[] = { + { .compatible = "allwinner,sun6i-a31-clock-reset" }, + { } +}; + +U_BOOT_DRIVER(sun6i_prcm_reset) = { + .name = "sun6i_prcm_reset", + .id = UCLASS_RESET, + .of_match = sun6i_prcm_reset_ids, + .ops = &sun6i_prcm_reset_ops, +}; + +static int sun6i_prcm_of_to_plat(struct udevice *dev) +{ + struct sun6i_prcm_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) + return -ENOMEM; + + return 0; +} + +static const struct udevice_id sun6i_prcm_mfd_ids[] = { + { .compatible = "allwinner,sun6i-a31-prcm" }, + { .compatible = "allwinner,sun8i-a23-prcm" }, + { } +}; + +U_BOOT_DRIVER(sun6i_prcm_mfd) = { + .name = "sun6i_prcm_mfd", + .id = UCLASS_SIMPLE_BUS, + .of_match = sun6i_prcm_mfd_ids, + .of_to_plat = sun6i_prcm_of_to_plat, + .plat_auto = sizeof(struct sun6i_prcm_plat), +}; -- 2.37.4

2 1

[PATCH 0/3] cmd: pxe: support INITRD and FDT selection with FIT
by Patrick Delaunay 03 Jan '23

03 Jan '23

Since the commit d5ba6188dfbf ("cmd: pxe_utils: Check fdtcontroladdr in label_boot") the FDT or the FDTDIR label is required in extlinux.conf and the fallback done by bootm command when only the device tree is present in this command parameters is no more performed when FIT is used for kernel. The next file "extlinux.conf" no more selects the device tree in FIT but use the pxe fallback with the device tree of U-Boot. menu title Select the boot mode DEFAULT test LABEL test KERNEL /fitImage This serie restores the possibility to use a FIT in extlinux.conf by using FDT label with the same string. menu title Select the boot mode DEFAULT test LABEL test KERNEL /fitImage FDT /fitImage even when a specific FIT config is used: menu title Select the boot mode DEFAULT test LABEL test KERNEL /fitImage#config FDT /fitImage#config The last commit of the series is only a minor improvement. Patrick Delaunay (3): cmd: pxe: reorder kernel treatment in label_boot cmd: pxe: support INITRD and FDT selection with FIT cmd: pxe: use strdup to copy config boot/pxe_utils.c | 69 +++++++++++++++++++++++++-------------------- doc/README.pxe | 8 ++++++ include/pxe_utils.h | 2 ++ 3 files changed, 49 insertions(+), 30 deletions(-) -- 2.25.1

6 19

[PATCH] powerpc: dts: keymile: Deduplicate binman code
by Pali Rohár 03 Jan '23

03 Jan '23

kmcent2-u-boot.dtsi file contains copy of powerpc u-boot.dtsi binman file. So remove code duplication and replace it by including u-boot.dtsi file. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/powerpc/dts/kmcent2-u-boot.dtsi | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index ab76a9f1226c..d0277627644b 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -74,24 +74,6 @@ compatible = "fsl,pcie-t104x"; law_trgt_if = <0>; }; - - binman { - filename = "u-boot-with-dtb.bin"; - skip-at-start = <CONFIG_SYS_TEXT_BASE>; - sort-by-offset; - pad-byte = <0xff>; - size = <CONFIG_SYS_MONITOR_LEN>; - - u-boot-with-ucode-ptr { - offset = <CONFIG_SYS_TEXT_BASE>; - optional-ucode; - }; - - u-boot-dtb-with-ucode { - align = <256>; - }; - powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; - }; - }; }; + +#include "u-boot.dtsi" -- 2.20.1

4 14

[PATCH 0/3] Initial support for Pinephone Pro
by Peter Robinson 03 Jan '23

03 Jan '23

This adds initial support for the PINE64 Pinephone Pro. It's a rebase to upstream core rk3399 DT pieces, and the addition of the upstream PPP DT from 6.1-rc1 and the U-Boot pieces are based on my work on the Pinebook Pro. Peter Robinson (3): arm64: dts: rk3399: sync rk3399.dtsi from 6.1-rc1 arm64: dts: rk3399: Add upstream Pinephone Pro dts rockchip: Add initial support for the PINE64 Pinephone Pro arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 39 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 398 ++++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 36 +- arch/arm/dts/rk3399.dtsi | 200 ++++++++- arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinephone-pro-rk3399/Makefile | 1 + .../pinephone-pro-rk3399.c | 76 ++++ configs/pinephone-pro-rk3399_defconfig | 104 +++++ drivers/clk/rockchip/clk_rk3399.c | 2 +- include/configs/pinephone-pro-rk3399.h | 19 + include/dt-bindings/clock/rk3399-cru.h | 24 +- include/dt-bindings/power/rk3399-power.h | 1 + 16 files changed, 875 insertions(+), 63 deletions(-) create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c create mode 100644 configs/pinephone-pro-rk3399_defconfig create mode 100644 include/configs/pinephone-pro-rk3399.h -- 2.38.1

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[PATCH 1/2] arm: mediatek: add mt8195 SOC support
by Macpaul Lin 02 Jan '23

02 Jan '23

From: Fabien Parent <fparent(a)baylibre.com> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. Signed-off-by: Fabien Parent <fparent(a)baylibre.com> Signed-off-by: Macpaul Lin <macpaul.lin(a)mediatek.com> --- MAINTAINERS | 2 + arch/arm/dts/mt8195.dtsi | 317 +++++++++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8195/Makefile | 3 + arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++ 6 files changed, 416 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt8195.dtsi create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile create mode 100644 arch/arm/mach-mediatek/mt8195/init.c diff --git a/MAINTAINERS b/MAINTAINERS index 1cf99c1393..5528dd28c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,8 +362,10 @@ ARM MEDIATEK M: Ryder Lee <ryder.lee(a)mediatek.com> M: Weijie Gao <weijie.gao(a)mediatek.com> M: Chunfeng Yun <chunfeng.yun(a)mediatek.com> +M: Macpaul Lin <macpaul.lin(a)mediatek.com> R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream(a)mediatek.com> S: Maintained +F: arch/arm/dts/mt8195.dtsi F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/ diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi new file mode 100644 index 0000000000..d28b038d57 --- /dev/null +++ b/arch/arm/dts/mt8195.dtsi @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Copyright (C) 2022 BayLibre, SAS + * Author: Ben Ho <ben.ho(a)mediatek.com> + * Erin Lo <erin.lo(a)mediatek.com> + * Fabien Parent <fparent(a)baylibre.com> + * Macpaul Lin <macpaul.lin(a)mediatek.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x002>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x003>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + mmc_source_clk: mmc-source-clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "mmc_source_clk"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt", + "mediatek,wdt"; + reg = <0 0x10007000 0 0x100>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + sysirq: interrupt-controller@c530a80 { + compatible = "mediatek,mt8195-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c530a80 0 0x50>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", + "mediatek,hsuart"; + reg = <0 0x11001100 0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <26000000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmc_source_clk>, + <&clk26m>, + <&clk26m>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + u3phy0: usb-phy@11f40000 { + compatible = "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "okay"; + + u2port0: usb-phy@0 { + reg = <0 0x700>; + clocks = <&clk26m>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&clk26m>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb: usb@11200000 { + compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x11200000 0 0x3e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + phys = <&u2port0 PHY_TYPE_USB2>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + ssusb: ssusb@11200000 { + compatible = "mediatek,ssusb"; + reg = <0 0x11200000 0 0x3e00>; + reg-names = "mac"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + xhci0: xhci@11200000 { + compatible = "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck"; + status = "disabled"; + }; + }; + + u3phy3: t-phy@11c50000 { + compatible = "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "okay"; + + u2port3: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + xhci3: xhci3@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port3 PHY_TYPE_USB2>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + usb2-lpm-disable; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 04aa2fd97f..3a2af1cdee 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -67,6 +67,15 @@ config TARGET_MT8183 SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. +config TARGET_MT8195 + bool "MediaTek MT8195 SoC" + select ARM64 + help + The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 + and LPDDR4 options. + config TARGET_MT8512 bool "MediaTek MT8512 M1 Board" select ARM64 @@ -105,6 +114,7 @@ config SYS_BOARD default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 + default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 + default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195 default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 default "lk=1" if TARGET_MT7623 diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index fc85293f71..fbbb5431d1 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ +obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile new file mode 100644 index 0000000000..886ab7e4eb --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c new file mode 100644 index 0000000000..1eb4ade6c5 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. + * Copyright (C) 2022 BayLibre, SAS + * Author: Macpaul Lin <macpaul.lin(a)mediatek.com> + * Author: Fabien Parent <fparent(a)baylibre.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <asm/system.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + return 0; +} + +int mtk_soc_early_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8195\n"); + return 0; +} + +static struct mm_region mt8195_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8195_mem_map; -- 2.18.0

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[PATCH] rockchip: rk3399: pass platform parameter to TF-A by default
by Quentin Schulz 02 Jan '23

02 Jan '23

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> Long are gone the times TF-A couldn't handle the FDT passed by U-Boot. Specifically, since commit e7b586987c0a ("rockchip: don't crash if we get an FDT we can't parse") in TF-A, failure to parse the FDT will use the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two years ago. Therefore, let's finally pass the FDT to TF-A so that it can get the serial configuration from U-Boot FDT instead of requiring the user to patch TF-A hardcoded fallback values. Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- rockchip: rk3399: pass platform parameter to TF-A Finally pass the FDT address to TF-A since it now gracefully fallbacks to hardcoded defaults if it cannot parse it. This allows us to avoid modifying hardcoded values in TF-A to enable the console. This was tested with TF-A v2.7.0 on Puma Haikou RK3399. To: Simon Glass <sjg(a)chromium.org> To: Philipp Tomsich <philipp.tomsich(a)vrull.eu> To: Kever Yang <kever.yang(a)rock-chips.com> Cc: Hugh Cole-Baker <sigmaris(a)gmail.com> Cc: Walter Lozano <walter.lozano(a)collabora.com> Cc: u-boot(a)lists.denx.de --- arch/arm/mach-rockchip/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 69d51ff378..2fcc23f9fa 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -249,7 +249,6 @@ config ROCKCHIP_RK3399 imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL imply TPL_LIBCOMMON_SUPPORT --- base-commit: 0cbeed4f6648e0e4966475e3544280a69ecb59d3 change-id: 20221114-rk3399-tf-a-plat-param-3ab055f40b9e Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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