October 2022 - U-Boot

[PATCH 0/6] sunxi: improve F1C200s support
by Andre Przywara 20 Oct '22

20 Oct '22

The Allwinner F1C200s is reportedly the same chip as the F1C100s, just with twice the amount of co-packaged DRAM: 64MB instead of just 32MB. U-Boot's F1C100 platform supported this quite naturally (since the DRAM size is auto-detected), but those better chips do not need to suffer from the same memory constraints as their smaller siblings. Patch 1/6 adds a notion of "minimum DRAM size" to Kconfig, so that we can select those smaller sizes independently from the actual SoC. This makes it easy to let the F1C200s use a more generous memory map, but also paves the way for the T113-S3 and D1s, later. Patch 2/6 uses the opportunity to improve the 32MB memory map, which was not really practical, and arguably also somewhat buggy. Patch 3/6 helps to keep the _defconfig files small, while patch 4+5 add support for the console on UART1. The final patch then adds a defconfig and .dts file for the CherryPi F1C200s board, which is used as an example for a F1C200s board. Please have a look and test, if possible. Cheers, Andre Andre Przywara (6): sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MB sunxi: fix 32MB load address layout sunxi: f1c100: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig sunxi: f1c100: add UART1 support sunxi: f1c100: dtsi: add UART1 pins sunxi: add CherryPi-F1C200s support Kconfig | 6 +-- .../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++ arch/arm/dts/suniv-f1c100s.dtsi | 5 ++ arch/arm/mach-sunxi/Kconfig | 14 ++++++ arch/arm/mach-sunxi/board.c | 4 ++ boot/Kconfig | 4 +- configs/cherrypi_f1c200s_defconfig | 11 +++++ configs/licheepi_nano_defconfig | 2 - drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + include/configs/sunxi-common.h | 49 ++++++++++--------- 10 files changed, 111 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig -- 2.25.1

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[PATCH v14 00/15] FWU: Add FWU Multi Bank Update feature support
by Sughosh Ganu 20 Oct '22

20 Oct '22

The patchset adds support for the FWU Multi Bank Update[1] feature. Certain aspects of the Dependable Boot[2] specification have also been implemented. The FWU multi bank update feature is used for supporting multiple sets(also called banks) of firmware image(s), allowing the platform to boot from a different bank, in case it fails to boot from the active bank. This functionality is supported by keeping the relevant information in a structure called metadata, which provides information on the images. Among other parameters, the metadata structure contains information on the currect active bank that is being used to boot image(s). Functionality is being added to work with the UEFI capsule driver in u-boot. The metadata is read to gather information on the update bank, which is the bank to which the firmware images would be flashed to. On a successful completion of the update of all components, the active bank field in the metadata is updated, to reflect the bank from which the platform will boot on the subsequent boots. Currently, the feature is being enabled on the STM32MP157C-DK2 and Synquacer boards. The DK2 board boots a FIP image from a uSD card partitioned with the GPT partioning scheme, while the Synquacer board boots a FIP image from a MTD partitioned SPI NOR flash device. This feature also requires changes in a previous stage of bootloader, which parses the metadata and selects the bank to boot the image(s) from. Support has being added in tf-a(BL2 stage) for the STM32MP157C-DK2 board to boot the active bank images. These changes have been merged to the upstream tf-a repository. The patch for adding a python test for the feature has been developed, and was sent in the version 5 of the patches[3]. However, the test script depends on adding support for the feature on MTD SPI NOR devices, and that is being done as part of the Synquacer patches. Hence these set of patches do not have the test script for the feature. That will be added through the patches for adding support for the feauture on Synquacer platform. [1] - https://developer.arm.com/documentation/den0118/a [2] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24… [3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html Changes since V13: * Move the implementation of fwu_gpt_mdata_check() to a common function, fwu_check_mdata_validity() * Add additional API's needed for implementing the above function, fwu_get_mdata_part_num(), fwu_read_mdata_partition() and fwu_write_mdata_partition() * Move the implementation of fwu_gpt_mdata_check() to a common function, fwu_check_mdata_validity() * Add GPT implementations for fwu_get_mdata_part_num(), fwu_read_mdata_partition() and fwu_write_mdata_partition() * Call gpt_read_write_mdata() directly instead of calling through gpt_read_mdata() and gpt_write_mdata_partition() * Add a node for the ev1 board as suggested by Etienne * Removed the superfluous setting of var_attributes before calling efi_get_variable_int() * Call fwu_get_dev_mdata() in fwu_trial_state_check() instead of fwu_boottime_checks() * Add a check for the accept capsule in fwu_empty_capsule_process() as suggested by Ilias * Return EFI_NOT_FOUND instead of EFI_DEVICE_ERROR for -ENODEV * Call fwu_check_mdata_validity() instead of fwu_mdata_check() * Use uclass_first_device_err() to get the FWU metadata device * Call fwu_check_mdata_validity() instead of fwu_mdata_check() Sughosh Ganu (15): dt/bindings: Add bindings for GPT based FWU Metadata storage device FWU: Add FWU metadata structure and driver for accessing metadata FWU: Add FWU metadata access driver for GPT partitioned block devices stm32mp1: Add a node for the FWU metadata device stm32mp1: Add image information for capsule updates FWU: Add helper functions for accessing FWU metadata FWU: STM32MP1: Add support to read boot index from backup register event: Add an event for main_loop FWU: Add boot time checks as highlighted by the FWU specification FWU: Add support for the FWU Multi Bank Update feature FWU: cmd: Add a command to read FWU metadata test: dm: Add test cases for FWU Metadata uclass mkeficapsule: Add support for generating empty capsules mkeficapsule: Add support for setting OEM flags in capsule header FWU: doc: Add documentation for the FWU feature arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 7 + arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 5 + arch/arm/mach-stm32mp/include/mach/stm32.h | 5 + arch/sandbox/Kconfig | 6 + arch/sandbox/dts/test.dts | 7 +- board/sandbox/sandbox.c | 8 + board/st/stm32mp1/stm32mp1.c | 39 + cmd/Kconfig | 6 + cmd/Makefile | 1 + cmd/fwu_mdata.c | 79 ++ common/board_r.c | 3 + common/event.c | 3 + configs/sandbox64_defconfig | 5 +- doc/develop/uefi/fwu_updates.rst | 184 +++++ doc/develop/uefi/index.rst | 1 + doc/develop/uefi/uefi.rst | 12 + .../firmware/fwu-mdata-gpt.yaml | 32 + doc/mkeficapsule.1 | 33 +- doc/usage/cmd/fwu_mdata.rst | 43 ++ doc/usage/index.rst | 1 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/fwu-mdata/Kconfig | 16 + drivers/fwu-mdata/Makefile | 8 + drivers/fwu-mdata/fwu-mdata-uclass.c | 178 +++++ drivers/fwu-mdata/gpt_blk.c | 288 +++++++ include/configs/stm32mp15_common.h | 4 + include/dm/uclass-id.h | 1 + include/event.h | 3 + include/fwu.h | 391 ++++++++++ include/fwu_mdata.h | 67 ++ lib/Kconfig | 6 + lib/Makefile | 1 + lib/efi_loader/efi_capsule.c | 212 +++++- lib/efi_loader/efi_firmware.c | 14 + lib/fwu_updates/Kconfig | 33 + lib/fwu_updates/Makefile | 7 + lib/fwu_updates/fwu.c | 703 ++++++++++++++++++ lib/fwu_updates/fwu_gpt.c | 123 +++ test/dm/Makefile | 1 + test/dm/fwu_mdata.c | 147 ++++ test/dm/fwu_mdata_disk_image.h | 112 +++ .../test_capsule_firmware_fit.py | 1 - .../test_capsule_firmware_signed_fit.py | 1 - tools/Makefile | 4 +- tools/eficapsule.h | 8 + tools/mkeficapsule.c | 109 ++- 47 files changed, 2899 insertions(+), 22 deletions(-) create mode 100644 cmd/fwu_mdata.c create mode 100644 doc/develop/uefi/fwu_updates.rst create mode 100644 doc/device-tree-bindings/firmware/fwu-mdata-gpt.yaml create mode 100644 doc/usage/cmd/fwu_mdata.rst create mode 100644 drivers/fwu-mdata/Kconfig create mode 100644 drivers/fwu-mdata/Makefile create mode 100644 drivers/fwu-mdata/fwu-mdata-uclass.c create mode 100644 drivers/fwu-mdata/gpt_blk.c create mode 100644 include/fwu.h create mode 100644 include/fwu_mdata.h create mode 100644 lib/fwu_updates/Kconfig create mode 100644 lib/fwu_updates/Makefile create mode 100644 lib/fwu_updates/fwu.c create mode 100644 lib/fwu_updates/fwu_gpt.c create mode 100644 test/dm/fwu_mdata.c create mode 100644 test/dm/fwu_mdata_disk_image.h -- 2.34.1

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[PATCH 0/2] ke-am62x-sk_evm: add ospi support
by Dhruva Gole 20 Oct '22

20 Oct '22

There's a S28HS512T Flash (by Cypress) on the AM625 SK EVM. - Add necessary DT nodes to enable OSPI interface with this flash. - Enable all configs that enable the OSPI related drivers and commands like SF probe. Tested on my AM62 SK EVM, attaching logs below. Logs: ------------------------------------------------------------------------ U-Boot SPL 2022.10-rc5-00012-g435596d57f8b-dirty (Sep 26 2022 - 16:27:48 +0530) SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.6--v08.04.06 (Jolly Jellyfi') Trying to boot from MMC2 Starting ATF on ARM64 core... NOTICE: BL31: v2.7(release):v2.7.0-dirty NOTICE: BL31: Built : 14:30:02, Aug 27 2022 U-Boot SPL 2022.10-rc5-00012-g435596d57f8b-dirty (Sep 26 2022 - 17:51:27 +0530) SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.6--v08.04.06 (Jolly Jellyfi') Trying to boot from MMC2 U-Boot 2022.10-rc5-00012-g435596d57f8b-dirty (Sep 26 2022 - 17:51:27 +0530) SoC: AM62X SR1.0 GP Model: Texas Instruments AM625 SK DRAM: 2 GiB Core: 37 devices, 18 uclasses, devicetree: separate MMC: mmc@fa10000: 2, mmc@fa00000: 1, mmc@fa20000: 3 Loading Environment from nowhere... OK In: serial@2800000 Out: serial@2800000 Err: serial@2800000 Net: No ethernet found. Hit any key to stop autoboot: 0 => sf probe SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB => fatload mmc 1 $loadaddr tiboot3.bin 285482 bytes read in 17 ms (16 MiB/s) => sf update $loadaddr 0x0 $filesize device 0 offset 0x0, size 0x45b2a 285482 bytes written, 0 bytes skipped in 2.623s, speed 111322 B/s => sf read 0x90000000 0x0 $filesize device 0 offset 0x0, size 0x45b2a SF: 285482 bytes @ 0x0 Read: OK => md $loadaddr 82000000: 94048230 fd038230 010203a0 64140202 0...0..........d 82000010: 3f829a45 85bb6dd8 232b5568 f8f4176f E..?.m..hU+#o... 82000020: 309fb7ff 2a09060d f7864886 0d01010d ...0...*.H...... 82000030: 81300005 300b319d 55030609 02130604 ..0..1.0...U.... 82000040: 0b315355 03060930 0c080455 31585402 US1.0...U....TX1 82000050: 060d300f 07045503 6144060c 73616c6c .0...U....Dallas 82000060: 25302731 04550306 541e0c0a 73617865 1'0%..U....Texas 82000070: 736e4920 6d757274 73746e65 636e4920 Instruments Inc 82000080: 6f70726f 65746172 30133164 55030611 orporated1.0...U 82000090: 0a0c0b04 636f7250 6f737365 13317372 ....Processors1. 820000a0: 03061130 0c030455 2049540a 70707553 0...U....TI Supp 820000b0: 3174726f 061b301d 48862a09 010df786 ort1.0...*.H.... 820000c0: 0e160109 70707573 4074726f 632e6974 ....support(a)ti.c 820000d0: 1e306d6f 32320d17 36323930 38353031 om0...2209261058 820000e0: 175a3331 3132320d 31363230 31383530 13Z..22102610581 820000f0: 81305a33 300b319d 55030609 02130604 3Z0..1.0...U.... => md 0x90000000 90000000: 94048230 fd038230 010203a0 64140202 0...0..........d 90000010: 3f829a45 85bb6dd8 232b5568 f8f4176f E..?.m..hU+#o... 90000020: 309fb7ff 2a09060d f7864886 0d01010d ...0...*.H...... 90000030: 81300005 300b319d 55030609 02130604 ..0..1.0...U.... 90000040: 0b315355 03060930 0c080455 31585402 US1.0...U....TX1 90000050: 060d300f 07045503 6144060c 73616c6c .0...U....Dallas 90000060: 25302731 04550306 541e0c0a 73617865 1'0%..U....Texas 90000070: 736e4920 6d757274 73746e65 636e4920 Instruments Inc 90000080: 6f70726f 65746172 30133164 55030611 orporated1.0...U 90000090: 0a0c0b04 636f7250 6f737365 13317372 ....Processors1. 900000a0: 03061130 0c030455 2049540a 70707553 0...U....TI Supp 900000b0: 3174726f 061b301d 48862a09 010df786 ort1.0...*.H.... 900000c0: 0e160109 70707573 4074726f 632e6974 ....support(a)ti.c 900000d0: 1e306d6f 32320d17 36323930 38353031 om0...2209261058 900000e0: 175a3331 3132320d 31363230 31383530 13Z..22102610581 900000f0: 81305a33 300b319d 55030609 02130604 3Z0..1.0...U.... => cmp.b $loadaddr 0x90000000 $filesize Total of 285482 byte(s) were the same ------------------------------------------------------------------------ Thus tested read, write and probe flash from u-boot prompt Dhruva Gole (2): arm: dts: k3-am625-sk: Add OSPI support configs: am62x_evm_a53: Enable OSPI Flash support arch/arm/dts/k3-am625-sk-u-boot.dtsi | 24 +++++++++ arch/arm/dts/k3-am625-sk.dts | 77 ++++++++++++++++++++++++++++ configs/am62x_evm_a53_defconfig | 13 +++++ 3 files changed, 114 insertions(+) -- 2.25.1

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[PATCH v2] riscv: ae350: Check firmware_fdt_addr header
by Rick Chen 20 Oct '22

20 Oct '22

Check firmware_fdt_addr header to see if it is a valid fdt blob. Signed-off-by: Rick Chen <rick(a)andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang(a)andestech.com> --- board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 36f0dd4b0f..08d0c6b264 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -60,7 +60,7 @@ void *board_fdt_blob_setup(int *err) *err = 0; if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (gd->arch.firmware_fdt_addr) + if (fdt_magic((void *)gd->arch.firmware_fdt_addr) == FDT_MAGIC) return (void *)(ulong)gd->arch.firmware_fdt_addr; } -- 2.18.0

1 0

[PATCH 0/4] Update Microchip PolarFire SoC
by Padmarao Begari 20 Oct '22

20 Oct '22

This patch set updates Microchip PolarFire SoC Icicle Kit support of RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://source.denx.de/u-boot/u-boot) at commit id 3724ddf157aab3bd009c1da234b9a1af1621b544 The memory device node is updated in the device tree based on the latest FPGA reference design and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, add Microchip QSPI driver. Padmarao Begari (4): riscv: dts: update memory configuration riscv: dts: Add QSPI NAND device node riscv: Update Microchip MPFS Icicle Kit support spi: Add Microchip PolarFire SoC QSPI driver arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 85 ++-- board/microchip/mpfs_icicle/Kconfig | 7 + configs/microchip_mpfs_icicle_defconfig | 1 + drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/microchip_qspi.c | 504 +++++++++++++++++++ 6 files changed, 548 insertions(+), 56 deletions(-) create mode 100644 drivers/spi/microchip_qspi.c -- 2.25.1

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[PATCH 0/1] imx8m: ddr_init: fix reading of DDR4 MR registers
by Ying-Chun Liu (PaulLiu) 20 Oct '22

20 Oct '22

Accorting to commit 290ffe57886271a6 we need to read more significant bytes to get a non-zero value. However commit 7e9bd84883aeb1e2 removes it by accident. Thus we add the changes back. This is needed to let imx8mm-cl-iot-gate to boot correctly. Ying-Chun Liu (PaulLiu) (1): imx8m: ddr_init: fix reading of DDR4 MR registers drivers/ddr/imx/imx8m/ddr_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1

2 2

[PATCH v2] clk: update clk_clean_rate_cache to use private clk struct
by Patrick Delaunay 20 Oct '22

20 Oct '22

In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- Changes in v2: - set *clkp = clk when CCF is not activated and when the clock is not found drivers/clk/clk-uclass.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf794..5cfa022a6dc 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -544,6 +544,19 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_get_priv(struct clk *clk, struct clk **clkp) +{ + *clkp = clk; + + /* get private clock struct associated to the provided clock */ + if (CONFIG_IS_ENABLED(CLK_CCF)) { + /* Take id 0 as a non-valid clk, such as dummy */ + if (clk->id) + clk_get_by_id(clk->id, clkp); + } +} + +/* clean cache, called with private clock struct */ static void clk_clean_rate_cache(struct clk *clk) { struct udevice *child_dev; @@ -563,6 +576,7 @@ static void clk_clean_rate_cache(struct clk *clk) ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; + struct clk *clkp; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); if (!clk_valid(clk)) @@ -572,8 +586,10 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* get private clock struct used for cache */ + clk_get_priv(clk, &clkp); /* Clean up cached rates for us and all child clocks */ - clk_clean_rate_cache(clk); + clk_clean_rate_cache(clkp); return ops->set_rate(clk, rate); } -- 2.25.1

3 2

[PATCH] rockchip: clk: pll: Fix constant typo
by Michal Suchanek 20 Oct '22

20 Oct '22

Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/clk/rockchip/clk_pll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 8d2aaf5b84..09b97cf57a 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table; #define RK3036_PLLCON1_DSMPD_SHIFT 12 #define RK3036_PLLCON2_FRAC_MASK 0xffffff #define RK3036_PLLCON2_FRAC_SHIFT 0 -#define RK3036_PLLCON1_PWRDOWN_SHIT 13 +#define RK3036_PLLCON1_PWRDOWN_SHIFT 13 #define MHZ 1000000 #define KHZ 1000 @@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power down */ rk_setreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); rk_clrsetreg(base + pll->con_offset, (RK3036_PLLCON0_POSTDIV1_MASK | @@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power Up */ rk_clrreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); /* waiting for pll lock */ while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) -- 2.37.3

2 1

[PATCH] clk: change return type of clk_get_parent_rate from long long to ulong
by Michal Suchanek 20 Oct '22

20 Oct '22

All functions getting and setting clock rate use ulong for rate, only clk_get_parent_rate is an exception. Change the return value to match other clock rate funcrions. Most users directly assign the rate to unsigned long anyway, and the few users that use u64 (not s64) multiply the rate so they may need the extra bits for the result in their use case. Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/clk/clk-uclass.c | 2 +- include/clk.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf79..4678ed43af 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -505,7 +505,7 @@ struct clk *clk_get_parent(struct clk *clk) return pclk; } -long long clk_get_parent_rate(struct clk *clk) +ulong clk_get_parent_rate(struct clk *clk) { const struct clk_ops *ops; struct clk *pclk; diff --git a/include/clk.h b/include/clk.h index 76bb64bb5e..41a8fb3419 100644 --- a/include/clk.h +++ b/include/clk.h @@ -444,7 +444,7 @@ struct clk *clk_get_parent(struct clk *clk); * * Return: clock rate in Hz, or -ve error code. */ -long long clk_get_parent_rate(struct clk *clk); +ulong clk_get_parent_rate(struct clk *clk); /** * clk_round_rate() - Adjust a rate to the exact rate a clock can provide @@ -577,7 +577,7 @@ static inline struct clk *clk_get_parent(struct clk *clk) return ERR_PTR(-ENOSYS); } -static inline long long clk_get_parent_rate(struct clk *clk) +static inline ulong clk_get_parent_rate(struct clk *clk) { return -ENOSYS; } -- 2.37.3

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[PATCH v17 0/2] add TCP and HTTP for downloading images
by Ying-Chun Liu (PaulLiu) 19 Oct '22

19 Oct '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> This patch is a refresh from previous patches made by Duncan Hare <DuncanCHare at yahoo.com>. I've contacted him and continue to work on this patch. This patch introduce a TCP stack with SACK. And a simple wget command to download images from http server. v1-v12: Made by Duncan, didn't tracked. v13: Fix some issues which is reviewed by Christian v14: Add options to enable/disable SACK. v15: Fix various syntax errors reviewed by Michal. Remove magic numbers. Use kernel-doc format. v16: Add more kernel-doc. Fix more double spaces. v17: Fix wget with address timeout issue reported by Ramon. Ying-Chun Liu (PaulLiu) (2): net: Add TCP protocol net: Add wget application cmd/Kconfig | 7 + cmd/net.c | 13 + include/net.h | 38 ++- include/net/tcp.h | 312 ++++++++++++++++++++ include/net/wget.h | 22 ++ net/Kconfig | 16 + net/Makefile | 2 + net/net.c | 36 +++ net/tcp.c | 720 +++++++++++++++++++++++++++++++++++++++++++++ net/wget.c | 428 +++++++++++++++++++++++++++ 10 files changed, 1584 insertions(+), 10 deletions(-) create mode 100644 include/net/tcp.h create mode 100644 include/net/wget.h create mode 100644 net/tcp.c create mode 100644 net/wget.c -- 2.35.1

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