January 2022 - U-Boot

[v2] board: ls1088a: update ifc node name to be memory-controller
by Jianpeng Bu 19 Jan '22

19 Jan '22

IFC-NOR and QSPI are muxed on SoC. So disable IFC node in dts if QSPI is enabled or disable QSPI node in dts in case QSPI is not enabled. "ifc/nor" will be changed to "memory-controller/nor" in linux. So need to modify "ifc/nor" to "memory-controller/nor" in fdt_path_offset(). Signed-off-by: Jianpeng Bu <jianpeng.bu(a)nxp.com> --- Changes for v2: - Modified commit message. --- board/freescale/ls1088a/ls1088a.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f5dc449d89..7b5f8d2486 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2021 NXP */ #include <common.h> #include <env.h> @@ -923,10 +923,10 @@ void fsl_fdt_fixup_flash(void *fdt) } if (disable_ifc) { - offset = fdt_path_offset(fdt, "/soc/ifc/nor"); + offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); if (offset < 0) - offset = fdt_path_offset(fdt, "/ifc/nor"); + offset = fdt_path_offset(fdt, "/memory-controller/nor"); } else { offset = fdt_path_offset(fdt, "/soc/quadspi"); @@ -936,10 +936,10 @@ void fsl_fdt_fixup_flash(void *fdt) #else #ifdef CONFIG_FSL_QSPI - offset = fdt_path_offset(fdt, "/soc/ifc/nor"); + offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); if (offset < 0) - offset = fdt_path_offset(fdt, "/ifc/nor"); + offset = fdt_path_offset(fdt, "/memory-controller/nor"); #else offset = fdt_path_offset(fdt, "/soc/quadspi"); -- 2.25.1

1 0

[PATCH 1/1] miiphy.h: Remove CONFIG_DM_xxx guards
by Tom Rini 18 Jan '22

18 Jan '22

Function prototypes must not be guarded with ifdef tests. Doing so prevents us from doing: if (CONFIG_IS_ENABLED(FOO)) func(); as that results in a warning when CONFIG_FOO is not enabled. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- I forgot that I had this applied when pushing before, as it's required by the aspeed mii changes. include/miiphy.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/miiphy.h b/include/miiphy.h index 8b77bac01e6a..77a00359587b 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -126,8 +126,6 @@ int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, #define ESTATUS_1000XF 0x8000 #define ESTATUS_1000XH 0x4000 -#ifdef CONFIG_DM_MDIO - /** * struct mdio_perdev_priv - Per-device class data for MDIO DM * @@ -185,10 +183,6 @@ struct phy_device *dm_mdio_phy_connect(struct udevice *mdiodev, int phyaddr, */ struct phy_device *dm_eth_phy_connect(struct udevice *ethdev); -#endif - -#ifdef CONFIG_DM_MDIO_MUX - /* indicates none of the child buses is selected */ #define MDIO_MUX_SELECT_NONE -1 @@ -206,5 +200,3 @@ struct mdio_mux_ops { #define mdio_mux_get_ops(dev) ((struct mdio_mux_ops *)(dev)->driver->ops) #endif - -#endif -- 2.25.1

1 0

[next 0/5] Add support of Ethernet for Aspeed AST2600 SoC
by Dylan Hung 18 Jan '22

18 Jan '22

This patch series adds support of Ethernet for Aspeed AST2600 SoC. There are 4 MAC controllers (ftgmac100) in AST2600 that can support 10/100/1000T Ethernet. 4 MDIO controllers are used to connect to PHY chips. The MDIO controller has stand-alone hardware block so we introduce DM_MDIO so that we can use external MDIO driver (aspeed_mdio) instead of integrated MDIO drier in ftgmac100.c. The patch series also revises the MII interface delay for better RMII/RGMII timing margin. Dylan Hung (5): net: ftgmac100: Add DM_MDIO support net: ftgmac100: Add Aspeed AST2600 support ARM: dts: ast2600: Add MDIO devices configs: ast2600: enable DM_MDIO and MDIO driver clk: ast2600: Revise MII interface delay arch/arm/dts/ast2600-evb.dts | 68 ++++++++++++++++++++++++++++++++ arch/arm/dts/ast2600.dtsi | 46 ++++++++++++++++++--- configs/evb-ast2600_defconfig | 2 + drivers/clk/aspeed/clk_ast2600.c | 10 ++--- drivers/net/ftgmac100.c | 21 +++++++--- 5 files changed, 132 insertions(+), 15 deletions(-) -- 2.25.1

3 15

[PATCH v4 0/6] Add MMC/SD support for S700/S900
by Amit Singh Tomar 18 Jan '22

18 Jan '22

Hi, Sorry, it took me some time to come up with v4. For v3, all the comments are from MMC driver(patch 5/6), and tried to address in this series(v4) with changelog mentioned in the patch (5/6) itself. -------------------------------------------------------- This series(v3) addresses review comments provided by Andre and Jaehoon. Earlier in MMC driver, we were *not* checking the command response errors(for instance, the CRC error) based on STATU register. This is now addressed in patch 5/6. Also, MMC driver(patch 5/6) now has replaced the switch/case with if/else to correlate MMC_RSP_Rx bitmask values with register bits as suggested by Andre. Apart from it, there are changes in patch 2/6 to fix weird assignments to div variable. ---------------------------------------------------------------------------------- Series(v2) has few important updates, while loading large files we found that MMC framework puts "0x1fffe00" into DMA Frame Length(DMA_FRAME_LEN 0x000C) but register itself is limited to 24 bits and hence it was failing. It is due to the wrong Block count(cfg->b_max) used in driver, that should be just 512. This is now fixed in patch 5/6. Apart from it, as Andre pointed that we might be just overclocking the MMC/SD clock, and to confirm this we run following test: $ md5sum clang 349eac46cbbe28f8e44da2dce07fa7b7 clang U-Boot => ext4load mmc 0:2 0x0 clang 503316480 bytes read in 19516 ms (24.6 MiB/s) U-Boot => md5sum 0x0 0x1e000000 md5 for 00000000 ... 1dffffff ==> d793bb51c4a1cf83c96d1980927461ff Even though file gets loaded but md5sum doesn't match. This is now fixed in patch 2/6 U-Boot => ext4load mmc 0:2 0x0 clang 503316480 bytes read in 41524 ms (11.6 MiB/s) U-Boot => md5sum 0x0 0x1e000000 md5 for 00000000 ... 1dffffff ==> 349eac46cbbe28f8e44da2dce07fa7b7 ----------------------------------------------------------------------------- At the moment on S700 based platforms, only way to load/boot the Kernel is from Ethernet, and with these patches one can now load/boot the Kernel from uSD card. Patches(1/6 and 2/6) adds changes needed for MMC/SD clock. It introduces set/get callback routine and get/set MMC/SD clock rate based on device id. Patch 4/6 adds MMC/SD node in U-boot specific dtsi file, which is used by MMC/SD driver to read controller base address later on. Patch 5/6 adds driver for MMC/SD controller present on S700 SoC, and its based on Mainline Linux driver and DMA related bits is picked and simpilified from vendor source. Final patch 6/6 enables the driver support along with MMC commands in Cubieboard7 config file. Also, while at it just took the opportunity to synchronize the S700 SoC DT with Linux in patch 3/6. This patch-set is tested on Cubieboard7-lite board with following results: U-Boot 2021.01-rc1-04434-g6589149-dirty (Dec 13 2020 - 13:51:07 +0530) cubieboard7 DRAM: 1 GiB PSCI: v0.2 MMC: mmc@e0210000: 0 In: serial@e0126000 Out: serial@e0126000 Err: serial@e0126000 Net: eth0: ethernet@e0220000 Hit any key to stop autoboot: 0 U-Boot => U-Boot => U-Boot => U-Boot => mmc info Device: mmc@e0210000 Manufacturer ID: 3 OEM: 5344 Name: SC16G Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.8 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes U-Boot => setenv bootargs console=ttyOWL3,115200n8 earlycon=owl,0xe0126000 init=/sbin/init root=/dev/mmcblk0p2 rw rootwait U-Boot => setenv kernel_addr_r 0x80000;setenv fdt_addr_r 0x10000000; U-Boot => fatload mmc 0:1 ${kernel_addr_r} image ;fatload mmc 0:1 ${fdt_addr_r} s700-cubieboard7.dtb 27480576 bytes read in 1041 ms (25.2 MiB/s) 7056 bytes read in 2 ms (3.4 MiB/s) U-Boot => booti $kernel_addr_r - $fdt_addr_r ## Flattened Device Tree blob at 10000000 Booting using the fdt blob at 0x10000000 Loading Device Tree to 000000003df56000, end 000000003df5ab8f ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 5.7.0-rc6-00022-g99f1c330923b-dirty (amit@amit-ThinkPad-X230) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05), GNU ld (GNU Binutils for Ubuntu) 2.26.1) #474 SMP PREEMPT Thu Aug 13 15:27:10 IST 2020 [ 0.000000] Machine model: CubieBoard7 [ 0.000000] earlycon: owl0 at MMIO 0x00000000e0126000 (options '') [ 0.000000] printk: bootconsole [owl0] enabled [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 32 MiB at 0x000000003e000000 Amit Singh Tomar (6): clk: actions: Introduce dummy get/set_rate callbacks clk: actions: Add SD/MMC clocks ARM: dts: sync Actions Semi S700 DT from Linux 5.10-rc7 ARM: dts: s700: add MMC/SD controller node mmc: actions: add MMC driver for Actions OWL S700/S900 configs: Enable mmc support arch/arm/dts/s700-u-boot.dtsi | 10 + arch/arm/dts/s700.dtsi | 17 +- configs/cubieboard7_defconfig | 3 + drivers/clk/owl/clk_owl.c | 99 +++++ drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/owl_mmc.c | 408 ++++++++++++++++++ .../dt-bindings/power/owl-s700-powergate.h | 19 + 8 files changed, 563 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/owl_mmc.c create mode 100644 include/dt-bindings/power/owl-s700-powergate.h -- 2.27.0

3 17

[PATCH] mtd: nand: pxa3xx: set mtd->dev
by Robert Marko 18 Jan '22

18 Jan '22

Currently the pxa3xx driver does not set the udevice in the mtd_info struct and this prevents the mtd from parsing the partitions via DTS like for SPI-NOR. So simply set the mtd->dev to the driver udevice. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/mtd/nand/raw/pxa3xx_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 8ff58a7038..eb739bb3b9 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -1913,6 +1913,7 @@ static int pxa3xx_nand_probe(struct udevice *dev) * user's mtd partitions configuration would get broken. */ mtd->name = "pxa3xx_nand-0"; + mtd->dev = dev; info->cs = cs; ret = pxa3xx_nand_scan(mtd); if (ret) { -- 2.34.1

3 2

[PATCH v2 1/7] common: spl: move armv7m-specific code to spl_perform_fixups()
by Ovidiu Panait 18 Jan '22

18 Jan '22

Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board specific function designed for this purpose. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait(a)windriver.com> --- (no changes since v1) arch/arm/cpu/armv7m/cpu.c | 6 ++++++ common/spl/spl.c | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 63721018c1..65427b5312 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -12,6 +12,7 @@ #include <irq_func.h> #include <asm/io.h> #include <asm/armv7m.h> +#include <spl.h> /* * This is called right before passing control to @@ -56,3 +57,8 @@ void reset_cpu(void) | (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK) | V7M_AIRCR_SYSRESET, &V7M_SCB->aircr); } + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + spl_image->entry_point |= 0x1; +} diff --git a/common/spl/spl.c b/common/spl/spl.c index 4c101ec5d3..dab0f5fe38 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -770,9 +770,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2) ret); } -#ifdef CONFIG_CPU_V7M - spl_image.entry_point |= 0x1; -#endif switch (spl_image.os) { case IH_OS_U_BOOT: debug("Jumping to %s...\n", spl_phase_name(spl_next_phase())); -- 2.25.1

4 15

[PATCH 1/2] lib: add BLAKE2 hash support
by Qu Wenruo 18 Jan '22

18 Jan '22

The code is cross-ported from BLAKE2 reference implementation (https://github.com/BLAKE2/BLAKE2). With minimal change to remove unused macros/features. Currently there is only one user inside U-boot (btrfs), and since it only utilize BLAKE2B, all other favors are all removed. Signed-off-by: Qu Wenruo <wqu(a)suse.com> --- include/u-boot/blake2.h | 94 ++++++++++++ lib/Kconfig | 8 + lib/Makefile | 1 + lib/blake2/blake2-impl.h | 163 ++++++++++++++++++++ lib/blake2/blake2b.c | 311 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 577 insertions(+) create mode 100644 include/u-boot/blake2.h create mode 100644 lib/blake2/blake2-impl.h create mode 100644 lib/blake2/blake2b.c diff --git a/include/u-boot/blake2.h b/include/u-boot/blake2.h new file mode 100644 index 000000000000..4984023a1a2d --- /dev/null +++ b/include/u-boot/blake2.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: CC0-1.0 */ +/* + BLAKE2 reference source code package - reference C implementations + + Copyright 2012, Samuel Neves <sneves(a)dei.uc.pt>. You may use this under the + terms of the CC0, the OpenSSL Licence, or the Apache Public License 2.0, at + your option. The terms of these licenses can be found at: + + - CC0 1.0 Universal : http://creativecommons.org/publicdomain/zero/1.0 + - OpenSSL license : https://www.openssl.org/source/license.html + - Apache 2.0 : http://www.apache.org/licenses/LICENSE-2.0 + + More information about the BLAKE2 hash function can be found at + https://blake2.net. +*/ + +/* + * Cross-ported from BLAKE2 (https://github.com/BLAKE2/BLAKE2). + * Modifications includes: + * + * - Remove unsupported compilers like MSC/CPP + * - Remove blake2s/blake2sp/blake2bp + * This blake2 implementation is mostly for btrfs, which only utilizes + * blake2b. + */ +#ifndef BLAKE2_H +#define BLAKE2_H + +#include <stddef.h> +#include <stdint.h> + +#if defined(_MSC_VER) +#define BLAKE2_PACKED(x) __pragma(pack(push, 1)) x __pragma(pack(pop)) +#else +#define BLAKE2_PACKED(x) x __attribute__((packed)) +#endif + + enum blake2b_constant + { + BLAKE2B_BLOCKBYTES = 128, + BLAKE2B_OUTBYTES = 64, + BLAKE2B_KEYBYTES = 64, + BLAKE2B_SALTBYTES = 16, + BLAKE2B_PERSONALBYTES = 16 + }; + + typedef struct blake2b_state__ + { + uint64_t h[8]; + uint64_t t[2]; + uint64_t f[2]; + uint8_t buf[BLAKE2B_BLOCKBYTES]; + size_t buflen; + size_t outlen; + uint8_t last_node; + } blake2b_state; + + BLAKE2_PACKED(struct blake2b_param__ + { + uint8_t digest_length; /* 1 */ + uint8_t key_length; /* 2 */ + uint8_t fanout; /* 3 */ + uint8_t depth; /* 4 */ + uint32_t leaf_length; /* 8 */ + uint32_t node_offset; /* 12 */ + uint32_t xof_length; /* 16 */ + uint8_t node_depth; /* 17 */ + uint8_t inner_length; /* 18 */ + uint8_t reserved[14]; /* 32 */ + uint8_t salt[BLAKE2B_SALTBYTES]; /* 48 */ + uint8_t personal[BLAKE2B_PERSONALBYTES]; /* 64 */ + }); + + typedef struct blake2b_param__ blake2b_param; + + /* Padded structs result in a compile-time error */ + enum { + BLAKE2_DUMMY_2 = 1/(int)(sizeof(blake2b_param) == BLAKE2B_OUTBYTES) + }; + + /* Streaming API */ + int blake2b_init( blake2b_state *S, size_t outlen ); + int blake2b_init_key( blake2b_state *S, size_t outlen, const void *key, size_t keylen ); + int blake2b_init_param( blake2b_state *S, const blake2b_param *P ); + int blake2b_update( blake2b_state *S, const void *in, size_t inlen ); + int blake2b_final( blake2b_state *S, void *out, size_t outlen ); + + /* Simple API */ + int blake2b( void *out, size_t outlen, const void *in, size_t inlen, const void *key, size_t keylen ); + + /* This is simply an alias for blake2b */ + int blake2( void *out, size_t outlen, const void *in, size_t inlen, const void *key, size_t keylen ); + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index 807a4c6ade06..e9976c7425e2 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -357,6 +357,14 @@ endmenu menu "Hashing Support" +config BLAKE2 + bool "Enable BLAKE2 support" + help + This option enables support of hashing using BLAKE2B algorithm. + The hash is calculated in software. + The BLAKE2 algorithm produces a hash value (digest) between 1 and + 64 bytes. + config SHA1 bool "Enable SHA1 support" help diff --git a/lib/Makefile b/lib/Makefile index 5ddbc77ed6d8..7950e847a9e2 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_$(SPL_)MD5) += md5.o obj-$(CONFIG_ECDSA) += ecdsa/ obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_HASH) += hash-checksum.o +obj-$(CONFIG_BLAKE2) += blake2/blake2b.o obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_SHA512) += sha512.o diff --git a/lib/blake2/blake2-impl.h b/lib/blake2/blake2-impl.h new file mode 100644 index 000000000000..7ee52fdf5ada --- /dev/null +++ b/lib/blake2/blake2-impl.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: CC0-1.0 */ +/* + BLAKE2 reference source code package - reference C implementations + + Copyright 2012, Samuel Neves <sneves(a)dei.uc.pt>. You may use this under the + terms of the CC0, the OpenSSL Licence, or the Apache Public License 2.0, at + your option. The terms of these licenses can be found at: + + - CC0 1.0 Universal : http://creativecommons.org/publicdomain/zero/1.0 + - OpenSSL license : https://www.openssl.org/source/license.html + - Apache 2.0 : http://www.apache.org/licenses/LICENSE-2.0 + + More information about the BLAKE2 hash function can be found at + https://blake2.net. +*/ + +/* + * Cross-ported from BLAKE2 (https://github.com/BLAKE2/BLAKE2). + * Modifications includes: + * + * - Remove unsupported compilers like MSC/CPP + * - Use u-boot library functions/macros + */ +#ifndef BLAKE2_IMPL_H +#define BLAKE2_IMPL_H + +#include <stdint.h> +#include <string.h> + +#define BLAKE2_INLINE inline + +#ifdef __LITTLE_ENDIAN +# define NATIVE_LITTLE_ENDIAN +#endif + +static BLAKE2_INLINE uint32_t load32( const void *src ) +{ +#if defined(NATIVE_LITTLE_ENDIAN) + uint32_t w; + memcpy(&w, src, sizeof w); + return w; +#else + const uint8_t *p = ( const uint8_t * )src; + return (( uint32_t )( p[0] ) << 0) | + (( uint32_t )( p[1] ) << 8) | + (( uint32_t )( p[2] ) << 16) | + (( uint32_t )( p[3] ) << 24) ; +#endif +} + +static BLAKE2_INLINE uint64_t load64( const void *src ) +{ +#if defined(NATIVE_LITTLE_ENDIAN) + uint64_t w; + memcpy(&w, src, sizeof w); + return w; +#else + const uint8_t *p = ( const uint8_t * )src; + return (( uint64_t )( p[0] ) << 0) | + (( uint64_t )( p[1] ) << 8) | + (( uint64_t )( p[2] ) << 16) | + (( uint64_t )( p[3] ) << 24) | + (( uint64_t )( p[4] ) << 32) | + (( uint64_t )( p[5] ) << 40) | + (( uint64_t )( p[6] ) << 48) | + (( uint64_t )( p[7] ) << 56) ; +#endif +} + +static BLAKE2_INLINE uint16_t load16( const void *src ) +{ +#if defined(NATIVE_LITTLE_ENDIAN) + uint16_t w; + memcpy(&w, src, sizeof w); + return w; +#else + const uint8_t *p = ( const uint8_t * )src; + return ( uint16_t )((( uint32_t )( p[0] ) << 0) | + (( uint32_t )( p[1] ) << 8)); +#endif +} + +static BLAKE2_INLINE void store16( void *dst, uint16_t w ) +{ +#if defined(NATIVE_LITTLE_ENDIAN) + memcpy(dst, &w, sizeof w); +#else + uint8_t *p = ( uint8_t * )dst; + *p++ = ( uint8_t )w; w >>= 8; + *p++ = ( uint8_t )w; +#endif +} + +static BLAKE2_INLINE void store32( void *dst, uint32_t w ) +{ +#if defined(NATIVE_LITTLE_ENDIAN) + memcpy(dst, &w, sizeof w); +#else + uint8_t *p = ( uint8_t * )dst; + p[0] = (uint8_t)(w >> 0); + p[1] = (uint8_t)(w >> 8); + p[2] = (uint8_t)(w >> 16); + p[3] = (uint8_t)(w >> 24); +#endif +} + +static BLAKE2_INLINE void store64( void *dst, uint64_t w ) +{ +#if defined(NATIVE_LITTLE_ENDIAN) + memcpy(dst, &w, sizeof w); +#else + uint8_t *p = ( uint8_t * )dst; + p[0] = (uint8_t)(w >> 0); + p[1] = (uint8_t)(w >> 8); + p[2] = (uint8_t)(w >> 16); + p[3] = (uint8_t)(w >> 24); + p[4] = (uint8_t)(w >> 32); + p[5] = (uint8_t)(w >> 40); + p[6] = (uint8_t)(w >> 48); + p[7] = (uint8_t)(w >> 56); +#endif +} + +static BLAKE2_INLINE uint64_t load48( const void *src ) +{ + const uint8_t *p = ( const uint8_t * )src; + return (( uint64_t )( p[0] ) << 0) | + (( uint64_t )( p[1] ) << 8) | + (( uint64_t )( p[2] ) << 16) | + (( uint64_t )( p[3] ) << 24) | + (( uint64_t )( p[4] ) << 32) | + (( uint64_t )( p[5] ) << 40) ; +} + +static BLAKE2_INLINE void store48( void *dst, uint64_t w ) +{ + uint8_t *p = ( uint8_t * )dst; + p[0] = (uint8_t)(w >> 0); + p[1] = (uint8_t)(w >> 8); + p[2] = (uint8_t)(w >> 16); + p[3] = (uint8_t)(w >> 24); + p[4] = (uint8_t)(w >> 32); + p[5] = (uint8_t)(w >> 40); +} + +static BLAKE2_INLINE uint32_t rotr32( const uint32_t w, const unsigned c ) +{ + return ( w >> c ) | ( w << ( 32 - c ) ); +} + +static BLAKE2_INLINE uint64_t rotr64( const uint64_t w, const unsigned c ) +{ + return ( w >> c ) | ( w << ( 64 - c ) ); +} + +/* prevents compiler optimizing out memset() */ +static BLAKE2_INLINE void secure_zero_memory(void *v, size_t n) +{ + static void *(*const volatile memset_v)(void *, int, size_t) = &memset; + memset_v(v, 0, n); +} + +#endif diff --git a/lib/blake2/blake2b.c b/lib/blake2/blake2b.c new file mode 100644 index 000000000000..bb1c333da226 --- /dev/null +++ b/lib/blake2/blake2b.c @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: CC0-1.0 */ +/* + BLAKE2 reference source code package - reference C implementations + + Copyright 2012, Samuel Neves <sneves(a)dei.uc.pt>. You may use this under the + terms of the CC0, the OpenSSL Licence, or the Apache Public License 2.0, at + your option. The terms of these licenses can be found at: + + - CC0 1.0 Universal : http://creativecommons.org/publicdomain/zero/1.0 + - OpenSSL license : https://www.openssl.org/source/license.html + - Apache 2.0 : http://www.apache.org/licenses/LICENSE-2.0 + + More information about the BLAKE2 hash function can be found at + https://blake2.net. +*/ + +/* + * Cross-ported from BLAKE2 (https://github.com/BLAKE2/BLAKE2). + * Modifications includes: + * + * - Remove unused features like selftest + * - Use u-boot library functions/macros + */ +#include <stdint.h> +#include <string.h> +#include <stdio.h> +#include <u-boot/blake2.h> +#include "blake2-impl.h" + +static const uint64_t blake2b_IV[8] = +{ + 0x6a09e667f3bcc908ULL, 0xbb67ae8584caa73bULL, + 0x3c6ef372fe94f82bULL, 0xa54ff53a5f1d36f1ULL, + 0x510e527fade682d1ULL, 0x9b05688c2b3e6c1fULL, + 0x1f83d9abfb41bd6bULL, 0x5be0cd19137e2179ULL +}; + +static const uint8_t blake2b_sigma[12][16] = +{ + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } , + { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 } , + { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 } , + { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 } , + { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 } , + { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 } , + { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 } , + { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 } , + { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 } , + { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13 , 0 } , + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } , + { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 } +}; + + +static void blake2b_set_lastnode( blake2b_state *S ) +{ + S->f[1] = (uint64_t)-1; +} + +/* Some helper functions, not necessarily useful */ +static int blake2b_is_lastblock( const blake2b_state *S ) +{ + return S->f[0] != 0; +} + +static void blake2b_set_lastblock( blake2b_state *S ) +{ + if( S->last_node ) blake2b_set_lastnode( S ); + + S->f[0] = (uint64_t)-1; +} + +static void blake2b_increment_counter( blake2b_state *S, const uint64_t inc ) +{ + S->t[0] += inc; + S->t[1] += ( S->t[0] < inc ); +} + +static void blake2b_init0( blake2b_state *S ) +{ + size_t i; + memset( S, 0, sizeof( blake2b_state ) ); + + for( i = 0; i < 8; ++i ) S->h[i] = blake2b_IV[i]; +} + +/* init xors IV with input parameter block */ +int blake2b_init_param( blake2b_state *S, const blake2b_param *P ) +{ + const uint8_t *p = ( const uint8_t * )( P ); + size_t i; + + blake2b_init0( S ); + + /* IV XOR ParamBlock */ + for( i = 0; i < 8; ++i ) + S->h[i] ^= load64( p + sizeof( S->h[i] ) * i ); + + S->outlen = P->digest_length; + return 0; +} + + + +int blake2b_init( blake2b_state *S, size_t outlen ) +{ + blake2b_param P[1]; + + if ( ( !outlen ) || ( outlen > BLAKE2B_OUTBYTES ) ) return -1; + + P->digest_length = (uint8_t)outlen; + P->key_length = 0; + P->fanout = 1; + P->depth = 1; + store32( &P->leaf_length, 0 ); + store32( &P->node_offset, 0 ); + store32( &P->xof_length, 0 ); + P->node_depth = 0; + P->inner_length = 0; + memset( P->reserved, 0, sizeof( P->reserved ) ); + memset( P->salt, 0, sizeof( P->salt ) ); + memset( P->personal, 0, sizeof( P->personal ) ); + return blake2b_init_param( S, P ); +} + + +int blake2b_init_key( blake2b_state *S, size_t outlen, const void *key, size_t keylen ) +{ + blake2b_param P[1]; + + if ( ( !outlen ) || ( outlen > BLAKE2B_OUTBYTES ) ) return -1; + + if ( !key || !keylen || keylen > BLAKE2B_KEYBYTES ) return -1; + + P->digest_length = (uint8_t)outlen; + P->key_length = (uint8_t)keylen; + P->fanout = 1; + P->depth = 1; + store32( &P->leaf_length, 0 ); + store32( &P->node_offset, 0 ); + store32( &P->xof_length, 0 ); + P->node_depth = 0; + P->inner_length = 0; + memset( P->reserved, 0, sizeof( P->reserved ) ); + memset( P->salt, 0, sizeof( P->salt ) ); + memset( P->personal, 0, sizeof( P->personal ) ); + + if( blake2b_init_param( S, P ) < 0 ) return -1; + + { + uint8_t block[BLAKE2B_BLOCKBYTES]; + memset( block, 0, BLAKE2B_BLOCKBYTES ); + memcpy( block, key, keylen ); + blake2b_update( S, block, BLAKE2B_BLOCKBYTES ); + secure_zero_memory( block, BLAKE2B_BLOCKBYTES ); /* Burn the key from stack */ + } + return 0; +} + +#define G(r,i,a,b,c,d) \ + do { \ + a = a + b + m[blake2b_sigma[r][2*i+0]]; \ + d = rotr64(d ^ a, 32); \ + c = c + d; \ + b = rotr64(b ^ c, 24); \ + a = a + b + m[blake2b_sigma[r][2*i+1]]; \ + d = rotr64(d ^ a, 16); \ + c = c + d; \ + b = rotr64(b ^ c, 63); \ + } while(0) + +#define ROUND(r) \ + do { \ + G(r,0,v[ 0],v[ 4],v[ 8],v[12]); \ + G(r,1,v[ 1],v[ 5],v[ 9],v[13]); \ + G(r,2,v[ 2],v[ 6],v[10],v[14]); \ + G(r,3,v[ 3],v[ 7],v[11],v[15]); \ + G(r,4,v[ 0],v[ 5],v[10],v[15]); \ + G(r,5,v[ 1],v[ 6],v[11],v[12]); \ + G(r,6,v[ 2],v[ 7],v[ 8],v[13]); \ + G(r,7,v[ 3],v[ 4],v[ 9],v[14]); \ + } while(0) + +static void blake2b_compress( blake2b_state *S, const uint8_t block[BLAKE2B_BLOCKBYTES] ) +{ + uint64_t m[16]; + uint64_t v[16]; + size_t i; + + for( i = 0; i < 16; ++i ) { + m[i] = load64( block + i * sizeof( m[i] ) ); + } + + for( i = 0; i < 8; ++i ) { + v[i] = S->h[i]; + } + + v[ 8] = blake2b_IV[0]; + v[ 9] = blake2b_IV[1]; + v[10] = blake2b_IV[2]; + v[11] = blake2b_IV[3]; + v[12] = blake2b_IV[4] ^ S->t[0]; + v[13] = blake2b_IV[5] ^ S->t[1]; + v[14] = blake2b_IV[6] ^ S->f[0]; + v[15] = blake2b_IV[7] ^ S->f[1]; + + ROUND( 0 ); + ROUND( 1 ); + ROUND( 2 ); + ROUND( 3 ); + ROUND( 4 ); + ROUND( 5 ); + ROUND( 6 ); + ROUND( 7 ); + ROUND( 8 ); + ROUND( 9 ); + ROUND( 10 ); + ROUND( 11 ); + + for( i = 0; i < 8; ++i ) { + S->h[i] = S->h[i] ^ v[i] ^ v[i + 8]; + } +} + +#undef G +#undef ROUND + +int blake2b_update( blake2b_state *S, const void *pin, size_t inlen ) +{ + const unsigned char * in = (const unsigned char *)pin; + if( inlen > 0 ) + { + size_t left = S->buflen; + size_t fill = BLAKE2B_BLOCKBYTES - left; + if( inlen > fill ) + { + S->buflen = 0; + memcpy( S->buf + left, in, fill ); /* Fill buffer */ + blake2b_increment_counter( S, BLAKE2B_BLOCKBYTES ); + blake2b_compress( S, S->buf ); /* Compress */ + in += fill; inlen -= fill; + while(inlen > BLAKE2B_BLOCKBYTES) { + blake2b_increment_counter(S, BLAKE2B_BLOCKBYTES); + blake2b_compress( S, in ); + in += BLAKE2B_BLOCKBYTES; + inlen -= BLAKE2B_BLOCKBYTES; + } + } + memcpy( S->buf + S->buflen, in, inlen ); + S->buflen += inlen; + } + return 0; +} + +int blake2b_final( blake2b_state *S, void *out, size_t outlen ) +{ + uint8_t buffer[BLAKE2B_OUTBYTES] = {0}; + size_t i; + + if( out == NULL || outlen < S->outlen ) + return -1; + + if( blake2b_is_lastblock( S ) ) + return -1; + + blake2b_increment_counter( S, S->buflen ); + blake2b_set_lastblock( S ); + memset( S->buf + S->buflen, 0, BLAKE2B_BLOCKBYTES - S->buflen ); /* Padding */ + blake2b_compress( S, S->buf ); + + for( i = 0; i < 8; ++i ) /* Output full hash to temp buffer */ + store64( buffer + sizeof( S->h[i] ) * i, S->h[i] ); + + memcpy( out, buffer, S->outlen ); + secure_zero_memory(buffer, sizeof(buffer)); + return 0; +} + +/* inlen, at least, should be uint64_t. Others can be size_t. */ +int blake2b( void *out, size_t outlen, const void *in, size_t inlen, const void *key, size_t keylen ) +{ + blake2b_state S[1]; + + /* Verify parameters */ + if ( NULL == in && inlen > 0 ) return -1; + + if ( NULL == out ) return -1; + + if( NULL == key && keylen > 0 ) return -1; + + if( !outlen || outlen > BLAKE2B_OUTBYTES ) return -1; + + if( keylen > BLAKE2B_KEYBYTES ) return -1; + + if( keylen > 0 ) + { + if( blake2b_init_key( S, outlen, key, keylen ) < 0 ) return -1; + } + else + { + if( blake2b_init( S, outlen ) < 0 ) return -1; + } + + blake2b_update( S, ( const uint8_t * )in, inlen ); + blake2b_final( S, out, outlen ); + return 0; +} + +int blake2( void *out, size_t outlen, const void *in, size_t inlen, const void *key, size_t keylen ) { + return blake2b(out, outlen, in, inlen, key, keylen); +} -- 2.34.1

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[PATCH] fs/btrfs: fix a bug that U-boot fs btrfs implementation doesn't handle NO_HOLE feature correctly
by Qu Wenruo 18 Jan '22

18 Jan '22

[BUG] When passing a btrfs with NO_HOLE feature to U-boot, and if one file contains holes, then the hash of the file is not correct in U-boot: # mkfs.btrfs -f test.img # Since v5.15, mkfs defaults to NO_HOLES # mount test.img /mnt/btrfs # xfs_io -f -c "pwrite 0 4k" -c "pwrite 8k 4k" /mnt/btrfs/file # md5sum /mnt/btrfs/file 277f3840b275c74d01e979ea9d75ac19 /mnt/btrfs/file # umount /mnt/btrfs # ./u-boot => host bind 0 /home/adam/test.img => ls host 0 < > 12288 Mon Dec 27 05:35:23 2021 file => load host 0 0x1000000 file 12288 bytes read in 0 ms => md5sum 0x1000000 0x3000 md5 for 01000000 ... 01002fff ==> 855ffdbe4d0ccc5acab92e1b5330e4c1 The md5sum doesn't match at all. [CAUSE] In U-boot btrfs implementation, the function btrfs_read_file() has the following iteration for file extent iteration: /* Read the aligned part */ while (cur < aligned_end) { ret = lookup_data_extent(root, &path, ino, cur, &next_offset); if (ret < 0) goto out; if (ret > 0) { /* No next, direct exit */ if (!next_offset) { ret = 0; goto out; } } /* Read file extent */ But for NO_HOLES features, hole extents will not have any extent item for it. Thus if @cur is at a hole, lookup_data_extent() will just return >0, and update @next_offset. But we still believe there is some data to read for @cur for ret > 0 case, causing we read extent data from the next file extent. This means, what we do for above NO_HOLES btrfs is: - Read 4K data from disk to file offset [0, 4K) So far the data is still correct - Read 4K data from disk to file offset [4K, 8K) We didn't skip the 4K hole, but read the data at file offset [8K, 12K) into file offset [4K, 8K). This causes the checksum mismatch. [FIX] Add extra check to skip to the next non-hole range after lookup_data_extent(). Signed-off-by: Qu Wenruo <wqu(a)suse.com> --- This bug exposed another missing link, that we don't have good test coverage in U-boot btrfs. This is partially caused by the fact that, btrfs-progs code is not designed to read file contents, but just to check the cross-reference (aka, btrfs-check). If we really only want read-only support in U-boot, and don't ever plan to add write support, then I'd say the btrfs-fuse project (https://github.com/adam900710/btrfs-fuse/) is more suitable for U-boot. As that project already has full fs content verification selftest along with extra multi-device recovery tests. And shares the same code style between btrfs-progs/kernel. --- fs/btrfs/inode.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 2c2379303d74..d00b5153336d 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -717,6 +717,14 @@ int btrfs_file_read(struct btrfs_root *root, u64 ino, u64 file_offset, u64 len, ret = 0; goto out; } + /* + * Find a extent gap, mostly caused by NO_HOLE feature. + * Just to next offset directly. + */ + if (next_offset > cur) { + cur = next_offset; + continue; + } } fi = btrfs_item_ptr(path.nodes[0], path.slots[0], struct btrfs_file_extent_item); -- 2.34.1

2 2

[PATCH] pinctrl: single: add support for pinctrl-single, pins when #pinctrl-cells = 2
by AJ Bagwell 18 Jan '22

18 Jan '22

Changes to the am33xx device (33e9021a) trees have been merged in from the upstream linux kernel which now means the device tree uses the new pins format (as of 5.10) where the confinguration can be stores as a separate configuration value and pin mux mode which are then OR'd together. This patch adds support for the new format to u-boot so that pinctrl-cells is now respected when reading in pinctrl-single,pins --- drivers/pinctrl/pinctrl-single.c | 55 +++++++++++++++++--------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 8fc07e3498..bc9c17bce8 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -28,6 +28,7 @@ struct single_pdata { int offset; u32 mask; u32 width; + u32 args_count; bool bits_per_mux; }; @@ -78,20 +79,6 @@ struct single_priv { struct list_head gpiofuncs; }; -/** - * struct single_fdt_pin_cfg - pin configuration - * - * This structure is used for the pin configuration parameters in case - * the register controls only one pin. - * - * @reg: configuration register offset - * @val: configuration register value - */ -struct single_fdt_pin_cfg { - fdt32_t reg; - fdt32_t val; -}; - /** * struct single_fdt_bits_cfg - pin configuration * @@ -314,25 +301,28 @@ static int single_pin_compare(const void *s1, const void *s2) * @dev: Pointer to single pin configuration device which is the parent of * the pins node holding the pin configuration data. * @pins: Pointer to the first element of an array of register/value pairs - * of type 'struct single_fdt_pin_cfg'. Each such pair describes the - * the pin to be configured and the value to be used for configuration. + * of type 'u32'. Each such pair describes the pin to be configured + * and the value to be used for configuration. + * The value can either be a simple value if #pinctrl-cells = 1 + * or a configuration value and a pin mux mode value if it is 2 * This pointer points to a 'pinctrl-single,pins' property in the * device-tree. * @size: Size of the 'pins' array in bytes. - * The number of register/value pairs in the 'pins' array therefore - * equals to 'size / sizeof(struct single_fdt_pin_cfg)'. + * The number of cells in the array therefore equals to + * 'size / sizeof(u32)'. * @fname: Function name. */ static int single_configure_pins(struct udevice *dev, - const struct single_fdt_pin_cfg *pins, + const u32 *pins, int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); struct single_priv *priv = dev_get_priv(dev); - int n, pin, count = size / sizeof(struct single_fdt_pin_cfg); + int stride = pdata->args_count + 1; + int n, pin, count = size / sizeof(u32); struct single_func *func; phys_addr_t reg; - u32 offset, val; + u32 offset, val, mux; /* If function mask is null, needn't enable it. */ if (!pdata->mask) @@ -344,16 +334,22 @@ static int single_configure_pins(struct udevice *dev, func->name = fname; func->npins = 0; - for (n = 0; n < count; n++, pins++) { - offset = fdt32_to_cpu(pins->reg); + for (n = 0; n < count; n += stride) { + offset = fdt32_to_cpu(pins[n]); if (offset > pdata->offset) { dev_err(dev, " invalid register offset 0x%x\n", offset); continue; } + /* if the pinctrl-cells is 2 then the second cell contains the mux */ + if (stride == 3) + mux = fdt32_to_cpu(pins[n + 2]); + else + mux = 0; + reg = pdata->base + offset; - val = fdt32_to_cpu(pins->val) & pdata->mask; + val = (fdt32_to_cpu(pins[n + 1]) | mux) & pdata->mask; pin = single_get_pin_by_offset(dev, offset); if (pin < 0) { dev_err(dev, " failed to get pin by offset %x\n", @@ -453,7 +449,7 @@ static int single_configure_bits(struct udevice *dev, static int single_set_state(struct udevice *dev, struct udevice *config) { - const struct single_fdt_pin_cfg *prop; + const u32 *prop; const struct single_fdt_bits_cfg *prop_bits; int len; @@ -461,7 +457,7 @@ static int single_set_state(struct udevice *dev, if (prop) { dev_dbg(dev, "configuring pins for %s\n", config->name); - if (len % sizeof(struct single_fdt_pin_cfg)) { + if (len % sizeof(u32)) { dev_dbg(dev, " invalid pin configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } @@ -612,6 +608,13 @@ static int single_of_to_plat(struct udevice *dev) pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux"); + /* If no pinctrl-cells is present, default to old style of 2 cells with + * bits per mux and 1 cell otherwise. + */ + ret = dev_read_u32(dev, "#pinctrl-cells", &pdata->args_count); + if (ret) + pdata->args_count = pdata->bits_per_mux ? 2 : 1; + return 0; } -- 2.30.1 (Apple Git-130)

3 3

[PATCH] drivers: musb_gadget: Save endpoint desc to usb_ep->desc
by qianfanguijin＠qq.com 18 Jan '22

18 Jan '22

From: qianfan Zhao <qianfanguijin(a)163.com> Fix fastboot flash bug. If the downloading file size is equal to the partition size, "fastboot flash" can't work, at least in sunxi platform, because used an uninitalized point: ep->desc. This patch also fixed 'data abort' bug in am335x platform. Reproduce: fastboot flash loader1 spl/sunxi-spl.bin. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- drivers/usb/musb-new/musb_gadget.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index 1fef00b292..7cca92b970 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -1188,6 +1188,7 @@ static int musb_gadget_enable(struct usb_ep *ep, } else musb_ep->dma = NULL; + musb_ep->end_point.desc = desc; musb_ep->desc = desc; musb_ep->busy = 0; musb_ep->wedged = 0; @@ -1245,9 +1246,7 @@ static int musb_gadget_disable(struct usb_ep *ep) } musb_ep->desc = NULL; -#ifndef __UBOOT__ musb_ep->end_point.desc = NULL; -#endif /* abort all pending DMA and requests */ nuke(musb_ep, -ESHUTDOWN); -- 2.17.1

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