January 2022 - U-Boot

[PATCH] socfpga: enable EFI partition support for de0-nano-soc
by Frank Kunz 19 Jan '22

19 Jan '22

This fixes boot problems with distributions that use EFI boot like opensuse. Signed-off-by: Frank Kunz <mailinglists(a)kunz-im-inter.net> --- configs/socfpga_de0_nano_soc_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 17c160dd2a..3068f5615a 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -35,7 +35,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y -- 2.33.1

2 2

[PATCH] zynqmp: Use the same style for macro definitions
by Michal Simek 19 Jan '22

19 Jan '22

Use the same coding style for all macros. #define<space>NAME<tab/tabs>VALUE Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/zynqmp_firmware.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 51ecbef63464..19c004e91993 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -342,20 +342,20 @@ enum pm_ioctl_id { IOCTL_AIE_ISR_CLEAR = 24, }; -#define PM_SIP_SVC 0xc2000000 +#define PM_SIP_SVC 0xc2000000 -#define ZYNQMP_PM_VERSION_MAJOR 1 -#define ZYNQMP_PM_VERSION_MINOR 0 -#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 -#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF #define ZYNQMP_PM_VERSION \ ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ ZYNQMP_PM_VERSION_MINOR) -#define ZYNQMP_PM_VERSION_INVALID ~0 +#define ZYNQMP_PM_VERSION_INVALID ~0 -#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) /* * Return payload size @@ -384,9 +384,9 @@ int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, #define PM_MASTER_USING_SLAVE_MASK 0x2U /* IPI Mask for Master */ -#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001 -#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100 -#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200 +#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001 +#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100 +#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200 enum zynqmp_pm_request_ack { ZYNQMP_PM_REQUEST_ACK_NO = 1, -- 2.34.1

2 1

[PATCH 0/4] zynqmp: Add support for sending pmufw config object overlay
by Michal Simek 19 Jan '22

19 Jan '22

Hi, this small series is extending firmware interface for sending pmufw configuration overlay with asking for access to certain device. This infrastructure can be used via command or via power domain driver. Thanks, Michal Michal Simek (4): xilinx: firmware: Introduce zynqmp_pmufw_node() for loading PMU fragments firmware: zynqmp: Move loading message to debug firmware: zynqmp: Do not report error if node is already configured arm64: zynqmp: Add command for disabling loading other overlays board/xilinx/zynqmp/cmds.c | 16 ++++++++ drivers/firmware/firmware-zynqmp.c | 60 +++++++++++++++++++++++++++++- include/zynqmp_firmware.h | 2 + 3 files changed, 77 insertions(+), 1 deletion(-) -- 2.34.1

2 5

[PATCH v2] arm: dts: Aspeed: add Bletchley dts
by Potin Lai 19 Jan '22

19 Jan '22

Initial introduction of Bletchley equipped with Aspeed 2600 BMC SoC. Signed-off-by: Potin Lai <potin.lai(a)quantatw.com> --- Change since v1: - Disable mdio0, mdio1, mdio2 - Remove mac0, mac1, mac3 (keep disabled) - Enable mac2, and set to fixed-link --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/ast2600-bletchley.dts | 285 +++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-bletchley.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df844065cd..a172a9f8c6 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -685,7 +685,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-rainier.dtb \ ast2600-slt.dtb \ ast2600-tacoma.dtb \ - ast2600-intel.dtb + ast2600-intel.dtb \ + ast2600-bletchley.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb diff --git a/arch/arm/dts/ast2600-bletchley.dts b/arch/arm/dts/ast2600-bletchley.dts new file mode 100644 index 0000000000..ec14898400 --- /dev/null +++ b/arch/arm/dts/ast2600-bletchley.dts @@ -0,0 +1,285 @@ +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "AST2600 EVB"; + compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + mmc0 = &emmc_slot0; + mmc1 = &sdhci_slot0; + mmc2 = &sdhci_slot1; + spi0 = &fmc; + spi1 = &spi1; + spi2 = &spi2; + ethernet0 = &mac0; + ethernet1 = &mac1; + ethernet2 = &mac2; + ethernet3 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&mac2 { + status = "okay"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default &pinctrl_mac3link_default>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&fmc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fmcquad_default>; + + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@2 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&spi1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default + &pinctrl_spi1cs1_default &pinctrl_spi1wp_default + &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; + + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&spi2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default + &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; + + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@2 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&emmc { + u-boot,dm-pre-reloc; + timing-phase = <0x700ff>; +}; + +&emmc_slot0 { + u-boot,dm-pre-reloc; + status = "okay"; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_default>; + sdhci-drive-type = <1>; +}; + +&sdhci { + timing-phase = <0xc6ffff>; +}; + +&sdhci_slot0 { + status = "okay"; + bus-width = <4>; + pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_default>; + sdhci-drive-type = <1>; +}; + +&sdhci_slot1 { + status = "okay"; + bus-width = <4>; + pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + sdhci-drive-type = <1>; +}; + +&i2c4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; +}; + +&i2c5 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; +}; + +&i2c6 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; +}; + +&i2c7 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; +}; + +&i2c8 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; + +&pcie_bridge1 { + status = "okay"; +}; + +&h2x { + status = "okay"; +}; + +#if 0 +&fsim0 { + status = "okay"; +}; + +&fsim1 { + status = "okay"; +}; +#endif + +&ehci1 { + status = "okay"; +}; + +&display_port { + status = "okay"; +}; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac1-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac2-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; + mac3-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; +}; + +&hace { + status = "okay"; +}; -- 2.17.1

4 3

[PATCH] arm64: zynqmp: Change firmware dependency
by Michal Simek 19 Jan '22

19 Jan '22

In case of mini U-Boot configurations there is no need to enable firmware driver which just consume space for nothing. That's why add an option to disable it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23d57ca10c51..635cea6131a8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1193,7 +1193,7 @@ config ARCH_ZYNQMP select DM_SERIAL select DM_SPI if SPI select DM_SPI_FLASH if DM_SPI - select FIRMWARE + imply FIRMWARE select GICV2 select GPIO_EXTRA_HEADER select OF_CONTROL @@ -1203,7 +1203,7 @@ config ARCH_ZYNQMP select SPL_DM_SPI if SPI && SPL_DM select SPL_DM_SPI_FLASH if SPL_DM_SPI select SPL_DM_MAILBOX if SPL - select SPL_FIRMWARE if SPL + imply SPL_FIRMWARE if SPL select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL select ZYNQMP_IPI -- 2.34.1

2 1

[PATCH] arm64: xilinx: dts: Add dma properties to fix dtbs_check warnings
by Michal Simek 19 Jan '22

19 Jan '22

From: Shravya Kumbham <shravya.kumbham(a)xilinx.com> Update dma name and add #dma-cells properties to fix dtbs_check warnings. Signed-off-by: Shravya Kumbham <shravya.kumbham(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp.dtsi | 48 ++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 1331cec36f34..755a4ed2e515 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -265,7 +265,7 @@ }; /* GDMA */ - fpd_dma_chan1: dma@fd500000 { + fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; @@ -276,9 +276,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan2: dma@fd510000 { + fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; @@ -289,9 +290,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan3: dma@fd520000 { + fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; @@ -302,9 +304,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan4: dma@fd530000 { + fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; @@ -315,9 +318,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan5: dma@fd540000 { + fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; @@ -328,9 +332,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan6: dma@fd550000 { + fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; @@ -341,9 +346,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan7: dma@fd560000 { + fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; @@ -354,9 +360,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan8: dma@fd570000 { + fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; @@ -367,6 +374,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; gic: interrupt-controller@f9010000 { @@ -396,7 +404,7 @@ * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ - lpd_dma_chan1: dma@ffa80000 { + lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; @@ -407,9 +415,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan2: dma@ffa90000 { + lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; @@ -420,9 +429,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan3: dma@ffaa0000 { + lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; @@ -433,9 +443,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan4: dma@ffab0000 { + lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; @@ -446,9 +457,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan5: dma@ffac0000 { + lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; @@ -459,9 +471,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan6: dma@ffad0000 { + lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; @@ -472,9 +485,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan7: dma@ffae0000 { + lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; @@ -485,9 +499,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan8: dma@ffaf0000 { + lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; @@ -498,6 +513,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; mc: memory-controller@fd070000 { -- 2.34.1

2 1

[PATCH] arm64: zynqmp: Update USB node handle from dwc3 to usb
by Michal Simek 19 Jan '22

19 Jan '22

From: Manish Narani <manish.narani(a)xilinx.com> The DWC3 bindings require all USB node handles to be '^usb@[0-9a-f]+$'. Update the same in ZynqMP device tree. Signed-off-by: Manish Narani <manish.narani(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 300a2189f6eb..1331cec36f34 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -858,7 +858,7 @@ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; - dwc3_0: dwc3@fe200000 { + dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; @@ -890,7 +890,7 @@ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; - dwc3_1: dwc3@fe300000 { + dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; -- 2.34.1

2 1

[PATCH] arm64: zynqmp: Change compatible strings for cadence uart
by Michal Simek 19 Jan '22

19 Jan '22

Based on Linux kernel DT binding there should be different compatible strings used that's why align zynqmp.dtsi with it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 015a582d7a79..300a2189f6eb 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -824,7 +824,7 @@ uart0: serial@ff000000 { u-boot,dm-pre-reloc; - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -835,7 +835,7 @@ uart1: serial@ff010000 { u-boot,dm-pre-reloc; - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; -- 2.34.1

2 1

[PATCH v2 1/1] doc: printf() codes
by Heinrich Schuchardt 19 Jan '22

19 Jan '22

Document the format specifier codes used by U-Boot's printf() implementation. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- v2: describe flags (' ', '#', '-', '+') mention %o --- doc/develop/index.rst | 1 + doc/develop/printf.rst | 199 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 200 insertions(+) create mode 100644 doc/develop/printf.rst diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 9592d193fc..c84b10ea88 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -21,6 +21,7 @@ Implementation logging makefiles menus + printf uefi/index version diff --git a/doc/develop/printf.rst b/doc/develop/printf.rst new file mode 100644 index 0000000000..9a66bfaf77 --- /dev/null +++ b/doc/develop/printf.rst @@ -0,0 +1,199 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Printf() format codes +===================== + +Each conversion specification consists of: + +* leading '%' character +* zero or more flags +* an optional minimum field width +* an optional precision field preceded by '.' +* an optional length modifier +* a conversion specifier + +Flags +----- + +- + left justify + ++ + add sign field of decimal conversion + +'space' + fill up with spaces to reach the specified length + +# + convert to alternative form + + * prepend 0 to octal output + * ignored for decimal output + * prepend 0X to hexadecimal output + +0 + fill up with zeroes to reach the specified length + + +Integer types +------------- + +Length modifiers +'''''''''''''''' + +The optional length modifier specifies the size of the argument. + +no modifier + bool, enum, short, int are passed as int + +%h + convert to (unsigned) short before printing. + Only the low 16 bits are printed. + +%hh + **not implemented** + +%j + **not implemented** + +%l + long + +%ll, %L + long long + +%t + ptr_diff_t + +%z, %Z + size_t, ssize_t + +Conversion specifiers +''''''''''''''''''''' + +Conversion specifiers control the output. + +%d + signed decimal + +%u + unsigned decimal + +%o + unsigned octal + +%x + unsigned lower case hexadecimal + +%X + unsigned upper case hexadecimal + +The floating point conversion specifiers are not implemented: + +* %a +* %A +* %e +* %E +* %f +* %F +* %g +* %G + +The following tables shows the correct combinations of modifiers and specifiers +for the individual integer types. + +=================== ================== +Type Format specifier +=================== ================== +bool %d, %x +char %d, %x +unsigned char %u, %x +short %d, %x +unsigned short %u, %x +int %d, %x +unsigned int %d, %x +long %ld, %lx +unsigned long %lu, %lx +long long %lld, %llx +unsigned long long %llu, %llx +off_t %llu, %llx +ptr_diff_t %td, %tx +fdt_addr_t %pa, see pointers +fdt_size_t %pa, see pointers +phys_addr_t %pa, see pointers +phys_size_t %pa, see pointers +resource_size_t %pa, see pointers +size_t %zu, %zx, %zX +ssize_t %zd, %zx, %zX +=================== ================== + +Characters +---------- + +%% + a '%' character is written + +%c + prints a single character + +%lc + **not implemented** + +Strings +------- + +%s + prints a UTF-8 string (char \*) + +%ls + prints a UTF-16 string (u16 \*) + +Pointers +-------- + +%p + prints the address the pointer points to hexadecimally + +%pa, %pap + prints the value of a phys_addr_t value that the pointer points to + preceded with 0x and zero padding according to the size of phys_addr_t. + The following types should be printed this way: + + * fdt_addr_t + * fdt_size_t + * phys_addr_t + * phys_size_t + * resource_size_t + +%pD + prints a UEFI device path + +%pi4, %pI4 + prints IPv4 address, e.g. '192.168.0.1' + +%pm + prints MAC address without separators, e.g. '001122334455' + +%pM + print MAC address colon separated, e.g. '00:01:02:03:04:05' + +%pUb + prints GUID big endian, lower case + e.g. '00112233-4455-6677-8899-aabbccddeeff' + +%pUB + prints GUID big endian, upper case + e.g. '00112233-4455-6677-8899-AABBCCDDEEFF' + +%pUl + prints GUID little endian, lower case + e.g. '33221100-5544-7766-8899-aabbccddeeff' + +%pUL + prints GUID little endian, upper case + e.g. '33221100-5544-7766-8899-AABBCCDDEEFF' + +%pUs + prints text description of a GUID or if such is not known little endian, + lower case, e.g. 'system' for a GUID identifying an EFI system + partition. -- 2.33.1

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[PATCH v3 0/1] rsa: adds rsa3072 algorithm
by Jamin Lin 19 Jan '22

19 Jan '22

Add to support rsa 3072 bits algorithm in tools for make-image signing at host side and add rsa 3072 bits verification in the image binary. v3: - Fix typo - Add test case in vboot for rsa3072 testing v2: - update to send a single patch Jamin Lin (1): rsa: adds rsa3072 algorithm include/u-boot/rsa.h | 1 + lib/rsa/rsa-verify.c | 6 +++ test/py/tests/test_vboot.py | 12 +++++- test/py/tests/vboot/sign-configs-sha384.its | 45 +++++++++++++++++++++ test/py/tests/vboot/sign-images-sha384.its | 42 +++++++++++++++++++ tools/image-sig-host.c | 7 ++++ 6 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 test/py/tests/vboot/sign-configs-sha384.its create mode 100644 test/py/tests/vboot/sign-images-sha384.its -- 2.17.1

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