January 2022 - U-Boot

[PATCH 00/20] i.MX8ULP misc update
by Peng Fan (OSS) 05 Feb '22

05 Feb '22

From: Peng Fan <peng.fan(a)nxp.com> This is to upstream NXP downstream i.MX8ULP patches including ADC/DRAM/LPAV/FUSE/ENET update/fix Alice Guo (3): imx8ulp: clock: Support to enable/disable the ADC1 clock imx8ulp: measure die temperature using PMC Temperature Sensor imx8ulp: implement to obtain the SoC current temperature Jacky Bai (1): imx8ulp:ddr: saving the dram config timing data into sram Peng Fan (1): imx8ulp: assign PXP/HIFI4/EPDC to APD domain Ye Li (15): imx8ulp: soc: Check the DBD_EN fuse before setting RDC arm: imx8ulp: Allocate LPAV resources to AP domain imx8ulp: clock: Support LPAV clocks in cgc and pcc imx8ulp: clock: Add MIPI DSI clock and DCNano clock imx8ulp: rdc: allow A35 access flexspi0 mem imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest imx8ulp: Fix DCNANO QoS setting imx8ulp: Remove freescale name from CPU revision imx8ulp: Workaround LPOSC_TRIM fuse load issue imx8ulp: clock: Reset DDR controller before clock enable imx8ulp: clock: Support to reset DCNano and MIPI DSI imx8ulp: Update ethernet mac to get from fuse imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock imx8ulp: ddr: Fix DDR frequency request issue arch/arm/include/asm/arch-imx8ulp/cgc.h | 37 +- arch/arm/include/asm/arch-imx8ulp/clock.h | 4 + arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 63 +++- .../include/asm/arch-imx8ulp/imx8ulp-pins.h | 4 + arch/arm/include/asm/arch-imx8ulp/pcc.h | 70 +++- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 + arch/arm/mach-imx/imx8ulp/cgc.c | 325 +++++++++++++++--- arch/arm/mach-imx/imx8ulp/clock.c | 156 ++++++++- arch/arm/mach-imx/imx8ulp/pcc.c | 158 ++++++++- arch/arm/mach-imx/imx8ulp/soc.c | 117 ++++++- board/freescale/imx8ulp_evk/imx8ulp_evk.c | 56 +++ board/freescale/imx8ulp_evk/spl.c | 9 + drivers/ddr/imx/imx8ulp/Kconfig | 7 + drivers/ddr/imx/imx8ulp/ddr_init.c | 55 ++- drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/imx_pmc_temperature.c | 174 ++++++++++ 17 files changed, 1148 insertions(+), 97 deletions(-) create mode 100644 drivers/thermal/imx_pmc_temperature.c -- 2.30.0

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[PATCH 1/2] ARM: imx: imx8m: Align PLL 1.2 GHz option with Linux
by Marek Vasut 05 Feb '22

05 Feb '22

Linux uses slightly different divider settings for the 1.2 GHz PLL configuration, adjust the coefficients to match Linux. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index f8e4ec0d905..2ca3bf68e74 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -244,9 +244,9 @@ int intpll_configure(enum pll_clocks pll, ulong freq) INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); break; case MHZ(1200): - /* 24 * 0xc8 / 2 / 2 ^ 1 */ - pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) | - INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1); + /* 24 * 0x12c / 3 / 2 ^ 1 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); break; case MHZ(2000): /* 24 * 0xfa / 3 / 2 ^ 0 */ -- 2.34.1

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[PATCH v7 0/2] arm: imx8m: add support for Advantech RSB-3720
by Ying-Chun Liu 05 Feb '22

05 Feb '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console v2: update dts v3: remove unnecessary code. move board code to board/advantech v4: rebase to latest master branch. v5: fix commit description v6: update dts v7: remove redefined configs for latest master branch. Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mp-rsb3720-a1 dts file arm: imx8m: add support for Advantech RSB-3720 arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 161 ++ arch/arm/dts/imx8mp-rsb3720-a1.dts | 805 +++++++ arch/arm/mach-imx/imx8m/Kconfig | 15 + board/advantech/imx8mp_rsb3720a1/Kconfig | 14 + board/advantech/imx8mp_rsb3720a1/MAINTAINERS | 7 + board/advantech/imx8mp_rsb3720a1/Makefile | 24 + .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 213 ++ .../imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg | 11 + .../lpddr4_timing_rsb3720a1_4G.c | 1848 ++++++++++++++++ .../lpddr4_timing_rsb3720a1_6G.c | 1875 +++++++++++++++++ board/advantech/imx8mp_rsb3720a1/spl.c | 260 +++ configs/imx8mp_rsb3720a1_4G_defconfig | 167 ++ configs/imx8mp_rsb3720a1_6G_defconfig | 168 ++ include/configs/imx8mp_rsb3720.h | 223 ++ 15 files changed, 5794 insertions(+) create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1.dts create mode 100644 board/advantech/imx8mp_rsb3720a1/Kconfig create mode 100644 board/advantech/imx8mp_rsb3720a1/MAINTAINERS create mode 100644 board/advantech/imx8mp_rsb3720a1/Makefile create mode 100644 board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c create mode 100644 board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/spl.c create mode 100644 configs/imx8mp_rsb3720a1_4G_defconfig create mode 100644 configs/imx8mp_rsb3720a1_6G_defconfig create mode 100644 include/configs/imx8mp_rsb3720.h -- 2.34.1

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[PATCH] imx8mn-ddr4-evk: generate single bootable image
by Andrey Zhizhikin 05 Feb '22

05 Feb '22

As suggested in commit 028abfd9b157 ("imx8mm-evk: Generate a single bootable flash.bin again") for imx8mm_evk, it is possible to produce single bootable image via binman. This restores the original behavior in distros, where only one boot container is used to create target image. Perform similar adaptions in order to provide single bootable image for imx8mn-ddr4-evk derivate. Update documentation to drop additional step of copying u-boot.itb Fixes: 353dfe4b4359 ("imx8mn-ddr4-evk: switch to use binman") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin(a)leica-geosystems.com> --- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++- .../imx8mn_evk/imximage-8mn-ddr4.cfg | 2 +- doc/board/nxp/imx8mn_evk.rst | 1 - 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 1d3844437d..2e39790766 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -157,7 +157,9 @@ }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; @@ -224,4 +226,19 @@ }; }; }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "spl.bin"; + }; + + uboot: blob-ext@2 { + offset = <0x58000>; + filename = "u-boot.itb"; + }; + }; }; diff --git a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg index 22aec26da7..7286b26494 100644 --- a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg +++ b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg @@ -7,4 +7,4 @@ ROM_VERSION v2 BOOT_FROM sd -LOADER mkimage.flash.mkimage 0x912000 +LOADER u-boot-spl-ddr.bin 0x912000 diff --git a/doc/board/nxp/imx8mn_evk.rst b/doc/board/nxp/imx8mn_evk.rst index 9fbb947032..711545af89 100644 --- a/doc/board/nxp/imx8mn_evk.rst +++ b/doc/board/nxp/imx8mn_evk.rst @@ -50,7 +50,6 @@ Burn the flash.bin to MicroSD card offset 32KB: .. code-block:: bash $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc - $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc Boot ---- base-commit: 4e81f3be340072ad2c0aac093677333702f14f22 -- 2.25.1

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[PATCH 1/3] doc: imx8mm_evk: Remove ATF_LOAD_ADDR export
by Fabio Estevam 05 Feb '22

05 Feb '22

imx8mm-u-boot.dtsi passes the ATF load address via the 'entry' and 'load' properties. Remove the step that performs the ATF_LOAD_ADDR export, which is now unneeded. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- doc/board/nxp/imx8mm_evk.rst | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/board/nxp/imx8mm_evk.rst b/doc/board/nxp/imx8mm_evk.rst index b377c4de276d..b9e67b954fc2 100644 --- a/doc/board/nxp/imx8mm_evk.rst +++ b/doc/board/nxp/imx8mm_evk.rst @@ -42,7 +42,6 @@ Build U-Boot $ export CROSS_COMPILE=aarch64-poky-linux- $ make imx8mm_evk_defconfig - $ export ATF_LOAD_ADDR=0x920000 $ make Burn the flash.bin to MicroSD card offset 33KB: -- 2.25.1

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[PATCH 1/2] clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imxrt10{20|50}
by Heiko Thiery 05 Feb '22

05 Feb '22

The clock composite is required when using the clock framework. So select it automatically. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- drivers/clk/imx/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index a2cd0347c3..cdd348020b 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -76,6 +76,7 @@ config SPL_CLK_IMXRT1020 depends on ARCH_IMXRT && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MXRT1020 @@ -84,6 +85,7 @@ config CLK_IMXRT1020 depends on ARCH_IMXRT select CLK select CLK_CCF + select CLK_COMPOSITE_CCF help This enables support clock driver for i.MXRT1020 platforms. @@ -92,6 +94,7 @@ config SPL_CLK_IMXRT1050 depends on ARCH_IMXRT && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MXRT1050 @@ -100,5 +103,6 @@ config CLK_IMXRT1050 depends on ARCH_IMXRT select CLK select CLK_CCF + select CLK_COMPOSITE_CCF help This enables support clock driver for i.MXRT1050 platforms. -- 2.30.2

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[PATCH] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board
by Marek Vasut 05 Feb '22

05 Feb '22

From: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> The PDK2 board is capable of running both 100M and 1G ethernet. However, the i.MX6 has only one ethernet MAC, so it is possible to configure either 100M or 1G Ethernet. In case of 100M option, the PHY is on the SoM and the signals are routed to a RJ45 port. For 1G the PHY is on the PDK2 board with another RJ45 port. 100M and 1G ethernet use different signal pins from the i.MX6, but share the MDIO bus. This SoM board combination is used to demonstrate how to enable 1G ethernet configuration. Signed-off-by: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Stefano Babic <sbabic(a)denx.de> --- NOTE: Adapted from Linux 298591bf725a ("ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board") --- arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi | 2 +- arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi | 50 +++++++++++++++++++-- include/configs/dh_imx6.h | 4 +- 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi index 32128d4d2ab..a1ffb1d6fc5 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi @@ -15,7 +15,7 @@ }; &fec { - phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; phy-reset-post-delay = <10>; diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi index af4719aaeba..d8772a98966 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi @@ -38,6 +38,45 @@ status = "okay"; }; +/* 1G ethernet */ +/delete-node/ &ethphy0; +&fec { + phy-mode = "rgmii"; + phy-handle = <&ethphy7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1G>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy7: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy7>; + pinctrl-names = "default"; + reg = <7>; + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + &hdmi { ddc-i2c-bus = <&i2c2>; status = "okay"; @@ -113,9 +152,14 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1 + >; + }; + + pinctrl_ethphy7: ethphy7-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ >; }; diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 8183e7debd4..3cf0578b5e1 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -32,9 +32,9 @@ /* FEC ethernet */ #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_MXC_PHYADDR 7 #define CONFIG_ARP_TIMEOUT 200UL /* MMC Configs */ -- 2.33.0

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[PATCH] arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B
by Marek Vasut 05 Feb '22

05 Feb '22

The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020 documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the pinmux tables. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/imx8mm-pinfunc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h index a003e6af335..a7411c800be 100644 --- a/arch/arm/dts/imx8mm-pinfunc.h +++ b/arch/arm/dts/imx8mm-pinfunc.h @@ -248,6 +248,7 @@ #define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 #define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 #define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0 #define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 #define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 #define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -- 2.34.1

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[PATCH v1 0/2] board: toradex: improve env badblock management for NAND variant boards
by Francesco Dolcini 05 Feb '22

05 Feb '22

Use the complete 512kb (4 blocks) nand partition reserved for u-boot environment instead of just the first block, this allows the module to have a working environment even if 3 blocks are bad. Francesco Dolcini (2): colibri-imx6ull: improve env badblock management colibri-imx7: improve env badblock management include/configs/colibri-imx6ull.h | 5 +++++ include/configs/colibri_imx7.h | 5 +++++ 2 files changed, 10 insertions(+) -- 2.25.1

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[PATCH] arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
by Marek Vasut 05 Feb '22

05 Feb '22

From: Oliver Stäbler <oliver.staebler(a)bytesatwork.ch> Fix address of the pad control register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems to be a typo but it leads to an exception when pinctrl is applied due to wrong memory address access. Signed-off-by: Oliver Stäbler <oliver.staebler(a)bytesatwork.ch> Reviewed-by: Fabio Estevam <festevam(a)gmail.com> Acked-by: Rob Herring <robh(a)kernel.org> Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm") Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ") Signed-off-by: Shawn Guo <shawnguo(a)kernel.org> Signed-off-by: Marek Vasut <marex(a)denx.de> # Picked from Linux 5cfad4f45806f ("arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0") --- arch/arm/dts/imx8mm-pinfunc.h | 2 +- arch/arm/dts/imx8mq-pinfunc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h index 5ccc4cc9195..a003e6af335 100644 --- a/arch/arm/dts/imx8mm-pinfunc.h +++ b/arch/arm/dts/imx8mm-pinfunc.h @@ -124,7 +124,7 @@ #define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 #define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h index b94b02080a3..68e8fa17297 100644 --- a/arch/arm/dts/imx8mq-pinfunc.h +++ b/arch/arm/dts/imx8mq-pinfunc.h @@ -130,7 +130,7 @@ #define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 #define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 #define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -- 2.34.1

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