August 2021 - U-Boot

[PATCH v2] Kconfig: Don't use RSA_FREESCALE_EXP on MX7ULP
by Oleksandr Suvorov 07 Oct '21

07 Oct '21

From: Ricardo Salveti <ricardo(a)foundries.io> The CAAM on IMX7ULP doesn't support public key hardware acceleration (PKHA), as in other NXP parts. Disable RSA_FREESCALE_EXP for IMX7ULP too. Fixed: f4e9ff7135 ("Kconfig: Don't use RSA_FREESCALE_EXP on IMX") Signed-off-by: Ricardo Salveti <ricardo(a)foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> --- Changes in v2: - add a dependency rule for RSA_FREESCALE_EXP lib/rsa/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index a90d67e5a8..634c9e5fa9 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -1,6 +1,6 @@ config RSA bool "Use RSA Library" - select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5 + select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5 select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP help RSA support. This enables the RSA algorithm used for FIT image @@ -56,7 +56,7 @@ config RSA_SOFTWARE_EXP config RSA_FREESCALE_EXP bool "Enable RSA Modular Exponentiation with FSL crypto accelerator" - depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5 + depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5 help Enables driver for RSA modular exponentiation using Freescale cryptographic accelerator - CAAM. -- 2.31.1

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[PATCH 0/1] imx8m: Restrict usable memory based on rom_pointer[0]
by Ying-Chun Liu 07 Oct '21

07 Oct '21

From: "Ying-Chun Liu (PaulLiu)" <paulliu(a)debian.org> When TEE is loaded, we need to restrict the memory usage based on rom_pointer[0] This patch fixes a regression on Compulab IoT gate imx8 hang when OPTEE runs. Ying-Chun Liu (PaulLiu) (1): imx8m: Restrict usable memory based on rom_pointer[0] arch/arm/mach-imx/imx8m/soc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.32.0

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[PATCH 1/2] imx53: usbarmory: Add card detect configuration
by andrej.rosano＠f-secure.com 07 Oct '21

07 Oct '21

From: Andrej Rosano <andrej.rosano(a)f-secure.com> After the enforcement of DM_MMC the microSD card is not detected. Fix by correctly configuring the card detect in the devicetree. Signed-off-by: Andrej Rosano <andrej.rosano(a)f-secure.com> --- arch/arm/dts/imx53-usbarmory.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx53-usbarmory.dts b/arch/arm/dts/imx53-usbarmory.dts index f34993a490..433b62e736 100644 --- a/arch/arm/dts/imx53-usbarmory.dts +++ b/arch/arm/dts/imx53-usbarmory.dts @@ -91,6 +91,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; + broken-cd; status = "okay"; }; -- 2.32.0

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[RFC PATCH v1 0/5] arm64: dts: imx8mm: add common -binman.dtsi and further clean-up
by Marcel Ziswiler 07 Oct '21

07 Oct '21

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> With the move to using binman to generate SPL aka u-boot-spl-ddr.bin and U-Boot proper aka u-boot.itb every board now covers such configuration in its own U-Boot specific device tree include. Introduce a new common imx8mm-binman.dtsi which covers the common part of that configuration. The initial patch fixes an issue with intermediate binary naming for the imx8mm-cl-iot-gate. And subsequent patches further clean up that dtsi. This series is based on Peng's binman conversion of late [1], my Verdin iMX8M Mini target refresh [2], Fabio's generating a single bootable flash.bin again for imx8mm-evk [3], Tim's switching imx8mm_venice to using binman to pack images [4] and Frieder's support for Kontron Electronics i.MX6UL/ULL and i.MX8MM SoMs [5]. This series has been run-time tested on Verdin iMX8M Mini. The other targets were only compile tested. Please note that for now, I left out the following intricacies of imx8mm-venice-u-boot.dtsi. Not quite sure what exactly those are used for. fit,fdt-list = "of-list"; ... @fdt-SEQ { ... default = "@config-DEFAULT-SEQ"; ... @config-SEQ { ... fdt = "fdt-SEQ"; [1] https://marc.info/?l=u-boot&m=162908367004699 [2] https://marc.info/?l=u-boot&m=162990457410422 [3] https://marc.info/?l=u-boot&m=162972343709264 [4] https://marc.info/?l=u-boot&m=162983187605276 [5] https://marc.info/?l=u-boot&m=162972880612450 Changes in v1: - This was suggested by Simon on my earlier patch set upon which we decided to first break this up into a common binman dtsi and then subsequently do such further improvements. Marcel Ziswiler (5): imx8mm-cl-iot-gate: fix imximage intermediate binary naming arm64: dts: imx8mm: add common -binman.dtsi arm64: dts: imx8mm-binman.dtsi: alphabetically re-order properties arm64: dts: imx8mm-binman.dtsi: explicitly add spl filename arm64: dts: imx8mm-binman.dtsi: improve odd blob-ext naming arch/arm/dts/imx8mm-binman.dtsi | 146 ++++++++++++++++++ arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 126 ++------------- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 124 +-------------- .../dts/imx8mm-kontron-n801x-s-u-boot.dtsi | 123 +-------------- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 120 +------------- arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 123 +-------------- .../imximage-8mm-lpddr4.cfg | 2 +- 7 files changed, 167 insertions(+), 597 deletions(-) create mode 100644 arch/arm/dts/imx8mm-binman.dtsi -- 2.26.2

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[PATCH] acpi: Use U-Boot version for OEM_REVISION
by Pali Rohár 06 Oct '21

06 Oct '21

OEM_REVISION is 32-bit unsigned number. It should be increased only when changing software version. Therefore it should not depend on build time. Change calculation to use U-Boot version numbers and set this revision to date number. Prior this change OEM_REVISION was calculated from build date and stored in the same format. After this change macro U_BOOT_BUILD_DATE is not used in other files so remove it from global autogenerated files and also from Makefile. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- This patch depends on similar patch for BIOS Release Date which is here: http://patchwork.ozlabs.org/project/uboot/patch/20210422160957.26936-1-pali… --- Makefile | 2 -- doc/develop/version.rst | 1 - lib/acpi/acpi_table.c | 18 +++++++++++++++++- test/dm/acpi.c | 20 ++++++++++++++------ 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 2047081a0739..6dd7d140cfa4 100644 --- a/Makefile +++ b/Makefile @@ -1903,7 +1903,6 @@ define filechk_timestamp.h LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ - LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \ else \ return 42; \ @@ -1912,7 +1911,6 @@ define filechk_timestamp.h LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ - LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \ fi) endef diff --git a/doc/develop/version.rst b/doc/develop/version.rst index 066901bcd2d9..3f2b07cd2261 100644 --- a/doc/develop/version.rst +++ b/doc/develop/version.rst @@ -84,7 +84,6 @@ fields. For example:: #define U_BOOT_DATE "Jan 06 2021" (US format only) #define U_BOOT_TIME "08:50:36" (24-hour clock) #define U_BOOT_TZ "-0700" (Time zone in hours) - #define U_BOOT_BUILD_DATE 0x20210106 (hex yyyymmdd format) #define U_BOOT_EPOCH 1609948236 The Epoch is the number of seconds since midnight on 1/1/70. You can convert diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 2f0774178412..e2f1dc0fc08f 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -16,6 +16,22 @@ #include <asm/global_data.h> #include <dm/acpi.h> +/* + * OEM_REVISION is 32-bit unsigned number. It should be increased only when + * changing software version. Therefore it should not depend on build time. + * U-Boot calculates it from U-Boot version and represent it in hexadecimal + * notation. As U-Boot version is in form year.month set low 8 bits to 0x01 + * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to + * value 0x20210401. + */ +#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ + (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ + (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ + ((U_BOOT_VERSION_NUM % 10) << 16) | \ + (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ + ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ + 0x01) + int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) { struct acpi_table_header *header = &dmar->header; @@ -100,7 +116,7 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature) memcpy(header->signature, signature, 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - header->oem_revision = U_BOOT_BUILD_DATE; + header->oem_revision = OEM_REVISION; memcpy(header->aslc_id, ASLC_ID, 4); } diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2edab7be5445..92901f4c7cc4 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -25,6 +25,14 @@ #define BUF_SIZE 4096 +#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ + (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ + (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ + ((U_BOOT_VERSION_NUM % 10) << 16) | \ + (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ + ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ + 0x01) + /** * struct testacpi_plat - Platform data for the test ACPI device * @@ -218,7 +226,7 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) ut_asserteq_mem(OEM_ID, hdr.oem_id, sizeof(hdr.oem_id)); ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id, sizeof(hdr.oem_table_id)); - ut_asserteq(U_BOOT_BUILD_DATE, hdr.oem_revision); + ut_asserteq(OEM_REVISION, hdr.oem_revision); ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id)); ut_asserteq(0x44, hdr.aslc_revision); @@ -365,20 +373,20 @@ static int dm_test_acpi_cmd_list(struct unit_test_state *uts) addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16); ut_assert_nextline("RSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_table_header) + - 3 * sizeof(u32), U_BOOT_BUILD_DATE); + 3 * sizeof(u32), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16); ut_assert_nextline("XSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_table_header) + - 3 * sizeof(u64), U_BOOT_BUILD_DATE); + 3 * sizeof(u64), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64); ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", - addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr, sizeof(struct acpi_dmar), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", - addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr, sizeof(struct acpi_dmar), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", - addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr, sizeof(struct acpi_dmar), OEM_REVISION); ut_assert_console_end(); return 0; -- 2.20.1

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[PATCH v2] pwm: Add driver for cadence TTC
by Michal Simek 06 Oct '21

06 Oct '21

TTC has three modes of operations. Timer, PWM and input counters. There is already driver for timer under CADENCE_TTC_TIMER which is used for ZynqMP R5 configuration. This driver is targeting PWM which is for example configuration which can be used for fan control. The driver has been tested on Xilinx Kria SOM platform where fan is connected to one PL pin. When TTC output is connected via EMIO to PL pin TTC pwm can be configured and tested for example like this: pwm config 0 0 10000 1200 pwm enable 0 0 pwm config 0 0 10000 1400 pwm config 0 0 10000 1600 Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Detect pwm-cells property for PWM driver - Fix all macro names - Use BIT and GENMASK macros - Introduce TTC_REG macro for reg offsets - Use FIELD_PREP - Move cadence_ttc_pwm_of_to_plat() below probe - Introduce struct cadence_ttc_pwm_plat - Read timer-width from DT - Use NSEC_PER_SEC macro - Use clock_ctrl variable instead of x - all reported by Sean MAINTAINERS | 1 + drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cadence-ttc.c | 247 ++++++++++++++++++++++++++++++++++ 4 files changed, 256 insertions(+) create mode 100644 drivers/pwm/pwm-cadence-ttc.c diff --git a/MAINTAINERS b/MAINTAINERS index 4cf0c33c5d58..889813382249 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,6 +600,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/pwm/pwm-cadence-ttc.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6840ce..176e703c8fbb 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,6 +9,13 @@ config DM_PWM frequency/period can be controlled along with the proportion of that time that the signal is high. +config PWM_CADENCE_TTC + bool "Enable support for the Cadence TTC PWM" + depends on DM_PWM && !CADENCE_TTC_TIMER + help + Cadence TTC can be configured as timer which is done via + CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now. + config PWM_CROS_EC bool "Enable support for the Chrome OS EC PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244bfb79d..abf5af41d2cc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c new file mode 100644 index 000000000000..99aaaa6a8ab6 --- /dev/null +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 Xilinx, Inc. Michal Simek + */ + +#include <clk.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <log.h> +#include <pwm.h> +#include <asm/io.h> +#include <log.h> +#include <div64.h> +#include <linux/bitfield.h> +#include <linux/math64.h> +#include <linux/log2.h> +#include <dm/device_compat.h> + +#define CLOCK_CONTROL 0 +#define COUNTER_CONTROL 0xc +#define INTERVAL_COUNTER 0x24 +#define MATCH_1_COUNTER 0x30 + +#define CLK_FALLING_EDGE BIT(6) +#define CLK_SRC_EXTERNAL BIT(5) +#define CLK_PRESCALE_MASK GENMASK(4, 1) +#define CLK_PRESCALE_ENABLE BIT(0) + +#define COUNTER_WAVE_POL BIT(6) +#define COUNTER_WAVE_DISABLE BIT(5) +#define COUNTER_RESET BIT(4) +#define COUNTER_MATCH_ENABLE BIT(3) +#define COUNTER_DECREMENT_ENABLE BIT(2) +#define COUNTER_INTERVAL_ENABLE BIT(1) +#define COUNTER_COUNTING_DISABLE BIT(0) + +#define NSEC_PER_SEC 1000000000L + +#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32)) +#define TTC_CLOCK_CONTROL(reg, channel) \ + TTC_REG((reg) + CLOCK_CONTROL, (channel)) +#define TTC_COUNTER_CONTROL(reg, channel) \ + TTC_REG((reg) + COUNTER_CONTROL, (channel)) +#define TTC_INTERVAL_COUNTER(reg, channel) \ + TTC_REG((reg) + INTERVAL_COUNTER, (channel)) +#define TTC_MATCH_1_COUNTER(reg, channel) \ + TTC_REG((reg) + MATCH_1_COUNTER, (channel)) + +struct cadence_ttc_pwm_plat { + u8 *regs; + u32 timer_mask; +}; + +struct cadence_ttc_pwm_priv { + u8 *regs; + u32 timer_mask; + unsigned long frequency; + bool invert[2]; +}; + +static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + priv->invert[channel] = polarity; + + dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity); + + return 0; +} + +static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + u32 counter_ctrl, clock_ctrl; + int period_clocks, duty_clocks, prescaler; + + dev_dbg(dev, "channel %d, duty %d/ period %d ns\n", channel, + duty_ns, period_ns); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + /* Make sure counter is stopped */ + counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel)); + setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_COUNTING_DISABLE); + + /* Calculate period, prescaler and set clock control register */ + period_clocks = div64_u64(((int64_t)period_ns * priv->frequency), + NSEC_PER_SEC); + + prescaler = ilog2(period_clocks) + 1 - 16; + if (prescaler < 0) + prescaler = 0; + + clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel)); + + if (!prescaler) { + clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK); + } else { + clock_ctrl &= ~CLK_PRESCALE_MASK; + clock_ctrl |= CLK_PRESCALE_ENABLE; + clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1); + }; + + /* External source is not handled by this driver now */ + clock_ctrl &= ~CLK_SRC_EXTERNAL; + + writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel)); + + /* Calculate interval and set counter control value */ + duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency), + NSEC_PER_SEC); + + writel((period_clocks >> prescaler) & priv->timer_mask, + TTC_INTERVAL_COUNTER(priv->regs, channel)); + writel((duty_clocks >> prescaler) & priv->timer_mask, + TTC_MATCH_1_COUNTER(priv->regs, channel)); + + /* Restore/reset counter */ + counter_ctrl &= ~COUNTER_DECREMENT_ENABLE; + counter_ctrl |= COUNTER_INTERVAL_ENABLE | + COUNTER_RESET | + COUNTER_MATCH_ENABLE; + + if (priv->invert[channel]) + counter_ctrl |= COUNTER_WAVE_POL; + else + counter_ctrl &= ~COUNTER_WAVE_POL; + + writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel)); + + dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks, + period_clocks, prescaler); + + return 0; +}; + +static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel, + bool enable) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel); + + if (enable) { + clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_COUNTING_DISABLE | + COUNTER_WAVE_DISABLE); + setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_RESET); + } else { + setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_COUNTING_DISABLE | + COUNTER_WAVE_DISABLE); + } + + return 0; +}; + +static int cadence_ttc_pwm_probe(struct udevice *dev) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev); + struct clk clk; + int ret; + + priv->regs = plat->regs; + priv->timer_mask = plat->timer_mask; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + priv->frequency = clk_get_rate(&clk); + if (IS_ERR_VALUE(priv->frequency)) { + dev_err(dev, "failed to get rate\n"); + return priv->frequency; + } + dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency); + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + return 0; +} + +static int cadence_ttc_pwm_of_to_plat(struct udevice *dev) +{ + struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev); + const char *cells; + u32 timer_width; + + cells = dev_read_prop(dev, "#pwm-cells", NULL); + if (!cells) + return -EINVAL; + + plat->regs = dev_read_addr_ptr(dev); + + timer_width = dev_read_u32_default(dev, "timer-width", 16); + plat->timer_mask = GENMASK(timer_width - 1, 0); + + return 0; +} + +static const struct pwm_ops cadence_ttc_pwm_ops = { + .set_invert = cadence_ttc_pwm_set_invert, + .set_config = cadence_ttc_pwm_set_config, + .set_enable = cadence_ttc_pwm_set_enable, +}; + +static const struct udevice_id cadence_ttc_pwm_ids[] = { + { .compatible = "cdns,ttc" }, + { } +}; + +U_BOOT_DRIVER(cadence_ttc_pwm) = { + .name = "cadence_ttc_pwm", + .id = UCLASS_PWM, + .of_match = cadence_ttc_pwm_ids, + .ops = &cadence_ttc_pwm_ops, + .of_to_plat = cadence_ttc_pwm_of_to_plat, + .probe = cadence_ttc_pwm_probe, + .priv_auto = sizeof(struct cadence_ttc_pwm_priv), + .plat_auto = sizeof(struct cadence_ttc_pwm_plat), +}; -- 2.33.0

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[PATCH v1 0/2] pinctrl single: GPIO support
by Bharat Kumar Reddy Gooty 06 Oct '21

06 Oct '21

From: Bharat Gooty <bharat.gooty(a)broadcom.com> pinctrl-single:- Add support to parse "pinctrl-single,gpio-range" and "#pinctrl-single,gpio-range-cells" DT properties Add pinctrl_ops request() Bharat Gooty (2): pinctrl: single: Parse gpio details from dt pinctrl: single: Add request() api drivers/pinctrl/pinctrl-single.c | 86 ++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) -- 2.17.1 -- This electronic communication and the information and any files transmitted with it, or attached to it, are confidential and are intended solely for the use of the individual or entity to whom it is addressed and may contain information that is confidential, legally privileged, protected by privacy laws, or otherwise restricted from disclosure to anyone else. If you are not the intended recipient or the person responsible for delivering the e-mail to the intended recipient, you are hereby notified that any use, copying, distributing, dissemination, forwarding, printing, or copying of this e-mail is strictly prohibited. If you received this e-mail in error, please return the e-mail to the sender, delete it from your computer, and destroy any printed copy of it.

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[PATCH v1 0/2] Broadcom netXtreme driver and commands
by Bharat Kumar Reddy Gooty 05 Oct '21

05 Oct '21

From: Bharat Gooty <bharat.gooty(a)broadcom.com> Broadcom netXtreme controller supports multiple ports and multiple link speeds like 10/25/50/100G 1. Added driver support for netXtreme controller 2. Added commands to know the port used, supported speeds, configure link speeds and MAC address. Bharat Gooty (2): net: brcm: netXtreme driver cmd: brcm: netXtreme commands cmd/Kconfig | 2 + cmd/broadcom/Kconfig | 10 + cmd/broadcom/Makefile | 3 +- cmd/broadcom/bnxt.c | 237 ++++ drivers/net/Kconfig | 1 + drivers/net/Makefile | 1 + drivers/net/bnxt/Kconfig | 7 + drivers/net/bnxt/Makefile | 5 + drivers/net/bnxt/bnxt.c | 2025 +++++++++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_dbg.h | 538 ++++++++++ drivers/net/bnxt/pci_ids.h | 17 + include/broadcom/bnxt.h | 419 ++++++++ include/broadcom/bnxt_hsi.h | 889 +++++++++++++++ include/broadcom/bnxt_ver.h | 22 + 14 files changed, 4175 insertions(+), 1 deletion(-) create mode 100644 cmd/broadcom/Kconfig create mode 100644 cmd/broadcom/bnxt.c create mode 100644 drivers/net/bnxt/Kconfig create mode 100644 drivers/net/bnxt/Makefile create mode 100644 drivers/net/bnxt/bnxt.c create mode 100644 drivers/net/bnxt/bnxt_dbg.h create mode 100644 drivers/net/bnxt/pci_ids.h create mode 100644 include/broadcom/bnxt.h create mode 100644 include/broadcom/bnxt_hsi.h create mode 100644 include/broadcom/bnxt_ver.h -- 2.17.1 -- This electronic communication and the information and any files transmitted with it, or attached to it, are confidential and are intended solely for the use of the individual or entity to whom it is addressed and may contain information that is confidential, legally privileged, protected by privacy laws, or otherwise restricted from disclosure to anyone else. If you are not the intended recipient or the person responsible for delivering the e-mail to the intended recipient, you are hereby notified that any use, copying, distributing, dissemination, forwarding, printing, or copying of this e-mail is strictly prohibited. If you received this e-mail in error, please return the e-mail to the sender, delete it from your computer, and destroy any printed copy of it.

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[PATCH] sunxi: h3: enable clock support for r_pio gpios
by Manuel Dipolt 05 Oct '21

05 Oct '21

This patch enables clock for the r_pio gpios for the h3 Signed-off-by: Manuel Dipolt <manuel.dipolt(a)robart.cc> --- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_h3-r.c | 51 ++++++++++++++++++++++++++++++++++++ drivers/gpio/sunxi_gpio.c | 9 +++++++ 3 files changed, 61 insertions(+) create mode 100644 drivers/clk/sunxi/clk_h3-r.c diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 36fb2aeb56..e93fe3c2f3 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -15,5 +15,6 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o +obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3-r.o obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_h3-r.c b/drivers/clk/sunxi/clk_h3-r.c new file mode 100644 index 0000000000..a314e37b87 --- /dev/null +++ b/drivers/clk/sunxi/clk_h3-r.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 RobArt GmbH + * Author: Manuel Dipolt <manuel.dipolt(a)robart.cc> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> + +static struct ccu_clk_gate h3_r_gates[] = { + [CLK_APB0_PIO] = GATE(0x28, BIT(0)), +}; + +static struct ccu_reset h3_r_resets[] = { + [RST_APB0_IR] = RESET(0x0b0, BIT(2)), + [RST_APB0_TIMER] = RESET(0x0b0, BIT(3)), + [RST_APB0_UART] = RESET(0x0b0, BIT(4)), + [RST_APB0_I2C] = RESET(0x0b0, BIT(6)), +}; + +static const struct ccu_desc h3_r_ccu_desc = { + .gates = h3_r_gates, + .resets = h3_r_resets, +}; + +static int h3_r_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(h3_r_resets)); +} + +static const struct udevice_id h3_r_ccu_ids[] = { + { .compatible = "allwinner,sun8i-h3-r-ccu", + .data = (ulong)&h3_r_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_h3_r) = { + .name = "sun8i_h3-r_ccu", + .id = UCLASS_CLK, + .of_match = h3_r_ccu_ids, + .priv_auto_alloc_size = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = h3_r_clk_bind, +}; + diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index cbed8d42b7..b505be4065 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -14,6 +14,7 @@ #include <errno.h> #include <fdtdec.h> #include <malloc.h> +#include <clk.h> #include <asm/arch/gpio.h> #include <asm/io.h> #include <asm/gpio.h> @@ -262,6 +263,14 @@ static int gpio_sunxi_probe(struct udevice *dev) { struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk gate_clk; + int ret; + + ret = clk_get_by_name(dev, "apb", &gate_clk); + + if (!ret) + clk_enable(&gate_clk); + /* Tell the uclass how many GPIOs we have */ if (plat) { -- 2.20.1

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[PATCH] dt-bindings: pinctrl: k3: Synchronize with v5.14 kernel
by Nishanth Menon 04 Oct '21

04 Oct '21

Synchronize with the upstream version as of v5.14 kernel tag Signed-off-by: Nishanth Menon <nm(a)ti.com> --- NOTE: checkpatch complains about BIT() macro usage, but I propose that we are better off staying in sync with the kernel tag itself. include/dt-bindings/pinctrl/k3.h | 51 +++++++++++++++----------------- 1 file changed, 24 insertions(+), 27 deletions(-) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e6cb1d0540e6..e085f102b283 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -1,36 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This header provides constants for TI K3-AM65 pinctrl bindings. + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. * - * Copyright (C) 2018-2021 Texas Instruments + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H -#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_200MHZ 0 -#define SLEWCTRL_150MHZ (1 << 19) -#define SLEWCTRL_100MHZ (2 << 19) -#define SLEWCTRL_50MHZ (3 << 19) -#define TX_DIS (1 << 21) -#define ISO_OVR (1 << 22) -#define ISO_BYPASS (1 << 23) -#define DS_EN (1 << 24) -#define DS_INPUT (1 << 25) -#define DS_FORCE_OUT_HIGH (1 << 26) -#define DS_PULL_UP_DOWN_EN 0 -#define DS_PULL_UP_DOWN_DIS (1 << 27) -#define DS_PULL_UP_SEL (1 << 28) -#define WAKEUP_ENABLE (1 << 29) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H +#define _DT_BINDINGS_PINCTRL_TI_K3_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) #define PIN_INPUT (INPUT_EN | PULL_DISABLE) #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -- 2.32.0

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