June 2021 - U-Boot

[PATCH 0/3] J7200: Add support for HS400 speed mode
by Aswath Govindraju 29 Jul '21

29 Jul '21

The following series of patches add support for HS400 speed mode on J7200 SoC. For HS400 support to work, the following series of patches depend on, https://patchwork.ozlabs.org/project/uboot/patch/20210405144428.12159-1-a-g… Aswath Govindraju (3): mmc: sdhci_am654: Read ti,strobe-sel property from device tree arm: dts: k3-j7200-main: Add support for HS400 and update delay select values for MMCSD subsystems configs: j7200_evm_*_defconfig: Enable configs for HS400 support arch/arm/dts/k3-j7200-main.dtsi | 11 ++++++++++- configs/j7200_evm_a72_defconfig | 4 ++-- configs/j7200_evm_r5_defconfig | 2 +- drivers/mmc/am654_sdhci.c | 1 + 4 files changed, 14 insertions(+), 4 deletions(-) -- 2.17.1

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[PATCH] arm: bootm: Disable LMB reservation for command line and board info on arm64
by Marek Vasut 29 Jul '21

29 Jul '21

On arm64, board info is not applicable and kernel command line patched into the DT, so the LMB reservation here makes no sense anymore. On legacy arm32, this might still be necessary on systems which do not use DT or use legacy ATAGS. Disable this LMB reservation on arm64. This also permits Linux DT to specify reserved memory node at address close to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after boot, U-Boot will be no more, this is OK. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Hai Pham <hai.pham.ud(a)renesas.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/lib/bootm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f60ee3a7e6..23b99a541c 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; +#ifndef CONFIG_ARM64 static ulong get_sp(void) { ulong ret; @@ -86,6 +87,7 @@ void arch_lmb_reserve(struct lmb *lmb) break; } } +#endif __weak void board_quiesce_devices(void) { -- 2.30.2

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[PATCH v10 00/27] mtd: spi-nor-core: add xSPI Octal DTR support
by Pratyush Yadav 28 Jul '21

28 Jul '21

Hi, This series adds support for octal DTR flashes in the SPI NOR framework, and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA flashes. The Cadence QSPI controller driver is also updated to run in Octal DTR mode. Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested on MT25QU512A for regressions. Changes in v10: - Rebase on top of u-boot-spi/next and fix conflicts. Changes in v9: - Fix a typo in patch 26 commit message. - Add Sean's Reviewed-by in patch 3. - Drop the 2-byte check from spi_mem_dtr_supports_op(). Instead, perform a even-byte length check on all 4 phases. Only do this when the buswidth of the phase is 8. - Make template ops in spi_nor_check_readop() and spi_nor_check_pp() have 2-byte data phase so they don't get rejected when 8D-8D-8D protocol is being used. Changes in v8: - Rebase on latest master, fixing merge conflicts. - Fix a regression related to address width that was discovered on Linux. - Port spi_mem_dtr_supports_op() from Linux and use it in Cadence qspi driver. - Do not set non-volatile Uniform Sector mode bit on S28HS512T. Instead use Takahiro's non-uniform erase patch to enable non-uniform erases. - Make sure spi_nor_write_reg() does not set data direction to out when there is no data to write, like in write enable. - Set buswidths to 0 before calling spi_nor_setup_op(), like how it is done in Linux. Changes in v7: - Port back changes requested on the Linux series. - Introduce the flag SPI_NOR_OCTAL_DTR_PP to indicate 8D page program support since it can't be detected from SFDP. - Re-order Profile 1.0 related defines by DWORD order. - Drop local variables addr_width and dummy in spi_nor_read_sr() spi_nor_read_fsr(). - Do not make having command opcode extension as a reserved field fatal. - Update doc comment for spi_nor_parse_profile1() and spi_nor_cypress_octal_dtr_enable() to add missing fields. - Move rdsr parameter parsing to where opcode is parsed because it is from the same DWORD. - Convert a comment in Profile 1.0 parsing from multi-line to one line. - Rename 'table' to 'dwords' in xSPI Profile 1.0 parsing. - Update spi_nor_check_readop() and spi_nor_check_pp() to use spi_nor_setup_op() so the buswidths are properly set up for DTR ops. - Do not set Uniform Sector bit on the Cypress S28HS512T flash if it is already set. It will avoid wearing out the non-volatile bit. - Enable DQS for Micron MT35XU512ABA. No reason not to. - Avoid enabling 4-byte addressing mode for all DTR ops instead of just Octal DTR ops. This is based on the assumption that DTR ops can only use 4-byte addressing. - Make spi_nor_set_fixups() static. - Add flag SPI_NOR_OCTAL_DTR_PP to both Cypress S28HS512T and Micron MT35XU512ABA. - Use values set up by spi-{rx,tx}-bus-width via device tree to determine if the controller supports the op or not. Gives more flexibility to choose protocol per-board. - Use tiny SPI NOR on x530 because of size constraints. Changes in v6: - Use "# CONFIG_SPI_FLASH_SMART_HWCAPS is not set" instead of "CONFIG_SPI_FLASH_SMART_HWCAPS=n" in x530_defconfig. Changes in v5: - Fix build breaking when CONFIG_SPL_SPI_FLASH_TINY is enabled because spi-nor-tiny did not have spi_nor_remove(). - The build was breaking in x530 because of SPL size too big. Fix it by the below changes. - Re-introduce old hwcaps selection logic and put the new one behind a config. This lets boards with size restrictions use the old logic which takes up less space. The code was getting hard to manage with the old code behind ifdefs. So, re-structure the old hwcaps selection logic and move it into one function: spi_nor_adjust_hwcaps(). This way, the common code just calls spi_nor_adjust_hwcaps(), but the old or new hwcaps selection is used based on the config option selected. - Put spi_nor_soft_reset() behind the config option SPI_NOR_SOFT_RESET. - Rename the config option used for soft resetting on boot to SPI_NOR_SOFT_RESET_ON_BOOT to make its intention clearer. - Put the fixup hooks of MT35XU512ABA and S28HS512T flashes behind config options to reduce code size on platforms that don't need them. - Introduce spi_nor_set_fixups(). Earlier, the fixup members of each flash was specified in spi-nor-ids.c. This meant they had to be declared as extern in sf_internal.h. But since spi-nor-tiny.c also uses it, and it doesn't have those fixups, they had to be put behind in an ifdef. The ".fixups = " assignment in spi-nor-ids.c also had to be put in an ifdef to account for spi-nor-tiny.c not having the fixup hooks. On top of this, the fixup of each flash is behind the flash's config. All this lead to a soup of ifdefs that wasn't easy to digest. So don't set the fixups in the common code. Instead, add a function in spi-nor-core.c that sets the fixups of each flash. This isn't ideal, but its the best compromise I could figure out. - Build were breaking with boards that use spi-mem-nodm.c because it doesn't have spi_mem_supports_op() which is needed for smart hwcaps selection. Add an equivalent to spi_mem_default_supports_op() there. - Replace uses of sizeof(op->cmd.opcode) with op->cmd.nbytes. - Do not set quad_enable to NULL if the value is set to reserved. Instead just print a warning and go on. quad_enable should be set to NULL in fixup hooks instead. Suggested on the Linux list. - Set dummy cycles for DTR mode in spi_nor_micron_octal_dtr_enable() instead of in the post sfdp hook. This keeps the flash functional in case Octal DTR mode is not selected. - Only use nor->rdsr_addr_nbytes and nor->rdsr_dummy when in Octal DTR mode. This makes sure the flash is functional in case Octal DTR is not selected. - Rebase on latest master and fix a small merge conflict. Changes in v4: - Fix BFPT parsing stopping too early for JESD216 rev B flashes. - Instead of just checking for spi_nor_get_protocol_width() in spi_nor_octal_dtr_enable(), make sure the protocol is SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data width. - Do not enable stateful X-X-X modes if the reset line is broken. - Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table parsing, do it in spi_nor_info_init_params() instead based on the SPI_NOR_OCTAL_DTR_READ flag instead. - Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this capability is no longer set in Profile 1.0 parsing. - Rename spi_nor_cypress_octal_enable() to spi_nor_cypress_octal_dtr_enable(). - Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find them out from the Profile 1.0 table. - Call post-bfpt fixup when exiting early because of JESD rev A. - Do not make an invalid Quad Enable BFPT field a fatal error. Silently ignore it by assuming no quad enable bit is present. - Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD(). - Reject ops with more than 1 command byte in spi_mem_default_supports_op(). - Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability via BFPT. - Add missing headers that were removed from common header. Changes in v3: - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid tripping up controllers. - Use op->data.nbytes as a measure of whether the data phase exists or not. This fixes data buswidth not being updadted for SR and FSR reads because they keep data buffer as NULL when calling spi_nor_setup_op(). - Add support for Micron mt35xu512aba to run in Octal DTR mode. Pratyush Yadav (26): spi: spi-mem: allow specifying whether an op is DTR or not spi: spi-mem: allow specifying a command's extension spi: spi-mem: export spi_mem_default_supports_op() spi: spi-mem: add spi_mem_dtr_supports_op() spi: cadence-qspi: Do not calibrate when device tree sets read delay spi: cadence-qspi: Add a small delay before indirect writes spi: cadence-qspi: Add support for octal DTR flashes mtd: spi-nor-core: Fix address width on flash chips > 16MB mtd: spi-nor-core: Add a ->setup() hook mtd: spi-nor-core: Move SFDP related declarations to top mtd: spi-nor-core: Introduce flash-specific fixup hooks mtd: spi-nor-core: Rework hwcaps selection mtd: spi-nor-core: Do not set data direction when there is no data mtd: spi-nor-core: Add support for DTR protocol mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D mtd: spi-nor-core: Get command opcode extension type from BFPT mtd: spi-nor-core: Parse xSPI Profile 1.0 table mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode mtd: spi-nor-core: Enable octal DTR mode when possible mtd: spi-nor-core: Do not make invalid quad enable fatal mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT mtd: spi-nor-core: Perform a Soft Reset on shutdown mtd: spi-nor-core: Perform a Soft Reset on boot mtd: spi-nor-core: allow truncated erases mtd: spi-nor-core: Add support for Cypress Semper flash mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode Takahiro Kuwano (1): mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress drivers/mtd/spi/Kconfig | 42 + drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/sf_probe.c | 6 + drivers/mtd/spi/spi-nor-core.c | 1447 ++++++++++++++++++++++++++------ drivers/mtd/spi/spi-nor-ids.c | 7 +- drivers/mtd/spi/spi-nor-tiny.c | 22 - drivers/spi/cadence_qspi.c | 69 +- drivers/spi/cadence_qspi.h | 16 +- drivers/spi/cadence_qspi_apb.c | 292 ++++++- drivers/spi/mtk_snfi_spi.c | 3 +- drivers/spi/spi-mem-nodm.c | 66 +- drivers/spi/spi-mem.c | 46 +- include/linux/mtd/spi-nor.h | 279 ++++-- include/spi-mem.h | 19 +- 14 files changed, 1921 insertions(+), 394 deletions(-) -- 2.30.0

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[PATCH] sunxi: Load sun8i secure monitor to SRAM A2
by Samuel Holland 27 Jul '21

27 Jul '21

Most sun6i-derived SoCs contain SRAM A2, a secure SRAM area for ARISC SCP firmware. H3 has a smaller SRAM than other SoCs (A31/A33/A23/A83T). On sun8i SoCs which do not have SRAM B, we can use part of this SRAM for the secure monitor. Follow the design of 64-bit SoCs and use the first part for the monitor, and the last 16 KiB for the SCP firmware. With this change, the monitor no longer needs to reserve a region in DRAM. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 11 +++++++++++ include/configs/sun8i.h | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 02ce73954d..d4c795d89c 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -11,7 +11,18 @@ #define SUNXI_SRAM_A1_BASE 0x00000000 #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ +#if defined(CONFIG_SUNXI_GEN_SUN6I) && \ + !defined(CONFIG_MACH_SUN8I_R40) && \ + !defined(CONFIG_MACH_SUN8I_V3S) +#define SUNXI_SRAM_A2_BASE 0x00040000 +#ifdef CONFIG_MACH_SUN8I_H3 +#define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */ +#else +#define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */ +#endif +#else #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#endif #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 9b4675e4c3..545d27996c 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -12,6 +12,13 @@ * A23 specific configuration */ +/* + * Skip the first 16 KiB of SRAM A2, which is not usable, as only certain bytes + * are writable. Reserve the last 17 KiB for the resume shim and SCP firmware. + */ +#define CONFIG_ARMV7_SECURE_BASE (SUNXI_SRAM_A2_BASE + 16 * 1024) +#define CONFIG_ARMV7_SECURE_MAX_SIZE (SUNXI_SRAM_A2_SIZE - 33 * 1024) + /* * Include common sunxi configuration where most the settings are */ -- 2.26.3

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[PATCH v4 0/5] stm32mp: Enable OP-TEE and TZC support in SPL
by Alexandru Gagniuc 27 Jul '21

27 Jul '21

The purpose of this series is to allow booting an OP-TEE image from SPL, by corectly configuring the TrustZone (TZC) memory regions. Although TZC400 is a generic silicon logic that could apply to other mach- families, support is currently restricted to stm32mp. I have neither a feasible way nor interest in validating this for other chips. It's fairly trivial to move the code from mach- to arch/, should another use case arise. The configuration of the memory regions is devicetree-driven, so there isn't much to hardcode, However the delineation between OP-TEE secure memory and shared memory is not given in the devicetree. This is the one thing that has to be hardcoded. Changes since v3: - Pass a "phys_size_t *" to ofnode_get_addr_size() to resolve warning - s/u-boot,dm-pre-reloc/u-boot,dm-spl/ in devicetree for clarity Changes since v2: - Use ram_get_info() instead of ofnode_read("st,mem-size") - Only hardcode shared memory size instead of TZDRAM size - Use log_info() instead of pr_info() Changes since v1: - Removed "Weak functions are stupid" comment - Addressed blank line complaints from checkpatch Alexandru Gagniuc (5): spl: mmc: Support OP-TEE payloads in Falcon mode spl: Introduce spl_board_prepare_for_optee() hook arm: stm32mp: Implement support for TZC 400 controller stm32mp1: spl: Configure TrustZone controller for OP-TEE ARM: dts: stm32mp: Add OP-TEE reserved memory to SPL dtb arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 + arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/include/mach/tzc.h | 33 ++++++ arch/arm/mach-stm32mp/spl.c | 92 +++++++++++++++ arch/arm/mach-stm32mp/tzc400.c | 136 +++++++++++++++++++++++ common/spl/spl.c | 5 + common/spl/spl_mmc.c | 6 +- include/spl.h | 14 +++ 8 files changed, 288 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-stm32mp/include/mach/tzc.h create mode 100644 arch/arm/mach-stm32mp/tzc400.c -- 2.31.1

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[PATCH 1/2] phy: meson-axg-mipi: Rename "priv_auto_alloc_size" to "priv_auto"
by Alper Nebi Yasak 27 Jul '21

27 Jul '21

With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". Apply the rename to these two drivers as well. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Fixes: 7ef19503bacf ("phy: Add Amlogic AXG MIPI D-PHY driver") Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- drivers/phy/meson-axg-mipi-dphy.c | 2 +- drivers/phy/meson-axg-mipi-pcie-analog.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c index 8b2469793ddc..cf2a1cd14c7f 100644 --- a/drivers/phy/meson-axg-mipi-dphy.c +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -389,5 +389,5 @@ U_BOOT_DRIVER(meson_axg_mipi_dphy) = { .of_match = meson_axg_mipi_dphy_ids, .probe = meson_axg_mipi_dphy_probe, .ops = &meson_axg_mipi_dphy_ops, - .priv_auto_alloc_size = sizeof(struct phy_meson_axg_mipi_dphy_priv), + .priv_auto = sizeof(struct phy_meson_axg_mipi_dphy_priv), }; diff --git a/drivers/phy/meson-axg-mipi-pcie-analog.c b/drivers/phy/meson-axg-mipi-pcie-analog.c index 276e6004e5ee..7106c23d508f 100644 --- a/drivers/phy/meson-axg-mipi-pcie-analog.c +++ b/drivers/phy/meson-axg-mipi-pcie-analog.c @@ -229,5 +229,5 @@ U_BOOT_DRIVER(meson_axg_mipi_pcie_analog) = { .of_match = meson_axg_mipi_pcie_analog_ids, .probe = meson_axg_mipi_pcie_analog_probe, .ops = &meson_axg_mipi_pcie_analog_ops, - .priv_auto_alloc_size = sizeof(struct phy_meson_axg_mipi_pcie_analog_priv), + .priv_auto = sizeof(struct phy_meson_axg_mipi_pcie_analog_priv), }; -- 2.31.1

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[PATCH] meson64: add kernel compression vars
by Artem Lapkin 27 Jul '21

27 Jul '21

make possible to load simple compressed linux kernel for meson64 Signed-off-by: Artem Lapkin <art(a)khadas.com> --- include/configs/meson64.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index e3d25493..552a08c2 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -113,6 +113,8 @@ "stdin=" STDIN_CFG "\0" \ "stdout=" STDOUT_CFG "\0" \ "stderr=" STDOUT_CFG "\0" \ + "kernel_comp_addr_r=0x0d080000\0" \ + "kernel_comp_size=0x2000000\0" \ "fdt_addr_r=0x08008000\0" \ "loadaddr=0x01000000\0" \ "scriptaddr=0x08000000\0" \ -- 2.25.1

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[PATCH v4 0/3] Add reboot mode support
by Nandor Han 23 Jul '21

23 Jul '21

Description ----------- Add support for reboot-mode configuration using GPIOs and RTC SRAM as back-end. Testing ------- Tested on a Zynq based board where device tree was configured to contain the reboot-mode configuration: &amba { status = "okay"; reboot-mode-gpio { compatible = "reboot-mode-gpio"; gpios = <&gpio0 47 GPIO_ACTIVE_LOW>; mode-test = <0x1>; }; reboot-mode-rtc { compatible = "reboot-mode-rtc"; rtc = <&rtc_0>; reg = <0x14 4>; mode-test = <0x21969147>; }; }; In addition to this and not part of this patchset is a change to board.c where GPIO or RTC SRAM backed is selected dynamically at runtime. 1. Test that the reboot mode configured in user-space is read in U-Boot and environment configured: PASS Userspace ~ # reboot test .... [ 177.335936] reboot: Restarting system with command 'test' U-Boot SPL 2019.01 (Mar 29 2019 - 10:44:22 +0000) ... U-Boot> print reboot-mode reboot-mode=test 2. Reset the system using the reset command and stop in U-Boot. 3. Verify that reboot-mode env variable is not configured anymore: PASS U-Boot> print reboot-mode ## Error: "reboot-mode" not defined 4. Toggle the GPIO configured for test mode to active and reset the system with command reset. 5. Stop in U-Boot and check that reboot-mode env variable is configured:PASS U-Boot> print reboot-mode reboot-mode=test 6. Verify that unit-tests are successful: PASS ``` localhost /u-boot-latest (wip-reboot-mode)> ./test/py/test.py --bd sandbox --build -k ut_dm_reboot_mode -v ... test/py/tests/test_ut.py::test_ut[ut_dm_reboot_mode_gpio] PASSED [ 50%] test/py/tests/test_ut.py::test_ut[ut_dm_reboot_mode_rtc] PASSED [100%] ========================================================== 2 passed, 759 deselected in 0.40 seconds ========================================================== ``` Changes since v1: ---------------- - rebased Changes since v2: ---------------- - unit-tests added Changes since v3: ---------------- - rebased - fix the struct udevice and struct driver incompatibilities Nandor Han (3): reboot-mode: add support for reboot mode control reboot-mode: read the boot mode from GPIOs status reboot-mode: read the boot mode from RTC memory arch/sandbox/dts/test.dts | 18 +++ configs/sandbox_defconfig | 3 + .../reboot-mode/reboot-mode-gpio.txt | 20 +++ .../reboot-mode/reboot-mode-rtc.txt | 22 +++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/reboot-mode/Kconfig | 36 +++++ drivers/reboot-mode/Makefile | 9 ++ drivers/reboot-mode/reboot-mode-gpio.c | 128 +++++++++++++++++ drivers/reboot-mode/reboot-mode-rtc.c | 127 +++++++++++++++++ drivers/reboot-mode/reboot-mode-uclass.c | 134 ++++++++++++++++++ include/dm/uclass-id.h | 1 + include/reboot-mode/reboot-mode-gpio.h | 32 +++++ include/reboot-mode/reboot-mode-rtc.h | 16 +++ include/reboot-mode/reboot-mode.h | 56 ++++++++ test/dm/Makefile | 1 + test/dm/reboot-mode.c | 71 ++++++++++ 17 files changed, 677 insertions(+) create mode 100644 doc/device-tree-bindings/reboot-mode/reboot-mode-gpio.txt create mode 100644 doc/device-tree-bindings/reboot-mode/reboot-mode-rtc.txt create mode 100644 drivers/reboot-mode/Kconfig create mode 100644 drivers/reboot-mode/Makefile create mode 100644 drivers/reboot-mode/reboot-mode-gpio.c create mode 100644 drivers/reboot-mode/reboot-mode-rtc.c create mode 100644 drivers/reboot-mode/reboot-mode-uclass.c create mode 100644 include/reboot-mode/reboot-mode-gpio.h create mode 100644 include/reboot-mode/reboot-mode-rtc.h create mode 100644 include/reboot-mode/reboot-mode.h create mode 100644 test/dm/reboot-mode.c -- 2.26.3

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[PATCH] fit: Allow external data for FDTs
by John Keeping 23 Jul '21

23 Jul '21

Switch to fit_image_get_data_and_size() for consistency with all other data loaded from FIT. Signed-off-by: John Keeping <john(a)metanate.com> --- common/image-fit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/image-fit.c b/common/image-fit.c index 94501b1071..4c5a24806d 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1772,7 +1772,8 @@ int fit_conf_find_compat(const void *fit, const void *fdt) } /* search in this config's kernel FDT */ - if (fit_image_get_data(fit, kfdt_noffset, &fdt, &sz)) { + if (fit_image_get_data_and_size(fit, kfdt_noffset, + &fdt, &sz)) { debug("Failed to get fdt \"%s\".\n", kfdt_name); continue; } -- 2.32.0

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[PATCH] cmd: part: Correct error handling
by Anders Dellien 23 Jul '21

23 Jul '21

As 'part_get_info_by_name' now returns more status codes than just -1 to indicate failure, we need to update the return value check. Signed-off-by: Anders Dellien <anders.dellien(a)arm.com> --- cmd/part.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/part.c b/cmd/part.c index 3395c17b89..e0463b5a54 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -140,7 +140,7 @@ static int do_part_info(int argc, char *const argv[], enum cmd_part_info param) return 1; } else { part = part_get_info_by_name(desc, argv[2], &info); - if (part == -1) + if (part < 0) return 1; } -- 2.17.1

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