April 2021 - U-Boot

[PATCH 1/9] net: eqos: Add PHY reset control for i.MX platform
by Ye Li 21 Jul '21

21 Jul '21

Parse the "phy-reset-gpios", "phy-reset-post-delay" and "phy-reset-duration" properties from eqos node to control the ethernet PHY reset at driver probe. Reset PHY once is enough that can reduce the time cost to get IP after the first time. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/net/dwc_eth_qos.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e8242ca..14aafc6 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -303,6 +303,8 @@ struct eqos_priv { struct eqos_tegra186_regs *tegra186_regs; struct reset_ctl reset_ctl; struct gpio_desc phy_reset_gpio; + uint32_t reset_delay; + uint32_t reset_post_delay; struct clk clk_master_bus; struct clk clk_rx; struct clk clk_ptp_ref; @@ -1880,6 +1882,7 @@ static int eqos_probe_resources_imx(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); phy_interface_t interface; + int ret = 0; debug("%s(dev=%p):\n", __func__, dev); @@ -1890,8 +1893,52 @@ static int eqos_probe_resources_imx(struct udevice *dev) return -EINVAL; } + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + pr_debug("gpio_request_by_name(phy reset) failed: %d", ret); + } + + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + eqos->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); + if (eqos->reset_delay > 1000) { + pr_err("phy reset duration should be <= 1000ms\n"); + /* property value wrong, use default value */ + eqos->reset_delay = 1; + } + + mdelay(eqos->reset_delay); + + eqos->reset_post_delay = dev_read_u32_default(dev, + "phy-reset-post-delay", + 0); + if (eqos->reset_post_delay > 1000) { + pr_err("phy reset post delay should be <= 1000ms\n"); + /* property value wrong, use default value */ + eqos->reset_post_delay = 0; + } + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + goto err_free_gpio_phy_reset; + } + + if (eqos->reset_post_delay) + mdelay(eqos->reset_post_delay); + } + debug("%s: OK\n", __func__); return 0; + +err_free_gpio_phy_reset: + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_free(dev, &eqos->phy_reset_gpio); + } + + debug("%s: returns %d\n", __func__, ret); + return ret; } static phy_interface_t eqos_get_interface_imx(struct udevice *dev) @@ -1951,6 +1998,14 @@ static int eqos_remove_resources_stm32(struct udevice *dev) static int eqos_remove_resources_imx(struct udevice *dev) { + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_free(dev, &eqos->phy_reset_gpio); + } + + debug("%s: OK\n", __func__); return 0; } -- 2.7.4

2 10

[PATCH v2 0/6] net: dwc_eth_qos: add support of device tree configuration for reset delay
by Patrick Delaunay 20 Jul '21

20 Jul '21

It is the V2 version of [1] after Marek remarks: all commit are new. I change the DWC_ETH_QOS STM32 variant by using generic eth phy driver. This driver is updated to use the gpio reset and assert/deassert delay from DT with the generic binding defined in linux: Documentation/devicetree/bindings/net/ethernet-phy.yaml or in U-Boot: doc/device-tree-bindings/net/phy.txt [1] net: dwc_eth_qos: add support of device tree configuration for reset delay http://patchwork.ozlabs.org/project/uboot/list/?series=238253&state=* Changes in v2: - Update eth-phy driver (NEW) - use log macro in eth-phy driver (NEW) - update eth-phy driver to support STM32 binding with a mdio0 subnode (NEW) - remove unused element in the struct eqos_priv (NEW) - use generic ethernet phy for stm32 variant, this patch is a REWORK of previous serie: the device parsing is done in eth-phy driver and the gpio support is removed in stm32 variant: eqos_start/stop_resets_stm32 and eqos_probe_resources_stm32. - cleanup ops by adding a common null ops (NEW) Patrick Delaunay (6): net: eth-phy: add support of device tree configuration for gpio reset net: eth-phy: use dev_dbg and log_notice net: eth-phy: manage subnode mdio0 net: dwc_eth_qos: remove the field phyaddr of the struct eqos_priv net: dwc_eth_qos: use generic ethernet phy for stm32 variant net: dwc: add a common empty ops eqos_null_ops drivers/net/Kconfig | 1 + drivers/net/dwc_eth_qos.c | 152 +++++------------------------------ drivers/net/eth-phy-uclass.c | 78 +++++++++++++++--- 3 files changed, 91 insertions(+), 140 deletions(-) -- 2.17.1

3 15

[PATCH] arm64: Update memcpy_{from, to}io() helpers
by Patrice Chotard 19 Jul '21

19 Jul '21

At early U-Boot stage, before relocation, MMU is not yet configured and disabled. DDR may not be configured with the correct memory attributes (can be configured in MT_DEVICE instead of MT_MEMORY). In this case, usage of memcpy_{from, to}io() may leads to synchronous abort in AARCH64 in case the normal memory address is not 64Bits aligned. To avoid such situation, forbid usage of normal memory cast to (u64 *) in case MMU is not enabled. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: mark.kettenis(a)xs4all.nl --- arch/arm/cpu/armv8/cache_v8.c | 10 ++++++++++ arch/arm/include/asm/io.h | 25 +++++++++++++++---------- include/cpu_func.h | 1 + 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 15cecb5e0b..3de18c7675 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -719,6 +719,11 @@ int icache_status(void) return (get_sctlr() & CR_I) != 0; } +int mmu_status(void) +{ + return (get_sctlr() & CR_M) != 0; +} + void invalidate_icache_all(void) { __asm_invalidate_icache_all(); @@ -740,6 +745,11 @@ int icache_status(void) return 0; } +int mmu_status(void) +{ + return 0; +} + void invalidate_icache_all(void) { } diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index df264a170b..36b840378a 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -338,6 +338,7 @@ extern void __readwrite_bug(const char *fn); /* Optimized copy functions to read from/write to IO sapce */ #ifdef CONFIG_ARM64 +#include <cpu_func.h> /* * Copy data from IO memory space to "real" memory space. */ @@ -351,11 +352,13 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) count--; } - while (count >= 8) { - *(u64 *)to = __raw_readq(from); - from += 8; - to += 8; - count -= 8; + if (mmu_status()) { + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } } while (count) { @@ -379,11 +382,13 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) count--; } - while (count >= 8) { - __raw_writeq(*(u64 *)from, to); - from += 8; - to += 8; - count -= 8; + if (mmu_status()) { + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } } while (count) { diff --git a/include/cpu_func.h b/include/cpu_func.h index 8aa825daa4..a8806dd295 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -59,6 +59,7 @@ int dcache_status(void); void dcache_enable(void); void dcache_disable(void); void mmu_disable(void); +int mmu_status(void); /* arch/$(ARCH)/lib/cache.c */ void enable_caches(void); -- 2.17.1

3 3

[PATCH] smbios: Fix calculating BIOS Release Date
by Pali Rohár 16 Jul '21

16 Jul '21

BIOS Release Date must be in format mm/dd/yyyy and must be release date. U-Boot currently sets BIOS Release Date from U_BOOT_DMI_DATE macro which is generated from current build timestamp. Fix this issue by setting U_BOOT_DMI_DATE macro to U-Boot version which is better approximation of U-Boot release date than current build timestamp. Current U-Boot versioning is in format yyyy.mm so as a day choose 01. Some operating systems are using BIOS Release Date for detecting when was SMBIOS table filled or if it could support some feature (e.g. BIOS from 1990 cannot support features invented in 2000). So this change also ensures that recompiling U-Boot from same sources but in different year does not change behavior of some operating systems. Macro U_BOOT_DMI_DATE is not used in other file than lib/smbios.c so remove it from global autogenerated files and also from Makefile. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- Makefile | 2 -- doc/develop/version.rst | 1 - lib/smbios.c | 23 +++++++++++++++++++++++ 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index e423f6de7468..4cd28bce237b 100644 --- a/Makefile +++ b/Makefile @@ -1832,7 +1832,6 @@ define filechk_timestamp.h LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ - LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \ else \ @@ -1842,7 +1841,6 @@ define filechk_timestamp.h LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ - LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \ fi) diff --git a/doc/develop/version.rst b/doc/develop/version.rst index a7797db41bb2..066901bcd2d9 100644 --- a/doc/develop/version.rst +++ b/doc/develop/version.rst @@ -84,7 +84,6 @@ fields. For example:: #define U_BOOT_DATE "Jan 06 2021" (US format only) #define U_BOOT_TIME "08:50:36" (24-hour clock) #define U_BOOT_TZ "-0700" (Time zone in hours) - #define U_BOOT_DMI_DATE "01/06/2021" (US format only) #define U_BOOT_BUILD_DATE 0x20210106 (hex yyyymmdd format) #define U_BOOT_EPOCH 1609948236 diff --git a/lib/smbios.c b/lib/smbios.c index 9eb226ec9fbd..e5cf05073543 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -8,6 +8,7 @@ #include <common.h> #include <dm.h> #include <env.h> +#include <linux/stringify.h> #include <mapmem.h> #include <smbios.h> #include <sysinfo.h> @@ -18,6 +19,28 @@ #include <dm/uclass-internal.h> #endif +/* Safeguard for checking that U_BOOT_VERSION_NUM macros are compatible with U_BOOT_DMI */ +#if U_BOOT_VERSION_NUM < 2000 || U_BOOT_VERSION_NUM > 2099 || \ + U_BOOT_VERSION_NUM_PATCH < 1 || U_BOOT_VERSION_NUM_PATCH > 12 +#error U_BOOT_VERSION_NUM macros are not compatible with DMI, fix U_BOOT_DMI macros +#endif + +/* + * U_BOOT_DMI_DATE contains BIOS Release Date in format mm/dd/yyyy. + * BIOS Release Date is calculated from U-Boot version and fixed day 01. + * So for U-Boot version 2021.04 it is calculated as "04/01/2021". + * BIOS Release Date should contain date when code was released + * and not when it was built or compiled. + */ +#if U_BOOT_VERSION_NUM_PATCH < 10 +#define U_BOOT_DMI_MONTH "0" __stringify(U_BOOT_VERSION_NUM_PATCH) +#else +#define U_BOOT_DMI_MONTH __stringify(U_BOOT_VERSION_NUM_PATCH) +#endif +#define U_BOOT_DMI_DAY "01" +#define U_BOOT_DMI_YEAR __stringify(U_BOOT_VERSION_NUM) +#define U_BOOT_DMI_DATE U_BOOT_DMI_MONTH "/" U_BOOT_DMI_DAY "/" U_BOOT_DMI_YEAR + DECLARE_GLOBAL_DATA_PTR; /** -- 2.20.1

5 8

[PATCH] riscv: booti: do not force relocation if force_reloc is not set
by Vitaly Wool 15 Jul '21

15 Jul '21

If force_reloc flag is not set and booti is called for an address ouside RAM (i. e. QSPI NOR flash), we should honor that and not try to force relocation in a bogus fashion. Signed-off-by: Vitaly Wool <vitaly.wool(a)konsulko.com> --- arch/riscv/lib/image.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c index 7357d3b07d..2032c2c399 100644 --- a/arch/riscv/lib/image.c +++ b/arch/riscv/lib/image.c @@ -48,7 +48,12 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, return -EINVAL; } *size = lhdr->image_size; - *relocated_addr = gd->ram_base + lhdr->text_offset; + if (force_reloc || + (gd->ram_base <= image && image < gd->ram_base + gd->ram_size)) { + *relocated_addr = gd->ram_base + lhdr->text_offset; + } else { + *relocated_addr = image; + } unmap_sysmem(lhdr); -- 2.29.2

2 1

[PATCH 1/4] phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ
by Ye Li 13 Jul '21

13 Jul '21

Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-imx8mq-usb.c | 197 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/phy/phy-imx8mq-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a..09cb744 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -268,5 +268,12 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config PHY_IMX8MQ_USB + bool "NXP i.MX8MQ USB PHY Driver" + depends on PHY + depends on IMX8MQ + help + Support the USB3.0 PHY in NXP i.MX8MQ SoC + source "drivers/phy/rockchip/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673..c6ad3b1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c new file mode 100644 index 0000000..afbc7ad --- /dev/null +++ b/drivers/phy/phy-imx8mq-usb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <clk.h> + +#define PHY_CTRL0 0x0 +#define PHY_CTRL0_REF_SSP_EN BIT(2) +#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) +#define PHY_CTRL0_FSEL_24M 0x2a +#define PHY_CTRL0_FSEL_100M 0x27 +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) + +#define PHY_CTRL1 0x4 +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_COMMONONN BIT(1) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20) + +#define PHY_CTRL2 0x8 +#define PHY_CTRL2_TXENABLEN0 BIT(8) +#define PHY_CTRL2_OTG_DISABLE BIT(9) + +#define PHY_CTRL3 0xc +#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0) +#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15) +#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15 +#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20) +#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20 +/* 1111: +24% ... 0000: -6% step: 2% */ +#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22) +#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22 +#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29) +#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29 + +#define PHY_CTRL4 0x10 +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15) +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15 + +#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) +#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0) + +#define PHY_CTRL6 0x18 +#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) +#define PHY_CTRL6_ALT_CLK_EN BIT(1) +#define PHY_CTRL6_ALT_CLK_SEL BIT(0) + +#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2) + +struct imx8mq_usb_phy { +#if CONFIG_IS_ENABLED(CLK) + struct clk phy_clk; +#endif + void __iomem *base; +}; + +static const struct udevice_id imx8mq_usb_phy_of_match[] = { + { + .compatible = "fsl,imx8mq-usb-phy", + }, + {}, +}; + +static int imx8mq_usb_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 | + PHY_CTRL1_COMMONONN); + value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(value, imx_phy->base + PHY_CTRL1); + + value = readl(imx_phy->base + PHY_CTRL0); + value |= PHY_CTRL0_REF_SSP_EN; + value &= ~PHY_CTRL0_SSC_RANGE_MASK; + value |= PHY_CTRL0_SSC_RANGE_4003PPM; + writel(value, imx_phy->base + PHY_CTRL0); + + value = readl(imx_phy->base + PHY_CTRL2); + value |= PHY_CTRL2_TXENABLEN0; + writel(value, imx_phy->base + PHY_CTRL2); + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(value, imx_phy->base + PHY_CTRL1); + + return 0; +} + +static int imx8mq_usb_phy_power_on(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + ret = clk_enable(&imx_phy->phy_clk); + if (ret) { + printf("Failed to enable usb phy clock\n"); + return ret; + } +#endif + + /* Disable rx term override */ + value = readl(imx_phy->base + PHY_CTRL6); + value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + + return 0; +} + +static int imx8mq_usb_phy_power_off(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + /* Override rx term to be 0 */ + value = readl(imx_phy->base + PHY_CTRL6); + value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imx_phy->phy_clk); +#endif + + return 0; +} + +static int imx8mq_usb_phy_exit(struct phy *usb_phy) +{ + return imx8mq_usb_phy_power_off(usb_phy); +} + +struct phy_ops imx8mq_usb_phy_ops = { + .init = imx8mq_usb_phy_init, + .power_on = imx8mq_usb_phy_power_on, + .power_off = imx8mq_usb_phy_power_off, + .exit = imx8mq_usb_phy_exit, +}; + +int imx8mq_usb_phy_probe(struct udevice *dev) +{ + struct imx8mq_usb_phy *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + if (!priv->base) + return -EINVAL; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + /* Assigned clock already set clock */ + ret = clk_get_by_name(dev, "phy", &priv->phy_clk); + if (ret) { + printf("Failed to get usb phy clock\n"); + return ret; + } +#endif + + return 0; +} + +U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = { + .name = "nxp_imx8mq_usb_phy", + .id = UCLASS_PHY, + .of_match = imx8mq_usb_phy_of_match, + .probe = imx8mq_usb_phy_probe, + .ops = &imx8mq_usb_phy_ops, + .priv_auto = sizeof(struct imx8mq_usb_phy), +}; -- 2.7.4

6 23

[PATCH] arch: cache: cp15: Add mmu_set_region_dcache_behaviour() when SYS_DCACHE_OFF is enable
by Patrice Chotard 10 Jul '21

10 Jul '21

From: Patrice Chotard <patrice.chotard(a)st.com> Fix following compilation issue when SYS_DCACHE_OFF is enable: drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour' when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be defined. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- arch/arm/lib/cache-cp15.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 24050e5bdd..f1703ead96 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -97,12 +97,6 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, mmu_page_table_flush(startpt, stoppt); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) -{ - mmu_set_region_dcache_behaviour_phys(start, start, size, option); -} - __weak void dram_bank_mmu_setup(int bank) { struct bd_info *bd = gd->bd; @@ -314,6 +308,12 @@ int dcache_status(void) { return 0; /* always off */ } + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ +} + #else void dcache_enable(void) { @@ -329,4 +329,10 @@ int dcache_status(void) { return (get_cr() & CR_C) != 0; } + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} #endif -- 2.17.1

3 2

[PATCH v4] armv8: Handle EL2 Host mode
by Mark Kettenis 10 Jul '21

10 Jul '21

On implementations that support VHE, the layout of the CPTR_EL2 register depends on whether HCR_EL2.E2H is set. If the bit is set, CPTR_EL2 uses the same layout as CPACR_EL1 and can in fact be accessed through that register. In that case, jump to the EL1 code to enable access to the FP/SIMD registers. This allows U-Boot to run on systems that pass control to U-Boot in EL2 with EL2 Host mode enabled such as machines using Apple's M1 SoC. Signed-off-by: Mark Kettenis <kettenis(a)openbsd.org> --- v4: use EL1 codepath when HCR_EL2.E2H is set suggested by Marc Zyngier <maz(a)kernel.org> v2: rename label arch/arm/cpu/armv8/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 662449156b..9e9c6140cd 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -132,11 +132,13 @@ pie_fixup_done: msr cntfrq_el0, x0 /* Initialize CNTFRQ */ #endif b 0f -2: set_vbar vbar_el2, x0 +2: mrs x1, hcr_el2 + tbnz x1, #34, 1f /* HCR_EL2.E2H */ + set_vbar vbar_el2, x0 mov x0, #0x33ff msr cptr_el2, x0 /* Enable FP/SIMD */ b 0f -1: set_vbar vbar_el1, x0 +1: set_vbar vbar_el1, x0 mov x0, #3 << 20 msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: -- 2.30.0

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[PATCH 00/37] imx: hab/caam new feature and update
by Peng Fan (OSS) 08 Jul '21

08 Jul '21

From: Peng <peng.fan(a)nxp.com> This patchset is to upstream NXP downstream caam, hab features One more patch is to update maintainer for imx8mn_evk board. Aymen Sghaier (6): crypto: caam: Add CAAM support to i.MX8M platforms crypto: caam: Fix build warnings pointer casting crypto: Add blob command support for i.MX8M platforms crypto: caam: Fix pointer size to 32bit for i.MX8M crypto: caam: Add secure memory vid 3 support crypto: caam: RNG4 TRNG errata Breno Lima (13): imx: imx7 Support for Manufacturing Protection imx: Avoid hardcoded output ring size register offset (ORSR) imx: Ensure CAAM clock is enabled prior getting out_jr_size imx: Avoid hardcoded Job Ring Max size imx: hab: Enable hab.c to authenticate additional images in open configuration imx: hab: Check if IVT header is HABv4 mx7ulp: hab: Add hab_status command for HABv4 M4 boot imx: hab: Fix build warnings in 32-bit targets crypto: fsl: blob: Flush dcache range for destination address mx6dq: hab: Fix chip version in hab.h code cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency cmd: blob: Instantiate RNG before running CMD_BLOB fsl_mfgprot: Fix typo in sign_mppubk() Clement Faure (2): imx8m: Add DEK blob encapsulation for imx8m imx8: Add DEK blob encapsulation Clement Le Marquis (1): imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3 Franck LENORMAND (3): crypto: caam: change JR running loop caam: enable support for iMX7ULP imx7ulp: Enable support for cmd blob Peng (1): imx8mn: evk: update MAINTAINERS Peng Fan (2): imx8m: add regs used by CAAM imx: HAB: Update hab codes to support ARM64 and i.MX8M Utkarsh Gupta (2): imx: HAB: Validate IVT before authenticating image imx: hab: Display All HAB events via hab_status command Ye Li (7): imx: hab: Add function to authenticate kernel image hab: Change calling to ROM API failsafe imx: HAB: Add support for iMX8MM iMX8M: Add support to enable CONFIG_IMX_HAB imx: cmd_dek: Enable DEK only for chips supporting CAAM crypto: caam: Add fsl caam driver crypto: fsl: refactor for 32 bit version CAAM support on ARM64 arch/arm/Kconfig | 6 + arch/arm/dts/imx8mm-evk-u-boot.dtsi | 7 + arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 6 + arch/arm/dts/imx8mp-evk-u-boot.dtsi | 6 + arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/arch-imx8/image.h | 11 + arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/include/asm/arch-imx8m/imx-regs.h | 10 + arch/arm/include/asm/arch-mx7/crm_regs.h | 8 + arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 12 + arch/arm/include/asm/mach-imx/hab.h | 37 +- arch/arm/mach-imx/Kconfig | 44 +- arch/arm/mach-imx/Makefile | 3 + arch/arm/mach-imx/cmd_dek.c | 262 ++++++- arch/arm/mach-imx/cmd_mfgprot.c | 150 ++++ arch/arm/mach-imx/hab.c | 417 +++++++++-- arch/arm/mach-imx/imx8/Kconfig | 1 + arch/arm/mach-imx/imx8m/Kconfig | 1 + arch/arm/mach-imx/imx8m/clock_imx8mm.c | 8 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 7 + arch/arm/mach-imx/mx7ulp/Kconfig | 1 + arch/arm/mach-imx/priblob.c | 33 + board/freescale/imx8mn_evk/MAINTAINERS | 3 +- cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/blob.c | 16 + cmd/cmd_fsl_caam.c | 88 +++ doc/imx/habv4/guides/mx6_mx7_secure_boot.txt | 25 + drivers/crypto/Makefile | 1 + drivers/crypto/fsl/Kconfig | 6 + drivers/crypto/fsl/Makefile | 4 +- drivers/crypto/fsl/desc.h | 49 +- drivers/crypto/fsl/desc_constr.h | 28 +- drivers/crypto/fsl/fsl_blob.c | 6 + drivers/crypto/fsl/fsl_hash.c | 6 +- drivers/crypto/fsl/fsl_mfgprot.c | 160 +++++ drivers/crypto/fsl/jobdesc.c | 16 +- drivers/crypto/fsl/jr.c | 53 +- drivers/crypto/fsl/jr.h | 11 +- drivers/crypto/fsl/type.h | 16 + drivers/crypto/fsl_caam.c | 720 +++++++++++++++++++ drivers/crypto/fsl_caam_internal.h | 230 ++++++ include/fsl_caam.h | 24 + include/fsl_sec.h | 54 +- 44 files changed, 2388 insertions(+), 169 deletions(-) create mode 100644 arch/arm/mach-imx/cmd_mfgprot.c create mode 100644 arch/arm/mach-imx/priblob.c create mode 100644 cmd/cmd_fsl_caam.c create mode 100644 drivers/crypto/fsl/fsl_mfgprot.c create mode 100644 drivers/crypto/fsl/type.h create mode 100644 drivers/crypto/fsl_caam.c create mode 100644 drivers/crypto/fsl_caam_internal.h create mode 100644 include/fsl_caam.h -- 2.25.1

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[PATCH v2 0/2] mmc: Add support for checking device number against alias index
by Aswath Govindraju 08 Jul '21

08 Jul '21

The following series of patches, - add support to check for a device with a sequence number equal to device number before looking for matching index - assign device number by reading aliases node's index by using dev_seq Changes since v1: - In patch 2 used dev_seq instead of using dev_read_alias_seq for reading alias index. Aswath Govindraju (2): mmc: Check for device with a seq number equal to num before checking against index mmc: mmc-uclass: Use dev_seq() to read aliases node's index drivers/mmc/mmc-uclass.c | 12 +++++------- drivers/mmc/mmc.c | 8 +++++--- 2 files changed, 10 insertions(+), 10 deletions(-) -- 2.17.1

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