April 2021 - U-Boot

[PATCH] env: Load env when ENV_IS_NOWHERE is only location selected
by Felix.Vietmeyer＠jila.colorado.edu 08 Apr '22

08 Apr '22

This patch prevent u-boot from hanging on a UltraZed EG board (zynqmp). Without the patch, (drv = env_driver_lookup(ENVOP_INIT, prio)) evaluates to 0, causing prio = 0 Then, (!prio) is hit, returning -ENODEV causing a stall. With the patch, instead of returning -ENODEV and causing a stall, we set gd->env_addr (is this really needed?) and then mark gd->env_valid = ENV_INVALID to use the default env. --- env/env.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/env/env.c b/env/env.c index e534008006..44a65ab216 100644 --- a/env/env.c +++ b/env/env.c @@ -335,17 +335,18 @@ int env_init(void) debug("%s: Environment %s init done (ret=%d)\n", __func__, drv->name, ret); - - if (gd->env_valid == ENV_INVALID) - ret = -ENOENT; } - if (!prio) - return -ENODEV; + if (!prio) { + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = ENV_INVALID; + + return 0; + } if (ret == -ENOENT) { gd->env_addr = (ulong)&default_environment[0]; - gd->env_valid = ENV_VALID; + gd->env_valid = ENV_INVALID; return 0; } -- 2.17.1

2 1

[PATCH 0/3] efi_loader: setting boot device
by Heinrich Schuchardt 04 Apr '22

04 Apr '22

Up to now the bootefi command uses the last file loaded to determine the boot partition. This has led to user irritation when the fdt has been loaded from another partition after the EFI binary. Before setting the boot device from a loaded file check if it is a PE-COFF image. The first patch carves out the test function. The second make use of the PE-COFF check. The third add the display of the boot device and file path for easier testing. Heinrich Schuchardt (3): efi_loader: print boot device and file path in helloworld efi_loader: carve out efi_check_pe() efi_loader: setting boot device cmd/bootefi.c | 14 ++- doc/uefi/uefi.rst | 11 +- fs/fs.c | 3 +- include/efi_loader.h | 8 +- lib/efi_loader/efi_image_loader.c | 80 ++++++++------ lib/efi_loader/helloworld.c | 167 ++++++++++++++++++++++++------ net/tftp.c | 9 +- 7 files changed, 211 insertions(+), 81 deletions(-) -- 2.29.2

4 18

[PATCH 00/14] mtd: nand: i.MX update
by Peng Fan 18 Mar '22

18 Mar '22

This is to upstream NXP downstream mtd nand patches, including DT/CLK/i.MX8M/i.MX8/SPL Alice Guo (2): nand: mxs_nand: make imx8mm can use hardware BCH and randomizer nand: enable the Randomizer module for i.mx7 and i.mx8 Han Xu (3): mtd: nand: mxs_nand: add i.MX6QP compatible string mtd: mxs_nand: fix the gf_13/14 definition issue mxs_nand: don't check zero count when ECC reading with randomizer Peng Fan (3): nand: mxs: fix the bitflips for erased page when uncorrectable error nand: mxs: correct bitflip for erased NAND page mtd: nand: support GPMI NAND driver for i.MX8 Ye Li (6): mtd: gpmi: change the BCH layout setting for large oob NAND mtd: gpmi: provide the option to use legacy bch geometry mxs_nand: Add support for i.MX8M nand: Update SPL MXS NAND mini driver mxs_nand: Update compatible string for i.MX6SX MXS_NAND: Add clock support for iMX8 arch/arm/include/asm/mach-imx/dma.h | 15 +- arch/arm/include/asm/mach-imx/regs-apbh.h | 9 +- arch/arm/include/asm/mach-imx/regs-bch.h | 20 +- drivers/dma/Kconfig | 2 +- drivers/dma/apbh_dma.c | 13 +- drivers/mtd/nand/raw/Kconfig | 6 +- drivers/mtd/nand/raw/mxs_nand.c | 291 ++++++++++++++++++++++-------- drivers/mtd/nand/raw/mxs_nand_dt.c | 91 ++++++++++ drivers/mtd/nand/raw/mxs_nand_spl.c | 41 ++++- include/mxs_nand.h | 15 +- 10 files changed, 387 insertions(+), 116 deletions(-) -- 2.16.4

7 36

iMX8MM USB support?
by Tim Harvey 09 Mar '22

09 Mar '22

Peng, It looks like IMX8MM USB support hasn't made it upstream yet. Is this something your working on? I'm interested in booting an IMX8MM via SDP. Best Regards, Tim

7 21

IMX8MM 4GiB boundary issue
by Tim Harvey 28 Feb '22

28 Feb '22

Greetings, I'm working with an IMX8MM board that has 4GiB of DRAM. I've found that in this configuration the MMC driver and FEC network driver appear to have some issues with crossing the 4GiB address space. If I tell U-Boot I have 3GiB everything is ok, but when I set it to 4GiB I see the following: MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Error found for upper 32 bits Error found for upper 32 bits Error found for upper 32 bits *** Warning - No block device, using default environment In: serial Out: serial Err: serial Net: DP83867 Warning: ethernet@30be0000 (eth0) using random MAC address - ea:22:3a:4d:8f:d5 eth0: ethernet@30be0000 [PRIME] Hit any key to stop autoboot: 0 On the FEC ethernet side I don't see any errors reported but ping's fail with 4GiB DRAM. I suspect drivers have 32bit addressing issues as the base of mem for IMX8MM is 1GiB so anything over 3GiB of DRAM runs you over the 32bit boundary. Anyone run into this yet? Marek, I noticed you are the maintainer for the technexion pico-imx8mq which has support for 1, 2, 3, and 4 GiB DRAM. Did you encounter such issues on the 4GiB variant? Best Regards, Tim

5 23

converting IMX6 board to DM_ETH and DM_USB - usb_ether gadget support
by Tim Harvey 10 Feb '22

10 Feb '22

Greetings, I'm trying to convert the gwventana board support to DM_ETH and DM_USB and one item I have not resolved yet is USB Ethernet gadget support. For non-dm a call to 'usb_eth_initialize' creates a usb_ether gadget that can be used for ethernet communication between the IMX6 OTG controller in device mode to a USB host. How is that accomplished via dm? I find that drivers/usb/gadget/ether.c has dm support but it would appear that a controller of UCLASS_USB_GADGET_GENERIC must bind for it to work yet I don't see how this works with CI_UDC. Other IMX6 boards that have gone through dm conversion have simply dropped the call to usb_eth_initialize and I don't see what else they enable that provides this functionality. Any ideas? Best regards, Tim

2 6

IMX8MM SD UHS support
by Tim Harvey 14 Jan '22

14 Jan '22

Greetings, In 50b1a69cee0d ("ARM: dts: imx8m: add UHS or HS400/HS400ES properties") u-boot dt props were added to enable UHS and HS400 on a couple of IMX8MM boards including the imx8mm-evk and in the subsequent patch enabled the config items. While I see this making a huge difference for eMMC performance in U-Boot I find it doesn't do anything for microSD performance. The issue appears to be that sd_get_capabilities() is not appropriately detecting UHS speeds on cards that appropriately detect as SDR104/DDR50 in Linux: u-boot=> mmc info Device: FSL_SDHC Manufacturer ID: 1b OEM: 534d Name: 00000 Bus Speed: 50000000 Mode: SD High Speed (50MHz) card capabilities: widths [4, 1] modes [MMC legacy, SD High Speed (50MHz)] ^^^^ no SDR104 detected for this card host capabilities: widths [4, 1] modes [MMC legacy, MMC High Speed (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz), UHS DDR50 (50MHz), UHS SDR104 (208MHz)] Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.9 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes The same card in Linux shows the following upon insertion and performance tests show that it is operating at SDR104 speeds: mmc1: new ultra high speed SDR104 SDHC card at address 0001 I haven't found very good documentation on the SD switch settings to understand if something is wrong in the U-Boot implementation of of sd_get_capabilities() and I suppose it also could be an issue in sdhci-esdhc-imx.c. Any ideas where to look? Anyone see SDR104 cards being detected properly for other platforms? Best regards, Tim

6 18

[PATCH 0/5] board: mediatek: pumpkin: add fastboot support
by Fabien Parent 16 Dec '21

16 Dec '21

This series adds USB/Fastboot support on MT8516 Pumpkin board. Fabien Parent (5): arm: dts: mt8516: add support for USB arm: dts: mt8516-pumpkin: enable usb port board: mediatek: pumpkin: initialize usb device configs: pumpkin: enable USB gadget configs: pumpkin: enable fastboot arch/arm/dts/mt8516-pumpkin.dts | 10 ++++++++++ arch/arm/dts/mt8516.dtsi | 14 ++++++++++++++ board/mediatek/pumpkin/pumpkin.c | 17 +++++++++++++++++ configs/pumpkin_defconfig | 15 ++++++++++++++- 4 files changed, 55 insertions(+), 1 deletion(-) -- 2.28.0

3 12

[PATCH] clk: fix clk_get_rate() documentation
by Giulio Benetti 15 Dec '21

15 Dec '21

clk_get_rate() can't and doesn't return -ve on error, it actually returns 0 on error or a value greater than 0 on success. So let's fix its documentation. Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- include/clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/clk.h b/include/clk.h index ca6b85fa6f..a833d6a27b 100644 --- a/include/clk.h +++ b/include/clk.h @@ -344,7 +344,7 @@ int clk_free(struct clk *clk); * * @clk: A clock struct that was previously successfully requested by * clk_request/get_by_*(). - * @return clock rate in Hz, or -ve error code. + * @return clock rate in Hz on success, or 0 on error. */ ulong clk_get_rate(struct clk *clk); -- 2.25.1

5 15

[PATCH v2] imx: support i.MX8QM DMSSE20 a1 board
by Oliver Graute 30 Nov '21

30 Nov '21

Add i.MX8QM DMSSE20 a1 board support U-Boot 2021.04-rc1-00070-g30e1471671 (Feb 19 2021 - 09:25:19 +0100) Model: Advantech iMX8QM DMSSE20 Board: DMS-SE20A1 8GB Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF 09c5cc9 Boot: USB DRAM: 8 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000 [PRIME] Warning: ethernet@5b050000 (eth1) using random MAC address - fe:ac:c4:1f:d9:9c , eth1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- Changes for v2 -replaced bd_t with struct bd_info -added missing DTS in MAINTAINERS -replaced README with imx8qm-dmsse20-a1.rst -move CMD_FUSE to Kconfig -removed fdt_high -added i2c support -added rtc support arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8qm-dmsse20-a1.dts | 407 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 7 + board/advantech/imx8qm_dmsse20_a1/Kconfig | 14 + board/advantech/imx8qm_dmsse20_a1/MAINTAINERS | 7 + board/advantech/imx8qm_dmsse20_a1/Makefile | 8 + .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 188 ++++++++ .../advantech/imx8qm_dmsse20_a1/imximage.cfg | 21 + board/advantech/imx8qm_dmsse20_a1/spl.c | 224 ++++++++++ common/Kconfig | 2 +- configs/imx8qm_dmsse20a1_defconfig | 94 ++++ doc/board/advantech/imx8qm-dmsse20-a1.rst | 58 +++ doc/board/advantech/index.rst | 1 + include/configs/imx8qm_dmsse20.h | 187 ++++++++ 14 files changed, 1218 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8qm-dmsse20-a1.dts create mode 100644 board/advantech/imx8qm_dmsse20_a1/Kconfig create mode 100644 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS create mode 100644 board/advantech/imx8qm_dmsse20_a1/Makefile create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c create mode 100644 board/advantech/imx8qm_dmsse20_a1/imximage.cfg create mode 100644 board/advantech/imx8qm_dmsse20_a1/spl.c create mode 100644 configs/imx8qm_dmsse20a1_defconfig create mode 100644 doc/board/advantech/imx8qm-dmsse20-a1.rst create mode 100644 include/configs/imx8qm_dmsse20.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c64ba90f01..db5e465cd7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ imx8qm-cgtqmx8.dtb \ + imx8qm-dmsse20-a1.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts new file mode 100644 index 0000000000..81ef7fb2ce --- /dev/null +++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Advantech iMX8QM DMSSE20"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-mek { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_rtc_mc_8803: rtc_mc_8803_grp{ + fsl,pins = < + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c + SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020 + SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default","state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + fsl,mii-exclusive; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_mc_8803>; + status = "okay"; + + rv8803@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + 24c02@50 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,24c04"; + reg = <0x50>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 6728d23b6b..0d04ca1939 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -97,6 +97,12 @@ config TARGET_IMX8QM_ROM7720_A1 select SUPPORT_SPL select IMX8QM +config TARGET_IMX8QM_DMSSE20_A1 + bool "Support i.MX8QM DMS-SE20-A1 board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT @@ -107,6 +113,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/congatec/cgtqmx8/Kconfig" +source "board/advantech/imx8qm_dmsse20_a1/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig new file mode 100644 index 0000000000..1d5e68a96f --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_DMSSE20_A1 + +config SYS_BOARD + default "imx8qm_dmsse20_a1" + +config SYS_VENDOR + default "advantech" + +config SYS_CONFIG_NAME + default "imx8qm_dmsse20" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS new file mode 100644 index 0000000000..8292c6ba71 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QM ROM DMSSE20 a1 BOARD +M: Oliver Graute <oliver.graute(a)kococonnector.com> +S: Maintained +F: board/advantech/imx8qm_dmsse20_a1/ +F: arch/arm/dts/imx8qm-dmsse20-a1.dtb +F: include/configs/imx8qm_dmsse20.h +F: configs/imx8qm_dmsse20a1_defconfig diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile new file mode 100644 index 0000000000..262ffcd683 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_dmsse20_a1.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c new file mode 100644 index 0000000000..c3c407e355 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * Copyright (C) 2020 Oliver Graute <oliver.graute(a)kococonnector.com> + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +/* #include <power-domain.h> */ + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + /* This is needed to because Kernel do not Power Up DC_0 */ + sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) + +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) + +static void board_gpio_init(void) +{ + /* Enable BB 3V3 */ + gpio_request(BB_GPIO_3V3_1, "bb_3v3_1"); + gpio_direction_output(BB_GPIO_3V3_1, 1); + gpio_request(BB_GPIO_3V3_2, "bb_3v3_2"); + gpio_direction_output(BB_GPIO_3V3_2, 1); + gpio_request(BB_GPIO_3V3_3, "bb_3v3_3"); + gpio_direction_output(BB_GPIO_3V3_3, 1); + + /* enable LVDS SAS boards */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable MIPI SAS boards */ + gpio_request(MIPI_ENABLE, "mipi_enable"); + gpio_direction_output(MIPI_ENABLE, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: DMS-SE20A1 8GB\n"); + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + if (IS_ENABLED(CONFIG_XEN)) { + /* Clear magic number to let xen know uboot is over */ + writel(0x0, (void __iomem *)0x80000000); + return; + } +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "DMS-SE20A1"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg new file mode 100644 index 0000000000..e324c7ca37 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c new file mode 100644 index 0000000000..06bb049c3a --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <fsl_esdhc.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +void init_clk_usdhc(u32 index); +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); +int arch_cpu_init(void); +int board_early_init_f(void); +int timer_init(void); +void board_init_r(gd_t *id, ulong dest_addr); + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void spl_board_init(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) + puts("Warning: failed to initialize FSPI0\n"); + } +#endif + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) + puts("Warning: failed to turn off FSPI0\n"); + } +#endif +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/common/Kconfig b/common/Kconfig index 2bce8c9ba1..8ccd2befd4 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -445,7 +445,7 @@ config BOARD_TYPES config DISPLAY_CPUINFO bool "Display information about the CPU during start up" - default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K + default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K help Display information about the CPU that U-Boot is running on when U-Boot starts up. The function print_cpuinfo() is called diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig new file mode 100644 index 0000000000..2d828f53f6 --- /dev/null +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_IMX8QM_DMSSE20_A1=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_OFFSET=0x80000 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/advantech/imx8qm_dmsse20_a1/imximage.cfg" +CONFIG_OF_CONTROL=y +CONFIG_CI_UDC=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_FS_EXT4=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FUSE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_MISC=y +CONFIG_SMC_FUSE=y +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_TINY_MEMSET=y +CONFIG_AHAB_BOOT=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV8803=y +CONFIG_CMD_DATE=y diff --git a/doc/board/advantech/imx8qm-dmsse20-a1.rst b/doc/board/advantech/imx8qm-dmsse20-a1.rst new file mode 100644 index 0000000000..d6765ce77f --- /dev/null +++ b/doc/board/advantech/imx8qm-dmsse20-a1.rst @@ -0,0 +1,58 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NXP i.MX8QM DMSSE20-a1 board +============================ + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ cd imx-atf/ + $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga + $ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin + $ chmod +x imx-sc-firmware-1.1.bin + $ ./imx-sc-firmware-1.1.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin + $ chmod +x firmware-imx-8.0.bin + $ ./firmware-imx-8.0.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 + $ tar -xf imx-sc-firmware-1.1.tar.bz2 + $ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 + $ tar -xf firmware-imx-8.0.tar.bz2 + $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + +Build U-Boot +------------ +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make imx8qm_dmsse20a1_defconfig + $ make u-boot.bin + $ make flash.bin diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst index e9b198c5c3..125b98c1f7 100644 --- a/doc/board/advantech/index.rst +++ b/doc/board/advantech/index.rst @@ -7,3 +7,4 @@ Advantech :maxdepth: 2 imx8qm-rom7720-a1.rst + imx8qm-dmsse20-a1.rst diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h new file mode 100644 index 0000000000..e1dca2de90 --- /dev/null +++ b/include/configs/imx8qm_dmsse20.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2019 NXP + */ + +#ifndef __IMX8QM_DMSSE20_H +#define __IMX8QM_DMSSE20_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#define CONFIG_REMAKE_ELF + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ + +#define CONFIG_NR_DRAM_BANKS 4 + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ + +/* ENET0 connects AR8031 on CPU board */ +#define CONFIG_FEC1_ENET_DEV 0 + +/* ENET1 connects AR8031 on CPU board */ +#define CONFIG_FEC2_ENET_DEV 1 +#define CONFIG_FEC_MXC_PHYADDR 0x4 +#define IMX_FEC_BASE 0x5B040000 +/* FEC1 */ +#define IMX_FEC1_BASE 0x5B040000 +#define CONFIG_FEC1_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME "eth0" +/* FEC2 */ +#define IMX_FEC2_BASE 0x5B050000 +#define CONFIG_FEC2_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME1 "eth1" + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-dmsse20-a1.dtb\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 0 + +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x080000000 +#define PHYS_SDRAM_1 0x080000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* #define CONFIG_OF_SYSTEM_SETUP */ + +#endif /* __IMX8QM_DMSSE20_H */ -- 2.17.1

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